OptimoDE: Programmable Accelerator Engines Through Retargetable Customization

Transcription

1 OptimoDE: Programmable Accelerator Engines Through Retargetable Customization Nathan Clark, Hongtao Zhong, Kevin Fan, Scott Mahlke CCCP Research Group University of Michigan Krisztián Flautner, Koen Van Nieuwenhove ARM Limited

2 OptimoDE Overview OptimoDE A configurable VLIW-styled Data Engine architecture Targeted at intensive data processing Characteristics Very wide performance envelope Power / area / speed tradeoff Exploiting parallelism in applications Unlimited data path configuration options User extensible through ISA customization Semi-automatic design system User-in-the-loop design, retargetable compiler toolchain

3 OptimoDE in a System On Chip SDRAM SDRAM Controller ARM CPU SRAM I/O AHB Bus Matrix Memory Data Control M1 M2 DMA Controller Interrupt Controller S Memory S M switch FIFO S M S S M DATA 1 DATA 2 CTRL Data Engine MEM SoC

4 OptimoDE Architecture Model Function units Registers regs regs Memories interconnect regs interconnect Interconnect I/O ports regs Controller Controller µc Functional Units ALU, ACU, Multipliers Custom Memory RAM ( asynch / synch ) ROM I/O ports addressable handshake protocol Registers Register files Interconnect Direct connection Shared bus Controller All layers required Intra-layer configuration

5 Design Toolchain OptimoDE Library OptimoDE Library ma Definition instantiate User Library User Library Librarian xxxxx xx dct xxxxx ma Evaluation ma.inc ma ma.inc.c 1.inc ma ma.inc.c 2.inc ma.inc.c 3 DesignDE save ma.tmp ISS set target run / profile load #include main() { = dct(); } DEvelop create_resource LOAD LIFETIME

6 Compiler Toolchain DEvelop C Source Description * 1 7 INPUT * * OUTPUT * * * 1 2 * 4 * 3 6 * 8 * 5 * 9 check map compile 7 10 Analysis feedback Microcode Syntax checks Dataflow analysis Match architecture and dataflow graph Optimize code and register use

7 32-point DCT Microarchitecture inport outport acu_1 acu_2 acu_3 rom ram_1 ram_2 alu_1 alu_2 imm_1 imm_2 control 2 Custom FUs, 2 RAM, 1 ROM, 3 ACU, 2 I/O ports Designer responsible for creating custom units manually

8 Retargetable Customization Prototype 2 technologies in OptimoDE Automated ISA customization Retargetable customization to an application-area Customizing for 1 application Programmability Nominally programmable Critical problem Cannot sustain performance across similar applications How well does a custom ISA generalize 5 encryption algorithms, create custom design for each Average loss >80% verses native [MICRO, 2003] Proactive generalization creates a retargetable design

9 Creating Custom Instructions Candidate discovery Identify customization opportunities Examine program DFG Partition DFG at: Memory operations Unprofitable edges Enumerate candidate subgraphs within each partition

10 Grouping and Selection Group candidate subgraphs with same structure Estimate performance and cost for each group Greedily select groups to implement in hardware subject to budget Group 1 Group 2 Cost: 2 Adders Gain: 10,000 Cycles Group 3 Cost: 1 Adder Gain: 1,500 Cycles Cost: 0.5 Adders Gain: 1,000 Cycles Group 4 Cost: 1 Adder Gain: 2,500 Cycles

11 Proactively Generalize Groups Cost-effectively extend group functionality to enable reuse Input 2 Input 1 Wildcard multiple functionality at nodes Input 2 Output Subsumed configurable interconnect to bypass nodes 0xFF >> 0x8 0xFF,- Output Input 1,& >> 0x8, 0x4

12 Native Speedups ARM 926EJ (200 MHz) OptimoDE (333 MHz, 5 Issue: 3 ALU, 1 Mem, 1 Brn) OptimoDE 1 CFU (333 MHz) 6 Speedup Des AES Blowfish Md5 Rc4 SHA

13 Importance of Generalization 7 7 Base Generalized Speedup des-3des 3des-Blowfish 3des-Rc4 3des-AES 3des-Sha Blowfish-3des Blowfish-Blowfish Blowfish-Rc4 Blowfish-AES Blowfish-Sha Rc4-3des Rc4-Blowfish Rc4-Rc4 Rc4-AES Rc4-Sha AES-3des AES-Blowfish AES-Rc4 AES-AES AES-Sha Sha-3des Sha-Blowfish 3des-3des 3des-3des 3des-Blowfish 3des-Blowfish 3des-Rc4 3des-Rc4 3des-AES 3des-AES 3des-Sha 3des-Sha Blowfish-3des Blowfish-3des Blowfish-Blowfish Blowfish-Blowfish Blowfish-Rc4 Blowfish-Rc4 Blowfish-AES Blowfish-AES Blowfish-Sha Blowfish-Sha Rc4-3des Rc4-3des Rc4-Blowfish Rc4-Blowfish Rc4-Rc4 Rc4-Rc4 Rc4-AES Rc4-AES Rc4-Sha Rc4-Sha AES-3des AES-3des AES-Blowfish AES-Blowfish AES-Rc4 AES-Rc4 AES-AES AES-AES AES-Sha AES-Sha Sha-3des Sha-3des Sha-Blowfish Sha-Blowfish Key: application run application designed for Sha-Rc4 Sha-AES Sha-Sha Sha-Rc4 Sha-Rc4 Sha-AES Sha-AES Sha-Sha Sha-Sha

14 1 Designing for a Domain 0.9 Fraction of Native Speedup Attained des AES Blowfish Rc4 Sha Md5 Mean 0 Rc4 Rc4, Sha Blowfish, Rc4, Sha 3des, Blowfish, Rc4, Sha Apps Designed For 3des, AES, Blowfish, Rc4, Sha

15 Case Study - Md5 Speedup CFU Cost Budget (Relative to 32-bit ripple-carry adder)

16 OptimoDE Design for this Point Input 1 Input 2 Input 3 ALU 1 ALU 2 ACU SRAM CFU Input 4 Input 2 Input 1 RF RF RF RF 0x1B 0x5 Input 3 ^ >> << & Control Memory ^ Output Output

17 Die Area Breakdown OptimoDE = 5.5 mm 2 in 0.13 µ ARM 926EJ = 5.0 mm 2 in 0.13 µ ALU 1 ALU 2 ACU SRAM CFU CFU 2% Reg. File and Interconnect 9% Control Memory 11% RF RF RF RF Baseline Design 78% Control Memory Die impact is artificially large because of naïve implementation

18 OptimoDE Conclusions Configurable VLIW-style data engine architecture Automated tools for implementing embedded signal and data processing solutions Automatic retargetable customization Customized design combined with cost-effective generalization Performance programmability - Performance stability across a family of similar applications