Evaluation of Cu Pillar Chemistries

Similar documents
MEPTEC Semiconductor Packaging Technology Symposium

Cu electroplating in advanced packaging

SLIM TM, High Density Wafer Level Fan-out Package Development with Submicron RDL

Optimized Cu plating in fan-out wafer-level packaging MultiPlate: a turnkey solution

TSV Interposer Process Flow with IME 300mm Facilities

Lead-Free Solder Bump Technologies for Flip-Chip Packaging Applications

Enabling Materials Technology for Multi-Die Integration

Ultra Fine Pitch Bumping Using e-ni/au and Sn Lift-Off Processes

Fraunhofer IZM Bump Bonding and Electronic Packaging

Chips Face-up Panelization Approach For Fan-out Packaging

TSV Processing and Wafer Stacking. Kathy Cook and Maggie Zoberbier, 3D Business Development

3DIC Integration with TSV Current Progress and Future Outlook

Electrical and Fluidic Microbumps and Interconnects for 3D-IC and Silicon Interposer

TIN-BASED LEAD-FREE SOLDER BUMPS FOR FLIP-CHIP APPLICATION. S. Yaakup, H. S. Zakaria, M. A. Hashim and A. Isnin

UTILIZATION OF ATMOSPHERIC PLASMA SURFACE PREPARATION TO IMPROVE COPPER PLATING PROCESSES.

Thermo-Mechanical Reliability of Through-Silicon Vias (TSVs)

Supplementary Materials for

S/C Packaging Assembly Challenges Using Organic Substrate Technology

Flip Chip Bump Electromigration Reliability: A comparison of Cu Pillar, High Pb, SnAg, and SnPb Bump Structures

SEMI Networking Day 2013 Rudolph Corporate Introduction

3D Package Technologies Review with Gap Analysis for Mobile Application Requirements. Apr 22, 2014 STATS ChipPAC Japan

Notable Trends in CMP: Past, Present and Future

Innovative Substrate Technologies in the Era of IoTs

Interconnect Structure for Room Temperature 3D-IC Stacking Employing Binary Alloying for High Temperature Stability

Simulations and Characterizations for Stress Reduction Designs in Wafer Level Chip Scale Packages

RoHS Compliance Document

Reaction of Sn-Bearing Solders with Nickel-based Under Bump Metallisations

1 mw/[] Bond-Able Post-Passivation Interconnect for Power Management Technologies.

Properties and Barrier Material Interactions of Electroless Copper used for Seed Enhancement

Probing Challenges with Cu Pillar. Phill Mai, JEM America Joe Mai, JEM Europe

INTERCONNECT STRUCTURE FOR ROOM TEMPERATURE 3D-IC STACKING EMPLOYING BINARY ALLOYING FOR HIGH TEMPERATURE STABILITY

An Innovative High Throughput Thermal Compression Bonding Process

1 Thin-film applications to microelectronic technology

THE EFFECTS OF PLATING MATERIALS, BOND PAD SIZE AND BOND PAD GEOMETRY ON SOLDER BALL SHEAR STRENGTH

Developments in low-temperature metal-based packaging

IME Technical Proposal. High Density FOWLP for Mobile Applications. 22 April High Density FOWLP Consortium Forum

Cu Pillar Interconnect and Chip-Package-Interaction (CPI) for Advanced Cu Low K chip

DITF ToolKit 1. Standard Substrate Sizes (selected at the factory for optimum process)

Overview of CMP for TSV Applications. Robert L. Rhoades, Ph.D. Presentation for AVS Joint Meeting June 2013 San Jose, CA

RoHS Compliance Document

Equipment and Process Challenges for the Advanced Packaging Landscape

Challenges and Solutions for Cost Effective Next Generation Advanced Packaging. H.P. Wirtz, Ph.D. MiNaPAD Conference, Grenoble April 2012

Adaption to scientific and technical progress under Directive 2002/95/EC

By Ron Blankenhorn, Pac Tech USA, Santa Clara, Calif., and Thomas Oppert, Pac Tech GbmH, Nauen, Germany

INTERVIA BPP-10 Photoresist

Fluxless soldering using Electron Attachment (EA) Technology

Adaption to scientific and technical progress under Directive 2002/95/EC

Metallization of MID Dec 2 010

3D technologies for integration of MEMS

Shear Strength in Solder Bump Joints for High Reliability Photodiode Packages

In-line Hybrid Metrology Solutions

Thermo-Mechanical FEM Analysis of Lead Free and Lead Containing Solder for Flip Chip Applications

Using Mass Metrology for Process Monitoring and Control During 3D Stacking of IC s

Maximum MAX662 12V DC-DC Converter

Challenges in Material Applications for SiP

1.3.2 Nanotechnology Nanoporosity Deposition Methods Dissolution Methods

28nm Mobile SoC Copper Pillar Probing Study. Jose Horas (Intel Mobile Communications) Amy Leong (MicroProbe) Darko Hulic (Nikad)

WF6317. A superactive low-volatile/high heat-resistant water-soluble flux for ball soldering

Bonding Technologies for 3D-Packaging

RELIABILITY IMPACT OF COPPER-DOPED EUTECTIC TIN-LEAD BUMP AND ITS VOIDING UPON FLIP CHIP ASSEMBLIES

CHALLENGES FACING ELECTROCHEMICAL DEPOSITION IN WAFER LEVEL PACKAGING MAY THOMAS B. RICHARDSON, Ph.D.

Flip Chip - Integrated In A Standard SMT Process

Motorola MC68360EM25VC Communication Controller

CERN/NA62 GigaTracKer Hybrid Module Manufacturing

Ultralow Residue Semiconductor Grade Fluxes for Copper Pillar Flip-Chip

Advanced Analytical Techniques for Semiconductor Assembly Materials and Processes. Jason Chou and Sze Pei Lim Indium Corporation

Investigation of the recommended immersion Tin thickness for Pbfree

A STUDY OF THE ENEPIG IMC FOR EUTECTIC AND LF SOLDERS

A study aimed at characterizing the interfacial structure in a tin silver solder on nickel-coated copper plate during aging

UMC UM F-7 2M-Bit SRAM

Challenges of Fan-Out WLP and Solution Alternatives John Almiranez

Method For Stripping Copper In Damascene Interconnects >>>CLICK HERE<<<

Interfacial Reactions between the Sn-9Zn Solder and Au/Ni/SUS304 Multi-layer Substrate

A Flexible Vertical MEMs Probe Card Technology for Pre-Bump and ewlp Applications

Embedded Mesh Technique for Increased Reliability between Substrate & Baseplate in IGBT Modules

Packaging Effect on Reliability for Cu/Low k Damascene Structures*

SIDE WALL WETTING INDUCED VOID FORMATION DUE TO SMALL SOLDER VOLUME IN MICROBUMPS OF Ni/SnAg/Ni UPON REFLOW

Lead Free Soldering Technology

Copper Wire Packaging Reliability for Automotive and High Voltage

Rockwell R RF to IF Down Converter

Solder Alloy Evolution and Development

3D-WLCSP Package Technology: Processing and Reliability Characterization

JOINT INDUSTRY STANDARD

Effects of Lead on Tin Whisker Elimination

Mosel Vitelic MS62256CLL-70PC 256Kbit SRAM

3D technologies for More Efficient Product Development

Copper Interconnect Technology

Micron Semiconductor MT5C64K16A1DJ 64K x 16 SRAM

IMPLEMENTATION OF A FULLY MOLDED FAN-OUT PACKAGING TECHNOLOGY

Chapter 4 Fabrication Process of Silicon Carrier and. Gold-Gold Thermocompression Bonding

Challenges for Embedded Device Technologies for Package Level Integration

Experience in Applying Finite Element Analysis for Advanced Probe Card Design and Study. Krzysztof Dabrowiecki Jörg Behr

Development of a Fluxless Flip Chip Bonding Process for Optical Military Electronics

Overpad Metallizations and Probe Challenges

HYPRES. Hypres MCM Process Design Rules 04/12/2016

Microbumping technology for Hybrid IR detectors, 10µm pitch and beyond

Future Electronic Devices Technology in Cosmic Space and Electroless Ni/Pd/Au Plating for High Density Semiconductor Package Substrate

The Role Of Electroplates In Contact Reliability

Hi-performance S3X58-M406

CMP for Thru-Silicon Vias TSV Overview & Examples March 2009

Transcription:

Presented at 2016 IMAPS Device Packaging Evaluation of Cu Pillar Chemistries imaps Device Packaging Conference Spring 2016 Matthew Thorseth, Mark Scalisi, Inho Lee, Sang-Min Park, Yil-Hak Lee, Jonathan Prange, Masaaki Imanari, Mark Lefebvre, Jeff Calvert Dow.com

Outline Introduction Cu Pillar Plating with INTERVIA Cu Products RDL Pillars Solder integration Next generation performance Megapillars 50 μm pillars

Background and Introduction SnAg Solder plating SOLDERON BP TS 4000 SnAg SOLDERON BP TS 6000 SnAg ETNA 3D chip stack with DRAM and Logic integration SnAg C4 Bump Cu Through-Si Via INTERLINK 9200 Cu Redistribution Layer Cu INTERVIA 8540 Cu INTERVIA 9000 Cu Cu pillar INTERVIA 8540 Cu INTERVIA 9000 Cu Memory Image courtesy of IMEC Logic Dual Damascene Cu ULTRAFILL 5001 Cu NANOPLATE 5200 Cu Ni Barrier Layer NIKAL BP Ni NIKAL BP 2000 Ni Solders Used for electrical joint formation, previously had been SnPb, shift to SnAg due to environmental concerns Copper Conductor used to carry signals throughout the chip package Nickel Used mainly as a seed & barrier layer to prevent intermetallic mixing at metal/metal interfaces www.dowelectronicmaterials.com 3

Background and Introduction Technology Trend in Packaging SnPb C4 Bump Pb-Free C4 Bump Cu Pillar + Pb-free Cap Cu µ-pillar + Pb-free Cap Structure SnAg SnAg Cu SnAg Cu Diameter 75 200 µm 75 150 µm 50 100 µm 10 30 µm Products SOLDERON BP + NIKAL BP Ni NIKAL BP 2000 Ni SOLDERON BP TS 4000 SnAg SOLDERON BP TS 6000 SnAg + NIKAL BP Ni NIKAL BP 2000 Ni INTERVIA 8540 Cu INTERVIA 9000 Cu + NIKAL BP Ni NIKAL BP 2000 Ni + SOLDERON Products INTERVIA Cu Products + NIKAL Products + SOLDERON Products Old Technology Current Technology Next-Generation Technology www.dowelectronicmaterials.com 4

Process Flow and Design Goals Incoming Wafer PR Si Seed Layer Passivation UBM Electroplating SnAg Ni Cu PR Strip, Seed Layer Etch, Reflow Design Goal RDL Target 20 μm Pillar Target 50 μm Pillar Target %WID Uniformity < 5% < 5% < 5% < 10% 200 μm Pillar Target %TIR Doming -5% to 5% -5% to 5% -5% to 5% -5% to 5% Plating Rate 2 to 12 ASD 4.5 to 12 ASD 4.5 to 18 ASD 20 to 40 ASD Total Doping (C,N,O,S,Cl) Solder Compatibility Void-free w/o Ni Barrier < 20 ppm < 20 ppm < 20 ppm < 20 ppm Void-free w/o Ni Barrier Void-free w/o Ni Barrier Void-free w/o Ni Barrier 5

Definitions Height Max Within-die (WID) Co-planarity Height Min 1 Height Max Height Min % WID 100 2 Height Avg Total Indicated Runout (TIR) Height Center Height Edge Height Center Height Edge % TIR 100 Height Max Dished (-TIR) Flat (0 TIR) Domed (+TIR) 6

300 mm Data INTERVIA Copper Chemistry

Redistribution Layer Pattern Plating at 4.5 ASD IV8540 INTERVIA 8540 Cu Images INTERVIA 9000 Cu Images Feature Size Optical Image Profile Optical Image Profile 5/5 μm line/space comb 50/50 μm line/space comb 100 μm square pad Similar plating performances between chemistries, with slightly less domed profiles with INTERVIA 9000 Cu 50 μm bond pad with 10 μm lines 8

Pillar Plating Performance Across Feature Sizes INTERVIA 8540 Cu Images INTERVIA 9000 Cu Images Pillar Size and Plating Rate Optical Image Profile Pillar Size and Plating Rate Optical Image Profile 20 μm pillar at 8 ASD 20 μm pillar at 8 ASD 50 μm pillar at 14 ASD 50 μm pillar at 14 ASD 75 μm pillar at 14 ASD 75 μm pillar at 14 ASD INTERVIA 9000 Cu pillars have lower doming across all pillar types 9

%WID 40 μm Pitch %TIR 40 μm Pitch INTERVIA 8540 Cu vs. INTERVIA 9000 Cu 20 μm diameter micropillars 20% 15% INTERVIA 8540 INTERVIA 9000 INTERVIA Cu 8540 Images INTERVIA Cu 9000 Images 10% 5% Current Density / ASD Optical Image Profile Dense Pitch Current Density / ASD Optical Image Profile Dense Pitch 0% 8 9 12 14 16 18 9 8 Current Density / ASD 10% INTERVIA 8540 INTERVIA 9000 14 12 5% 0% 8 9 12 14 16 18 18 16 Current Density / ASD 10

%WID 100 μm Pitch %TIR 100 μm Pitch INTERVIA 8540 vs. INTERVIA 9000 50 μm diameter pillars 20% 15% INTERVIA 8540 INTERVIA 9000 INTERVIA 8540 Images INTERVIA 9000 Images 10% 5% Current Density / ASD Optical Image Profile Dense Pitch Current Density / ASD Optical Image Profile Dense Pitch 0% -5% 9 14 16 18 Current Density / ASD 9 14 30% INTERVIA 8540 25% INTERVIA 9000 20% 14 16 15% 10% 5% 0% 9 14 16 18 18 18 Current Density / ASD 11

INTERVIA Cu Megapillar Plating Segment Level INTERVIA 8540 Cu INTERVIA 9000 Cu 18.5 ASD Avg. Plating Rate WID = 3.5% TIR > 10.3% WID = 4.0% TIR = 5.0% 12

Solder Integration with INTERVIA Cu on 20 μm Pillars INTERVIA 8540 Cu 1 Reflow INTERVIA 9000 Cu 10 Reflows High Temperature Storage at 150 C for 125 hr. Minimal voiding at SnAg-Cu interface after multiple reflows and HTS 13

INTERVIA 9000 Cu Integration with Ni and SnAg 20 µm Ø Pillar, 9 ASD, 1x Reflow 50 µm Ø Pillar, 9 ASD, 1x Reflow Solderon BP TS 6000 SnAg Solderon BP TS 6000 SnAg NIKAL BP Ni Solderon BP TS 6000 SnAg Solderon BP TS 6000 SnAg NIKAL BP Ni INTERVIA 9000 INTERVIA 9000 INTERVIA 9000 INTERVIA 9000 w/o Ni w/ 2 µm Ni w/o Ni w/ 2 µm Ni Excellent Compatibility with NIKAL BP Nickel and SOLDERON BP TS 6000 Tin- Silver in both 20 um and 50 um Ø sizes Organic doping (C, O, N, S, Cl) of <20 ppm as measured by SIMS 14

INTERVIA Cu Deposit Summary INTERVIA 8540 and 9000 Copper Chemistry deposits have excellent WID uniformity with superior integration with solder materials Both plating baths deposit pure Cu across a wide range of applications, including RDL, micropillar, pillar, and megapillars INTERVIA 9000 Cu deposits are flatter than INTERVIA 8540 Cu Plating rates of at least 18 ASD (4 μm min -1 ) are achievable with INTERVIA 9000 Cu plating baths Both chemistries deposit Cu with robust Cu-solder interfaces with minimal interfacial voiding, even after HTS at 150 C 15

Next Generation Prototype Chemistries Segment Level Testing

%Spec Total Organic Incorporation 200 μm Megapillar Prototype Chemistry 1 Plating Rate / ASD 20 25 30 40 40 ASD 10% 5% %WID %TIR 50 25 High Speed Cu Prototype INTERVIA 9000 INTERVIA 8540 0% 20 25 30 35 40 Plating Rate / ASD 0 0 20 40 Plating Rate / ASD High purity deposits with both INTERVIA 9000 Cu and new prototype chemistry at plating rates up to 40 ASD Uniform grain size without voiding up to 40 ASD 17

%WID %TIR 50 μm Pillar Prototype Chemistry 2 Plating Rate / ASD Optical Images INTERVIA 9000 Cu Prototype Chemistry 15% 10% 5% 0% INTERVIA 9000 Prototype 14 20-5% 50% 14 20 Plating Rate / ASD INTERVIA 9000 Prototype Similar TIR flat TIR performance in new prototype chemistry to INTERVIA 9000 Cu Significant improvement in WID at high plating rates with new prototype 25% 0% 14 20 Plating Rate / ASD 18

Thank You Trademark of the Dow Chemical Company ( Dow ) or an affiliated company of Dow