Chip Packaging for Wearables Choosing the Lowest Cost Package Alan Palesko alanp@savansys.com (512) 402-9943 www.savansys.com Slide - 1
Agenda Introduction Wearable Requirements Packaging Technologies and Cost Drivers Technology Cost Comparisons Summary Slide - 2
About Timeline 1995: Founded as a spin-off of Microelectronics and Computer Consortium (MCC) in Austin, TX. Began with cost modeling for PCB and MCM fabrication and assembly. 2005: Partnered with TechSearch International to expand line-up of cost models to include electronics packaging. Wire bond, flip chip, fan-in WLP, fan-out WLP, embedded die, etc. 2012: Initiated development of TSV, 2.5D and 3D fabrication and assembly modeling. Customers We have modeled suppliers in: Japan, Malaysia, Taiwan, China, Korea, Finland, and the US. Customers include: semiconductor giants, fabless semiconductor companies, OEMS, system design houses, and more. Our customer base is worldwide, with customers in Asia, Europe and the US. Slide - 3
Cost Modeling For... Cost Reduction/Optimization Size, Yield, and Cost Design Planning New Technology Adoption Cost Analysis Technology Platform and Process Comparison Supply Chain Collaboration Characterize Supplier Capabilities Consistent and Predictable Behavior Slide - 4
In Search of the Optimal Packaging Choice Optimal Product The lowest cost technology choice that meets product requirements Cost OPTIMAL PRODUCT Technology options Slide - 5
Components of Total Cost / Price Labor Cost Capital/Depreciation Cost Material Cost (Consumables and Permanent) Tooling/NRE Cost Scrap / Rework Cost Indirect Labor Cost Factory Overhead Cost Corporate Overhead Cost Profit Margin Risk Factor Direct Cost Indirect Cost Margin Usually Applied as a Percentage On Direct Cost Slide - 6
Example Wearables SMS Audio BioSport In- Ear Headphones Huawei Talkband B2 * Teardown photos by Chipworks Slide - 7
Market Requirements for Wearables Data Collection Sensors Low Cost Small Flexible / Washable / Invisible Water proof / Sweat proof Data Processing and Communication Bluetooth, WIFI, Cellular? Small, but may be rigid Water proof / Sweat proof Shock Resistant Low power Light Bio compatible Slide - 8
Wearables are not Smart Phones Size constraints in all dimensions Not just thin Less data processing requirements Minimal local data processing. Collect data and send off to smart phone, fog, or cloud No access to a battery as large as a cell phone Much tougher physical requirements Flexible, washable, sweat-proof, drop-proof, etc Slide - 9
Total Cost Relationship to Test/Scrap Opportunities Wafer Probe Fabricate Semiconduc tor Wafer Test Dice Scrap Test Complete Product Fabricate Package Test Scrap Bad Die Package Assembly Test Scrap Die & Package Scrap Bad Substrates Traditional Packaging Three opportunities to scrap at three different factories Advanced Packaging Possibly less than three opportunities to scrap Slide - 10
Yield Loss Example Assume following yields for all packages: 90% Die Yield 90% Fabrication Yield 90% Assembly Yield Technology Test/scrap die before assembly? Test/scrap substrate before assembly? Test/scrap after assembly? Cumulative Yield Wire Bond Yes Yes Yes 90% Flip Chip Yes Yes Yes 90% Fan-out WLP Yes No Yes 81% Embedded Die Yes No Yes 81% Fan-in WLP No No Yes 73% Slide - 11
Wire Bond Technology Process Flow 1. Fabricate substrate or leadframe 2. Die bond chip to package (pads face up) 3. Wire bond die pads to substrate/leadframe pads 4. Mold Cost Drivers Wire cost (if gold) Number of wire bonds Package size Summary Almost always the lowest cost option if product requirements (size, performance, etc.) can be met Slide - 12
Flip Chip Technology Process Flow 1. Fabricate substrate 2. Wafer bump die 3. Die bond chip to package (pads face down) 4. Underfill 5. Mold / Lid Cost Drivers Wafer bumping cost Underfill process Substrate cost Summary Good choice for high IO count dies with challenging size requirements Slide - 13
WLP, FOWLP, Embedded Die Technology Process Flow 1. Start with either wafer (fan-in WLP) or die (fan-out WLP, embedded) 2. Place die on tape or partially completed organic substrate 3. Add RDL for interconnect to die Cost Drivers Compound yield loss RDL process Summary Best option to meet difficult miniaturization requirements Suitable for small die Slide - 14
Activity Based Cost Modeling Cost Components of each Activity The time required to complete the activity The amount of labor dedicated to the activity The cost of material required to perform that activity both consumable and permanent material Any tooling cost The depreciation cost of the equipment required to perform the activity The yield loss associated with the activity Sample Output Substrate Labor Material Capital Tooling Yield Macro Running Total 2-[IL-Core] $0.0007 $0.2000 $0.0007 $0.0000 $0.0000 $0.0000 $0.2014 3-[IL-Photoresist] $0.0007 $0.0120 $0.0011 $0.0000 $0.0000 $0.0000 $0.2152 4-[IL - Image] $0.0007 $0.0144 $0.0045 $0.0000 $0.0000 $0.0000 $0.2349 5-[IL-DES] $0.0009 $0.0072 $0.0088 $0.0000 $0.0000 $0.0000 $0.2517 6-[IL - Oxide] $0.0010 $0.0001 $0.0026 $0.0000 $0.0000 $0.0000 $0.2554 7-[IL-AOI]-[Setup] $0.0001 $0.0000 $0.0006 $0.0000 $0.0000 $0.0000 $0.2561 7-[IL-AOI]-[Test] $0.0025 $0.0000 $0.0099 $0.0000 $0.0000 $0.0000 $0.2686 Slide - 15
Total Package Cost Trade Off Scenario 1 Packaging Technology vs. Package Size $2.50 Cost Comparison.2 defects/sq.cm DD $2.00 $1.50 Key Takeaways WLP has largest slope due to increasing yield fallout FC high because wafer bumping is required $1.00 $0.50 $0.00 3.5mmx3.5mm Package - WLP 4mmx4mm Package - 5mmx5mm Package - 100 IO 5.5mmx5.5mm Package - WLP 6mmx6mm Package - 7mmx7mm Package - 225 IO 7.5mmx7.5mm Package - WLP 8mmx8mm Package - 9mmx9mm Package - 400 IO WLP $0.09 $0.23 $0.46 9.5mmx9.5mm Package - WLP 10mmx10mm Package - 11mmx11mm Package - 625 IO 11.5mmx11.5mm Package - WLP 12mmx12mm Package - 13mmx13mm Package - 900 IO 13.5mmx13.5mm Package - WLP 14mmx14mm Package - 15mmx15mm Package - 1225 IO FOWLP $0.12 $0.25 $0.44 $0.69 $1.02 $1.44 FC PBGA $0.22 $0.40 $0.68 $1.06 $1.48 $2.08 PBGA $0.17 $0.29 $0.44 $0.65 $0.94 $1.24 Slide - 16
Trade Off Scenario 2 Effect of Die Size on Package Cost Key Takeaways relatively flat since package size and number of s drives cost FC very dependent due to wafer bumping costs FOWLP decreases due to less mold (larger die displaces more mold). Also assumes only 1 RDL required. Slide - 17
Summary Wire bond technology is almost always lowest cost WLP and Embedded die are smallest package but limited to small die Package Technology Sensitivity Wire Bond Not particularly sensitive to die or package size FOWLP Sensitive to package size but not die size Flip Chip Sensitive to both die size (wafer bumping) and package size (expensive substrate) Slide - 18
BACKUP Slide - 19
Total Package Cost Trade Off Scenario 3 Packaging Technology vs. Package Size $2.50 Cost Comparison.5 defects/sq.cm DD $2.00 $1.50 $1.00 $0.50 $0.00 3.5mmx3.5mm Package - WLP 4mmx4mm Package - 5mmx5mm Package - 100 IO 5.5mmx5.5mm Package - WLP 6mmx6mm Package - 7mmx7mm Package - 225 IO 7.5mmx7.5mm Package - WLP 8mmx8mm Package - 9mmx9mm Package - 400 IO WLP $0.10 $0.25 $0.55 9.5mmx9.5mm Package - WLP 10mmx10mm Package - 11mmx11mm Package - 625 IO 11.5mmx11.5mm Package - WLP 12mmx12mm Package - 13mmx13mm Package - 900 IO 13.5mmx13.5mm Package - WLP 14mmx14mm Package - 15mmx15mm Package - 1225 IO FOWLP $0.13 $0.25 $0.44 $0.69 $1.02 $1.44 FC PBGA $0.22 $0.41 $0.70 $1.10 $1.57 $2.25 PBGA $0.17 $0.29 $0.44 $0.65 $0.96 $1.27 Slide - 20
Total Package Cost Trade Off Scenario 4 Packaging Technology vs. Package Size $2.50 Cost Comparison.01 defects/sq.cm DD $2.00 $1.50 $1.00 $0.50 $0.00 3.5mmx3.5mm Package - WLP 4mmx4mm Package - 5mmx5mm Package - 100 IO 5.5mmx5.5mm Package - WLP 6mmx6mm Package - 7mmx7mm Package - 225 IO 7.5mmx7.5mm Package - WLP 8mmx8mm Package - 9mmx9mm Package - 400 IO WLP $0.09 $0.21 $0.41 9.5mmx9.5mm Package - WLP 10mmx10mm Package - 11mmx11mm Package - 625 IO 11.5mmx11.5mm Package - WLP 12mmx12mm Package - 13mmx13mm Package - 900 IO 13.5mmx13.5mm Package - WLP 14mmx14mm Package - 15mmx15mm Package - 1225 IO FOWLP $0.12 $0.25 $0.44 0.6902 1.0162 1.4316 FC PBGA $0.21 $0.40 $0.67 $1.03 $1.41 $1.95 PBGA $0.17 $0.29 $0.44 $0.64 $0.93 $1.21 Slide - 21
Total Package Cost Trade Off Scenario 5 Packaging Technology vs. Package Size $2.50 Cost Comparison.05 defects/sq.cm DD $2.00 $1.50 $1.00 $0.50 $0.00 3.5mmx3.5mm Package - WLP 4mmx4mm Package - 5mmx5mm Package - 100 IO 5.5mmx5.5mm Package - WLP 6mmx6mm Package - 7mmx7mm Package - 225 IO 7.5mmx7.5mm Package - WLP 8mmx8mm Package - 9mmx9mm Package - 400 IO WLP $0.09 $0.22 $0.42 9.5mmx9.5mm Package - WLP 10mmx10mm Package - 11mmx11mm Package - 625 IO 11.5mmx11.5mm Package - WLP 12mmx12mm Package - 13mmx13mm Package - 900 IO 13.5mmx13.5mm Package - WLP 14mmx14mm Package - 15mmx15mm Package - 1225 IO FOWLP $0.12 $0.25 $0.44 $0.69 $1.02 $1.43 FC PBGA $0.22 $0.40 $0.67 $1.03 $1.43 $1.98 PBGA $0.17 $0.29 $0.44 $0.64 $0.93 $1.22 Slide - 22