Enabling Materials Technology for Multi-Die Integration

Similar documents
Novel Materials and Activities for Next Generation Package. Hitachi Chemical., Co.Ltd. Packaging Solution Center Hiroaki Miyajima

TSV Interposer Process Flow with IME 300mm Facilities

Avatrel Stress Buffer Coatings: Low Stress Passivation and Redistribution Applications

Evaluation of Cu Pillar Chemistries

Material based challenge and study of 2.1, 2.5 and 3D integration

Low Temperature Curable Positive Tone Photosensitive Polyimide Photoneece LT series. Toray Industries, Inc.

Next Gen Packaging & Integration Panel

SLIM TM, High Density Wafer Level Fan-out Package Development with Submicron RDL

TSV Processing and Wafer Stacking. Kathy Cook and Maggie Zoberbier, 3D Business Development

Ultralow Residue Semiconductor Grade Fluxes for Copper Pillar Flip-Chip

MEPTEC Semiconductor Packaging Technology Symposium

Chips Face-up Panelization Approach For Fan-out Packaging

Fraunhofer IZM Bump Bonding and Electronic Packaging

Ultra Fine Pitch Bumping Using e-ni/au and Sn Lift-Off Processes

Henkel Enabling Materials for Semiconductor and Sensor Assembly. TechLOUNGE, 14 November 2017

IMPLEMENTATION OF A FULLY MOLDED FAN-OUT PACKAGING TECHNOLOGY

3DIC Integration with TSV Current Progress and Future Outlook

FABRICATION AND RELIABILITY OF ULTRA-FINE RDL STRUCTURES IN ADVANCED PACKAGING BY EXCIMER LASER ABLATION

Die Attach Materials. Die Attach G, TECH. 2U. TECHNICAL R&D DIV.

SUSS SOLUTIONS FOR LARGE FORMAT PATTERNING UV Scanning Lithography and Excimer Laser Ablation

An Innovative High Throughput Thermal Compression Bonding Process

Molding materials performances experimental study for the 3D interposer scheme

3D-IC Integration using D2C or D2W Alignment Schemes together with Local Oxide Reduction

Cu electroplating in advanced packaging

By Ron Blankenhorn, Pac Tech USA, Santa Clara, Calif., and Thomas Oppert, Pac Tech GbmH, Nauen, Germany

Selection and Application of Board Level Underfill Materials

CYCLOTENE* 4000 Series Advanced Electronic Resins (Photo BCB)

IME Technical Proposal. High Density FOWLP for Mobile Applications. 22 April High Density FOWLP Consortium Forum

The Effect of Fillers in Nonconductive Adhesive on the Reliability of Chip-on-Glass Bonding with Sn/Cu Bumps

Hot Chips: Stacking Tutorial

Dow Corning WL-5150 Photodefinable Spin-On Silicone

Overview of CMP for TSV Applications. Robert L. Rhoades, Ph.D. Presentation for AVS Joint Meeting June 2013 San Jose, CA

Photolithography I ( Part 2 )

Recent Advances in Die Attach Film

Challenges and Solutions for Cost Effective Next Generation Advanced Packaging. H.P. Wirtz, Ph.D. MiNaPAD Conference, Grenoble April 2012

Thin Wafers Bonding & Processing

Equipment and Process Challenges for the Advanced Packaging Landscape

WF6317. A superactive low-volatile/high heat-resistant water-soluble flux for ball soldering

Optical Profilometry of Substrate Bow Reduction Using Temporary Adhesives

Flip Chip - Integrated In A Standard SMT Process

125nXT Series. EMD PeRFoRmaNce MaTeRIaLs. technical datasheet. Photopolymer Negative Tone Photoresists APPLICATION TYPICAL PROCESS THICKNESS GRADES

Glass Carrier for Fan Out Panel Level Package

Innovative Substrate Technologies in the Era of IoTs

WS-575-C-RT. Halogen-Free Ball-Attach Flux PRODUCT DATA SHEET

3D Package Technologies Review with Gap Analysis for Mobile Application Requirements. Apr 22, 2014 STATS ChipPAC Japan

Frank Wei Disco Corporation Ota-ku, Tokyo, Japan

Cu Pillar Interconnect and Chip-Package-Interaction (CPI) for Advanced Cu Low K chip

Embedded Cooling Solutions for 3D Packaging

Fundamentals of Sealing and Encapsulation

Overview of Dual Damascene Cu/Low-k Interconnect

Low Temperature Dielectric Deposition for Via-Reveal Passivation.

Properties and Barrier Material Interactions of Electroless Copper used for Seed Enhancement

Challenges of Fan-Out WLP and Solution Alternatives John Almiranez

A NOVEL HIGH THERMAL CONDUCTIVE UNDERFILL FOR FLIP CHIP APPLICATION

Optimized Cu plating in fan-out wafer-level packaging MultiPlate: a turnkey solution

Metallizing High Aspect Ratio TSVs For MEMS Challenges and Capabilities. Vincent Mevellec, PhD

5. Packaging Technologies Trends

Chapter 4 Fabrication Process of Silicon Carrier and. Gold-Gold Thermocompression Bonding

UTILIZATION OF ATMOSPHERIC PLASMA SURFACE PREPARATION TO IMPROVE COPPER PLATING PROCESSES.

Photoneece PW-1200 series

TECHNICAL DATA SHEET DESCRIPTION PHYSICAL CHARACTERISTICS PRODUCT CHARACTERISTICS ETERTEC PR8200Y1 PHOTO-IMAGEABLE COVERLAY

Electrical and Fluidic Microbumps and Interconnects for 3D-IC and Silicon Interposer

/15/$ IEEE Electronic Components & Technology Conference

EPOXY FLUX MATERIAL AND PROCESS FOR ENHANCING ELECTRICAL INTERCONNECTIONS

Panel Discussion: Advanced Packaging

DuPont MX5000 Series

Advanced Analytical Techniques for Semiconductor Assembly Materials and Processes. Jason Chou and Sze Pei Lim Indium Corporation

TGV and Integrated Electronics

Towards Industrialization of Fan-out Panel Level Packaging

Challenges for Embedded Device Technologies for Package Level Integration

Henkel Adhesive Solutions for SiP Packaging. October 17-19, 2018 Shanghai, China

Technical Data Sheet Technisches Datenblatt

II. A. Basic Concept of Package.

CERN/NA62 GigaTracKer Hybrid Module Manufacturing

Assembly Reliability of TSOP/DFN PoP Stack Package

S/C Packaging Assembly Challenges Using Organic Substrate Technology

Chapter 2 Manufacturing Process

Anisotropic Conductive Films (ACFs)

Novel Polysulfide Substrates for Flexible Electronics. Tolis Voutsas, Ph.D. VP, Business Development Ares Materials, Inc.

Rapid Cleaning Using Novel Processes With Coa7ngs

3D technologies for integration of MEMS

micro resist technology

INTERVIA BPP-10 Photoresist

EE 527 MICROFABRICATION. Lecture 15 Tai-Chang Chen University of Washington EE-527 M4 MASK SET: NPN BJT. C (sub) A E = 40 µm x 40 µm

Hi-performance S3X58-M406

3D & 2½D Test Challenges Getting to Known Good Die & Known Good Stack

3D-WLCSP Package Technology: Processing and Reliability Characterization

The Role of Wafer Bonding in 3D Integration and Packaging

High Reliable Non-Conductive Adhesives for Flip Chip CSP Applications

ALPHA OM-5100 FINE PITCH SOLDER PASTE

Chapter 3 Silicon Device Fabrication Technology

CLAD MATERIAL ~ FINE CLAD is a solution for high density, low cost PWB.

Photoresist Coat, Expose and Develop Laboratory Dr. Lynn Fuller

Filling and Planarizing Deep Trenches with Polymeric Material for Through-Silicon Via Technology

Bonding Technologies for 3D-Packaging

Lithography Tool Package

Basic PCB Level Assembly Process Methodology for 3D Package-on-Package

SU Permanent Epoxy Negative Photoresist PROCESSING GUIDELINES FOR:

SEMI Networking Day 2013 Rudolph Corporate Introduction

Via Formation Process for Smooth Copper Wiring on Insulation Layer with Adhesion Layer

Transcription:

Enabling Materials Technology for Multi-Die Integration Dr. Jeffrey M. Calvert Global R&D Director, Advanced Packaging Technologies Dow Electronic Materials 455 Forest St., Marlborough, MA 01752 USA jcalvert@dow.com Dow.com

Outline Introduction Key Materials Needs and Challenges Enabling Materials Solutions Dielectrics Temporary Wafer Bonding Adhesive Non-Conductive Film Cu TSV Filling Summary 2

Drivers for Multi-Die Integration Flip-chip, wafer-level and 2.5D/3D packages are the market drivers for advanced packaging Key Drivers for 2.5D/3D Packaging Cost and complexity of scaling ( More Moore ) Demand for Increased Performance and Functionality ( More than Moore ) 3D Packaging is a complex landscape of many different package architectures, integration approaches diverse materials needs, uncertain insertion timing Global Roadmap for 3D Integration with TSV Graphic courtesy of Yole Developpement Graphic courtesy of Yole Developpement 3

Key Material Challenges for 3D Packaging Graphic courtesy of Yole Developpement High AR Cu via filling, planarization Fine pitch bump metallization (solder, Cu pillar) Low stress/low cure temperature dielectrics Improved bond/de-bond adhesives New underfill technology Thermal management 4

Dow s Enabling Materials for 3D-TSV Copper Damascene Pb-free Bump Plating Copper TSV Redistribution Copper Copper Pillars Metallization ETNA 3D chip stack with DRAM and Logic integration Memory Logic Process Chemicals Bump Plating, Etching Photoresists Ancillaries (Developers, Removers, Adhesion Promoters) Bonding Adhesive Layers (Temporary, Permanent) Dielectrics/ Photoresists Photodielectric Underfill Material (CUF, NCF) Bonding/ Assembly Materials 5

Outline Introduction Key Materials Needs and Challenges Enabling Materials Solutions Dielectrics Temporary Wafer Bonding Adhesive Non-Conductive Film Cu TSV Filling Summary 6

Dielectric Material Requirements Dielectrics for fine-pitch RDL, FI/FOWLP, stress buffers, embedded architectures have increasingly demanding technical requirements Low dielectric constant, Low dielectric loss High thermal stability, Low-temperature cure processing Fine geometry patterning Process flexibility (coating, patterning, development) Low moisture uptake Robust mechanical properties and chemical stability Tunable viscoelastic properties (planarization, gapfilling) High reliability New dielectric material developments High resolution, low stress, aqueous-developable (AD-BCB) dielectric Toughened BCB-based dielectrics Conventional photo or laser patternability Spin-on or dry film coating 7

AD-BCB Dielectric Material (Litho Performance) After Develop After 200 o C Cure FT: 6.5µm after SB (90 o C/90s) Spin-apply, 1200 rpm i-line stepper, E size @ 500mJ/cm 2 0.26N TMAH, 60sec, SSP Curing: 130 C/30min // 200 C/100min (<100ppm O 2 ) 10µm Via, 1:2 Pitch 5µm Via, 1:2 Pitch CYCLOTENE TM 6505 AD-BCB Photodielectric Positive-tone, Aqueous developable High-resolution patterning with conventional litho Extendible to 2µm patterning in 3.3µm FT κ = 3.2, tan δ = 0.015, V b >5MV/cm Rapid moisture desorption Weight Change (%) 2µm Via, 1:2 Pitch (3.3µm FT) Humidity cycling at 23 C (0-45% RH) Relative Humidity (%) Time (min) 8

AD-BCB Dielectric Material (Stress Reduction) -16% CYCLOTENE 6505 68.1 µm XP Low Stress 59.2 µm (-15%) CYCLOTENE 302x/402x Resin CYCLOTENE 6505 XP Low Stress Film stress: Toho Flexus Wafer Bow: Optical Profilometry New XP Photodielectric has lower residual film stress vs. commercial CYCLOTENE products (BCB or AD-BCB-based materials) Lower stress comparable reduction in wafer bow Litho performance of lower stress XP material similar to CYCLOTENE 6505 AD-BCB photodielectric CYCLOTENE 6505 (ADI) XP Low Stress (ADI) i-line exposure, 6.5 µm FT, TMAH develop 25.3 µm 10.2 µm 5.2 µm 25.0 µm 10.1 µm 5.0 µm 25µm Via 10µm Via 5µm Via 9

AD-BCB Dielectric Material (Reliability) CYCLOTENE 4022 or 6505 B ECD Cu (5µm) Sputtered Cu (0.3µm) Ti (UBM 0.05µm) Si Substrate CYCLOTENE 6505 CYCLOTENE 4022-35 A Au SnAgCu Ni Optical microscopy after HAST (30µm dielectric linewidth) Electrical resistivity >1E+12 Ω-cm, unchanged after 96hrs @ 130 o C / 85% RH / 5V bias Cu Cu RDL Layer 1 CYCLOTENE 6505 RDL Layer 2 SiN x Si Al Highly accelerated stress testing (HAST) of CYCLOTENE 6505 AD-BCB photodielectric shows no evidence of dendrite formation or electromigration Underfilled flipchip package with CYCLOTENE 6505 photodielectric passes MSL-3, TCT >1000 cycles from -55 C to +125 C 10

Toughened BCB-based Dielectric Materials Same BCB polymer resin as in CYCLOTENE 3000 and 4000 series dielectric materials Same low dielectric and low loss properties (2.65, 0.0008) Same low curing temp w/o outgassing Same low moisture uptake Same high thermal and chemical stability Dry etch or negative tone/solvent developable Modified BCB formulations offer new/improved features: Coating by spin-apply or lamination (dry film) Film thickness to >100µm Tunable mechanical properties High elongation to break (to >35%) Dry etch or neg. tone/solvent developable or laser patternable Long pot life: E gel unchanged after 30 days at RT Stress (MPa) 100.00 80.00 60.00 40.00 20.00 0.00 0 10 20 30 40 % Strain Elongation >35% achievable Flexible, transparent ~75µm thick freestanding toughened BCB film 11

Toughened BCB-based Dielectric Materials (Litho) Spin-on Version Dry Film Version Spincoat AP9000S Adh. Promoter, SB 90 C/90s Nominal 10µm FT Dielectric on PET backsheet Spincoat toughened BCB Photodielectric, SB 90 C/90s Vacuum or Hot roll lamination onto Si or glass i-line or BB exposure i-line or BB exposure PEB 90 C/90s PEB 90 C/90s Solvent develop (DS-2100), Single puddle 15s Solvent develop (DS-2100), Triple puddle 30s PDB, SB 90 C/30s PDB, SB 90 C/60s Std. low O 2 BCB curing process Std. low O 2 BCB curing process Lithographic performance (FT = 6.5µm) Lithographic performance (FT = 10µm) 85 5 µm Via 10 µm Via 10 µm Via 15µm Via 20 µm Via 25 µm Via 20µm Via 25µm Via 12

Toughened BCB-based Dielectric Materials (Laser) Via Pattern Pad Pattern Via Pad XP toughened BCB photodielectric coated onto 330mm PET backing w/ PE cover sheet Exposures performed using Süss MicroTec Photonics Systems - 248nm Laser System Pattern resolution to 7µm L/S demonstrated in 10µm thick dielectric film Laser ablation residue is cleanly removed using standard 0.26N TMAH developer 13

Dielectric Materials Summary CYCLOTENE 6505 Photodielectric product High resolution, positive-tone litho Compatibility with aqueous track processing (TMAH develop) High reliability performance, typical of BCB-based dielectric materials XP Low Stress Photodielectric High resolution patterning and aqueous processability ~15% lower residual stress, leading to reduced wafer bow XP Toughened BCB-based dielectrics Retain desirable electrical, thermal and other material properties of BCB Plus much improved mechanical properties And greater process flexibility Spin-on or dry film coating Conventional litho or laser patternability 14

Outline Introduction Key Materials Needs and Challenges Enabling Materials Solutions Dielectrics Temporary Wafer Bonding Adhesive Non-Conductive Film Cu TSV Filling Summary 15

Temporary Wafer Bonding (TWB) Adhesive XP-130215 TWB Adhesive Based on Dow s benzocyclobutene (BCB) resin technology; BCB is wellestablished in manufacturing as a permanent bonding adhesive material Designed for bond-debond applications ranging from planar/low topography structures to C4 bumps Coating thicknesses to >100µm. Rapid, low temperature curing process Cured film has high thermal (300 o C) and chemical stability Room temperature, mechanical debonding Compatible with wafer thinning and backside integration processes 16

TWB Overall Process Flow Full Thickness Bumped Device Wafer Carrier Wafer Spin-on Temporary Bonding Adhesive High-Throughput Bonding Spin-on Adhesion Promoter Thinning and Backside Processing RT Mechanical Lift-off from Device Wafer Tape-Peel Adhesive from Carrier Thinned TSV Device Wafer Reclaimed Carrier 17

TWB Adhesive Application Process Flip Wafer Device Wafer Spin Coat Thermoset Adhesive 35 sec Soft Bake & Pre-Cure 120 o C, 2 min + 180-210 o C, 2-5 min Thermocompression Bond Post-Bond Cure (N 2 atmosphere) 100 o C, 10 kn, 30 sec 210 o C 2 ~ 4 min Carrier Wafer Spin Coat Soft Bake Adhesion Promoter Adhesion Promoter 15 sec 120 o C, 1 min Process Flow diagram courtesy of Süss MicroTec Total process time in bonding chamber: <2min Enables high wafer throughput 18

TWB Adhesive Performance (Coating, TTV) After Coating (Flat Si) After Bonding (Flat Si) After Thinning (Flat Si) 25.6 µm FT; TTV = 0.36µm 25.6 µm FT; TTV = 3.2µm Thinned (50mm) Wafer; TTV = 2.3 µm After Bonding (Flat Si) After Coating (Cu Pillar) After Thinning (Cu Pillar) CSAM: Void-Free Defect-Free Coating, 25mm Cu Pillar Thinned (50mm) Wafer; TTV = 3.6 µm Low TTV after coating, bonding and thinning flat Si or over topography 19

TWB Adhesive Performance (After Debonding) Debonded Device Wafer Peeled-off Adhesive Layer 20 Clean, mechanical debonding from bumped die (Cu Pillar, C4 bump, µbump) at room temp TWB adhesive removed from carrier by tape peeling 20

TWB Adhesive Summary XP-130215 TWB Adhesive: New TWB product developed for room temperature, mechanical debonding Tunable film thickness, low TTV for surfaces ranging from low topography to Cu Pillars to C4 bumps extendibility to fine pitch/tsv applications Short cycle time for TWB adhesive deposition/curing, rapid, simple, clean mechanical debonding process lower CoO Compatible with backside integration process steps demonstrated with 300mm test vehicles high reliability/yield Customer evaluations ongoing 21

Outline Introduction Key Materials Needs and Challenges Enabling Materials Solutions Dielectrics Temporary Wafer Bonding Adhesive Non-Conductive Film Cu TSV Filling Summary 22

Non-Conductive Film (NCF) XP-130576A NCF* *Also referred to as Wafer-Level Underfill (WLUF) or Pre-Applied Underfill (PAUF) Silica-filled epoxy based film designed for vacuum lamination application Available in dual-use format with backgrinding tape High uniformity coating over topography (Cu pillar/solder cap) Good bump and fiducial visibility for dicing and alignment Self-fluxing, fast film curing during thermocompression bonding (TCB) Good joining without filler entrapment Void-free film after bonding Passes reliability testing 23

NCF Process Overview Thinned Wafer, Cu µpillar/snag Cap NCF Dynamic Rheology Profile Vacuum laminate NCF (Bumps covered or exposed) (1min @ elevated T, P) Complex Viscosity, η* (Pa-s) Maximum curing rate at 185 o C Dice TCB to TSV Wafer (<10s @ elevated T, P) NCF Post-Cure (175 o C, 90 min, 1atm) Scan Rate = 10 o C/min Representative profile - minimum viscosity and maximum curing rate are tunable Key Properties of Cured NCF T g (TMA): 170 o C CTE (a 1 ): 25ppm/ o C E: 6.5 GPa Minimum viscosity = 2.5 Pa*sec Temperature, T ( o C) 24

NCF Performance (Coating) Bumps Uncovered 330mm NCF Laminate Film Roll Film thickness (FT): 20-40µm Vacuum Lamination NCF Laminated Wafer 300mm Film Thickness Uniformity (across 330mm wide roll) FT: 25 + 0.5µm (+2%) Good Bump Visibility (Covered Bumps) Viewed through TCB camera FT: 23µm 25

NCF Performance (Bonding) Compatible with Dicing (Mechanical or Stealth) No cracking, chipping, hinging of laminated NCF Thermocompression Bonding Void-Free Adhesive Bonding C-SAM inspection of cured film Good Joint Formation SEM x-section No Filler Entrapment Observed SEM/EDX analysis 26

NCF Performance (Reliability) Fillet MSL3 Test Thermal Cycle Test Good coverage along die sidewall 50µm 1 week at 30 o C/60% RH + 3X solder reflow - Pass -55 to +125 o C, 2000 cycles - Pass Die 90um Die Mechanical test structure Passed with no delamination or voiding Mechanical test structure Passed 2000 cycles with no voiding or delamination Electrical Testing Testing in progress (electrically-testable die) Biased HAST 130 o C, 85%RH, 96 hrs - Pass SIR test structure Surface Insulation Resistance unchanged 27

NCF Summary XP-130576A NCF: New Non-Conductive Film developmental product Designed for fine pitch, narrow gap Cu Pillar/TSV applications Highly uniform laminated film over topography, TCB snap curing high throughput, lower CoO Void-free bonding, good joint formation, no filler entrapment high reliability/yield Customer evaluations ongoing 28

Outline Introduction Key Materials Needs and Challenges Enabling Materials Solutions Dielectrics Temporary Wafer Bonding Adhesive Non-Conductive Film Cu TSV Filling Summary 29

Cu TSV Plating Chemistry INTERLINK Cu TSV Chemistry Designed for Interposer and Via Middle TSV Applications Bath Components Sulfuric Acid-Based Copper Electrolyte 3 Part Additive System Accelerator: Electrocatalyst for bottom-up filling Suppressor: Suppresses deposition in field, along sidewalls Leveler: Enhances planarization over feature arrays 30

Cu TSV Plating Performance (Deposition) Partial Filling Sequences: Strong polarization at via opening ideal filling profile Via filling speed tests: Rapid filling capability Cycle times <15min (5x50µm), <40min (10x100µm) demonstrated (Wafer type, seed layer dependent) Low overburden thickness, smooth deposits Test Vehicle source: Applied Materials 0.80µm OB for 1.5µm Cu deposit R a <10nm 31

Cu TSV Plating Performance (Annealing) 5x50µm 10x100µm Test Vehicle source: Applied Materials Consistent via filling across 300 mm wafer in production toolset Cu TSVs annealed at 400 o C for 30 min Annealed film is void-free with large full-width Cu grains High purity Cu deposit (<50ppm organics by SIMS) 32

Cu TSV Plating Performance (Aging) Fresh Bath 1.7Ahr/L 3.5Ahr/L 6.8Ahr/L 11.1Ahr/L 13.8Ahr/L (aging study stopped) 10x100µm TSV aging study, 38min cycle time, 1.4µm overburden Continuous plating, 8% bleed/feed, daily additive dosing No voids in as-plated or annealed deposit, no polarization loss during aging study to 13.8 AHr/L After Annealing Test Vehicle source: Applied Materials 33

Cu TSV Plating Summary INTERLINK TM Cu TSV CHEMISTRY: New product developed for Cu TSV interposer and via middle applications Fast filling times and low overburden lower CoO Void-free filling, low defects, high purity deposit high reliability/yield Online bath metrology available Customer evaluations ongoing 34

Summary 2.5D/3D-TSV is a complex landscape with many different materials requirements Dow has successfully developed enabling new products that are tailored for these applications New Dielectrics, Temporary Wafer Bonding Adhesive, Non-Conductive Film, TSV Cu filling Fast, simple processes high throughput, reduce CoO Si Die Dow Cu/Ni/SnAg Si Substrate Dow NCF Test Vehicle source: Applied Materials 35

Thank You Trademark of The Dow Chemical Company ( Dow ) or an affiliated company of Dow.