RF System in Packages using Integrated Passive Devices by Kai Liu, YongTaek Lee, HyunTai Kim, Gwang Kim, and Billy Ahn STATS ChipPAC 1711 W. Greentree Drive, Suite #117, Tempe, AZ 85284, USA Tel: 480-222-1722 : kai.liu@statschippac.com Copyright 2011. Reprinted from 2011 International Microelectronics and Packaging Society (IMAPS) Proceedings. The material is posted here by permission of the International Microelectronics and Packaging Society (IMAPS). By choosing to view this document, you agree to all provisions of the copyright laws protecting it.
RF System in Packages using Integrated Passive Devices Kai Liu, YongTaek Lee, HyunTai Kim, Gwang Kim, and Billy Ahn 1711 W. Greentree Drive, Suite #117, Tempe, AZ 85284, USA Tel: 480-222-1722 Email: kai.liu@statschippac.com 1) Introduction Passive components are indispensible parts used in System in Packages (SiP) for various functions, such as decoupling, biasing, resonating, filtering, matching, transforming, etc. Making passive components embedded inside laminate substrates is limited on passive density. Discrete and SMD solutions are by far the most popular approaches in the industry, and may still be dominant for some times. Figure 1 shows a single package radio (Skyworks, 13 mm x 13 mm Dual Band GSM/GPRS). In this package, there are transceiver, power amplifiers, power management, LTCC filters, switch, SAW filters along with some SMD components (for RCL) on the laminate substrate. In addition, some small-value inductors are embedded inside the laminate substrate. As high-integration and high-performance has become a trend in the packaging solutions, integrated passive device (IPD) technology shows some unique features, which may help to achieve these goals, especially for RF packages. For certain functions (filtering, for example), IPD parts may be in two-times smaller footprints than LTCC counterparts, while achieving similar electrical performance. In most of applications, IPD parts are in low profile (150 um - 250 um height), which are thinner than LTCC parts, and may be used in SiP very efficiently.
Figure 1. Laminate-based RF SiP example (from Prismark). Substrate loss is a key specification for RF applications. The substrates that are widely used for RF packages and modules are, laminate, LTCC, Silicon, GaAs, Glass, etc. In this paper, the packaging approaches are based on a specially-treated silicon substrate. In the IPD process, lowloss substrate material is used, and therefore high-q inductors can be built. In addition, thin-film IPD process has finer pitch feature and better tolerance control than other commonly available ones, such as PCB and LTCC technologies, which may yield very repeatable electrical performance, and provide packages of high-integration. Figure 2 shows the IPD stack-up, where three metal layers (M1, M2, and M3) and some passivation layers (PI-1, PI-2) are used in the process. Capacitors are made through Silicon-nitride dielectric, resistors are made through TaSi layer, and inductors are made in M3 (Cu) layer. INDUCTOR CAPACITOR RESISTOR M3 M3 M3 M2 M2 M2 M1 M2 PI-2 PI-1 M2 oxide silicon substrate nitride TaSi nitride TaSi Figure 2. Thin-film integrated passive device (IPD) structure (illustration not in scale).
2) Case Study #1: QFN Package RF devices usually have low pin-count, and peoples have widely used QFN for cost-effective packaging approaches. A typical QFN package for RF application is shown in Figure 3. There are several RF chips (PA and switch) along with an IPD in this package. As can be seen, there are many wire connections between chips, pads, and paddles. Wires not only have some resistance and inductance contribution to the electrical devices packaged, and they also talk to Figure 3. QFN package using IPD. each other. In packages for digital circuits, crowded wires may be still acceptable for circuit functions. But in a circuit which needs high selectivity and high isolation, this wire arrangement may cause device malfunction, especially for RF circuits. A method to accurately characterize this impact is to use electromagnetic (EM) tools to get the wire models. These electrical models (usually in s-parameters) can then be used along with device models (e.g. PA models) to check the device s performance in presence of these wires. 3) Case Study #2: Stack-Die Package IPD RFIC Dummy Si Figure 4. Stack-die package using IPD.
3D or stack-die solutions have great potential to reduce package form-factor or cost, and have Figure 5. Coupling test structure for RF Stack-die package. been widely used in memory chip packages. However, when using this approach for RF packges, one has to take into account of the impact of cross-talk between the individual RF chips. In RF chips, there are inductors (for VCO and LNA, for example), which often talk to other inductors (in filters and baluns, for example) in IPD circuits, through magnetic fields. Since in a stack-die approach, the saperation (vertical distance) between these inductors are limited, these crosstalk/inteference/coupling may add noise and may provent the device from achieving its optimum performance. Figure 4 shows a RF stack-die package using IPD for balun and filter functions. The IPD die is in very small form-factor. There is a dummy siliocn chip along side with the IPD chip for the bottem dies to overcome top die overhanging issue. Figure 5 shows an approach to accurately characterize cross-talk between IPD inductor and inductor in a RFIC circuit. IPD inductor is usually larger than inductor implemented in a RFIC circuit, as they are properly scaled in the tester shown in Figure 5. In the tester, the bottom chip has an array of small inductor coils (representing RFIC inductors) with certain separation, and the top chip has one large inductor representing IPD inductor. G-S-G pads are made in both chips for probing measurement. By measuring 2-port s-parameter of the tester, one can obtain the cross-talk strength with horizontal distance. By assembling the top IPD chips with different thicknesses (back-grinded to different thicknesses), one can also know the cross-talk strength with vertical distance. This characterization data can be used for checking a RFIC s performance or for co-design with a RFIC in presence of IPD circuit in a stack-die configuration. 4) Case Study #3: Wafer-Level Integration Wafer-level integration has a very tight tolerance-control, and may result in very high-yield packaging products. Most of mold materials used in the packaging industry have good RF properties, such as low loss-tangent, which allows to build high-q inductors in presence of such mold substrates. Figure 6 shows a side-by-side package made through ewlb (embedded Wafer level BGA) process. In this package, one chip is a RF power amplifier (PA) and other one is an
IPD chip for matching and filtering functions. The interconnection is made through wafer-level RDL. For this PA package, excessive big bumps (220.0 um stand off) are made for heat dissipation purpose. The IPD and the RDL are made from two different batch processes. There is a need to set up a common simulation platform to incorporate the stack-up info from these two processes. Once the simulation for these passives and interconnections are ready, they can be used along with a PA design. PA performance is sensitive to the contribution from passives and interconnection, and to the cross-talk between individual parts. EM simulation of the packaging approach is needed to ensure a first-round success in such package development. Wafer-level RDL Wafer-level Passivation Figure 6. ewlb package have PA die and IPD die connecting through wafer-level RDL process. 5) Conclusions IPDs are made from silicon back-end batch process, which ensures high-yield passive products for RF applications. The RCL values and functional blocks from this process (e.g., filters and baluns) are well fit for RF SiP applications in terms of performance, size, and cost. For a RF SiP product, co-design between active chips, IPD, and packaging is needed, in order to properly take into account of impacts from passives and interconnections and to reduce development cycle-time.