Die Thickness Effects in RF Front-End Module Stack-Die Assemblies

Transcription

1 Die Thickness Effects in RF Front-End Module Stack-Die Assemblies By Kai Liu*, YongTaek Lee, HyunTai Kim, Gwang Kim, Robert Frye**, Hlaing Ma Phoo Pwint***, and Billy Ahn * STATS ChipPAC, Inc West Greentree, Ste. 117 Tempe, AZ USA *** STATS ChipPAC, Singapore 5 Yishun Street 23 Yishun , Singapore ** RF Design Consulting, LLC 334 B Carlton Avenue Piscataway, NJ 885 USA STATS ChipPAC, Ltd. San Ami-ri Bubal eup Ichon-si Kyonggi-do, Korea Copyright 21. Reprinted from 21 Electronic Components and Technology Conference (ECTC) Proceedings. The material is posted here by permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any STATS ChipPAC Ltd s products or services. Internal or personal use of this material is permitted, however, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or distribution must be obtained from the IEEE by writing to pubs-permission@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

2 Die Thickness Effects in RF Front-End Module Stack-Die Assemblies Kai Liu*, YongTaek Lee, HyunTai Kim, Gwang Kim, Robert Frye**, Hlaing Ma Phoo Pwint***, and Billy Ahn * STATS ChipPAC, Inc West Greentree, Suite 117 Tempe, Arizona 85284, USA Tel: kai.liu@statschippac.com ** RF Design Consulting, LLC 334 B Carlton Avenue Piscataway, NJ 885 USA bob@rfdesignconsulting.com *** STATS ChipPAC, Singapore. 5, Yishun Street 23 Yishun Zip , Singapore maphoopwint@statschippac.com STATS ChipPAC, Ltd. San Ami-ri Bubal eup Ichon-si Kyonggi-do, Korea yongtaek.lee@statschippac.com Abstract We have investigated the impact of die thickness on integrated passive device (IPD) performance both in simulation and from measurement for RF stack-die applications. Our simulation approach accurately predicts the behavior of the IPD in such stack-die configuration. This should help us to generate guidelines for RF integrated passive devices to be used in 3D stack-die packages. interference between dies may cause malfunction, and therefore packaging solutions should be investigated or codesigned with transceiver designs. In a stack-die package, if one chip is an RF transceiver, (for example), and another is a digital or analog baseband chip, it is likely that the RF chip (victim) will be the impacted by the signal interference from the other chip (aggressor). INDUCTOR CAPACITOR RESISTOR Introduction In RF communication systems, between antennas and transceivers there are switches, filters, baluns, and matching circuits (so called front-end-modules). Traditional implementation of front-end modules (FEM) is to have transceiver packages, and other surface-mount components (for switches and passives, for example) assembled on a system board. A more integrated solution is to use a laminate or LTCC substrate to implement all or some of the above active and passive components in one single package system in package (SiP). RF transceivers are mainly made from CMOS technology, while most RF switches are still made from GaAs technology and can not be made along with transceivers for performance reasons. For RF circuits, quality-factors (Q) of passives (inductors, for example) play significant roles in their electrical performance, and therefore passive components (RCL and functional blocks, such as filters and matching circuits) are intentionally made off-chip, through various options from LTCC, laminate, silicon, GaAs or glass substrates[1-4]. While side-by-side approaches are commonly adopted in SiP or MCM applications, stacked-die and 3D wafer-level packaging solutions are attracting attention. 3D assemblies are rapidly evolving into a promising new field, because they may significantly reduce the package footprint and cost by using interconnection through vertical dimension (Z-direction). However, when multiple dies are stacked in Z-direction, there may be strong electrical coupling between them since their separations are much shorter or less than those in side-byside configurations. For stack-die RF packages, electrical M3 M3 M3 oxide M1 silicon substrate TaSi nitride PI-2 PI-1 nitride TaSi Figure 1. Thin-film integrated passive device (IPD) structure (illustration not in scale). However, if both chips in a stack-die package have RF functions, either chip can be both aggressor and victim. We have investigated a case, in which the top die is an RF IPD chip and the bottom die is an RF transceiver chip (in flip-chip format) made from CMOS technology. In this study, we examine the case, in which the IPD is a victim impacted by a CMOS chip substrate. The tested CMOS wafer in the stack-die configuration was selected from a regular p-type CMOS wafer with resistivity of around 1. Ohm-cm to 1. Ohm-cm. To represent the actual stack-up of the package, the CMOS wafer was facing down with the metal patterns on the bottom side. The IPD wafer was then stacked onto the CMOS wafer for subsequent probing measurement. Design for Stacked Die Package 1) Silicon IPD Process In STATS ChipPAC s silicon IPD process, a specially treated silicon substrate is used to support dielectric layer and metal layers. There are three metal layers (M1,, and M3) /1/$ IEEE Electronic Components and Technology Conference

3 and two dielectric layers (PI-1, and PI-2) in the cross section as shown in Figure 1. Layers M1 and are used to form MIM capacitors and their thickness are 1. um and 3. um, respectively. The capacitance density is 33 pf/mm 2 from this process. This density is high enough for making capacitors for RF applications (typically less than few tens of pf), but may be not enough for decoupling applications. The layer M3 is made of thick copper, and inductors are implemented in this layer. For RF inductors (typically inductance value less than 3. nh), the Q factors achieved from this process are around 25. to 35., depending on inductance values. Both wire-bonding and flip-chip type IPDs can be made from this process. Typical finished thickness of the wafer is around 25. m or larger, and the actual circuit elements (RCL) are implemented in the top 1% area of the silicon Switch substrate. With this physical cross section, the Q factor and inductance will be slightly different for an inductor in wirebonding and flip-chip configurations, which has to be considered in IPD design. The process tolerance/variation is relatively small, compared to a thick-film (LTCC, for example) technology, which is used for conventional passive components in the industry. Highly repeatable passive circuits (filter, balun, matching, etc) for RF applications can be made through this IPD technology [6-8]. IPD RFIC Laminate Substrate SMD Figure 2. Illustration of stack-die package using IPD. h1 h h2 inductors is determined by many aspects, such as the IPD thickness, and the other die s thickness. Figure 2 shows a stack-die package example, where an IPD chip is stacked on to a transceiver chip (RFIC), and the transceiver chip is in flip-chip format. In this case, the distance to ground plane is the sum of the flip-chip bump height, transceiver thickness, and the IPD thickness (h+h1+h2). To achieve certain total package height, the elevation (h+h1+h2) of the IPD inductors in this package is chosen as around 42. m. The over-mold material is also considered in the electromagnetic (EM) simulation set up. A BPF working at 2.5 GHz is used in this work. The topology is shown in Figure 3, and the circuit element values are listed in Table I. Table I. LC values for the filter components (in pf or nh) and coupling coefficients. L A L B L C C A C B C C k AB k BC k AC The initial LC components based on the values in the table above were created using a GDS tool generator, which complies with the design rules. After some interconnection and a co-planar ground were added to form a functional block, an EM simulation tool was used to simulate the response from the layout. Due to the parasitic and the coplanar ground, the initial EM response altered from the A B C d2 d3 d3 d2 d1 Figure 3. Circuit topology for a balanced band-pass filter. 2) IPD Design In an IPD functional block, there are inductors and capacitors. For RF applications, inductor s performance is impacted by metal patterns or ground planes nearby. In a stack-die package, the ground plane location for IPD Figure 4. BPF with (bottom) and without (top) coplanar ground. expected response to some extent. Some internal ports were assigned on the electrodes of capacitors for tuning. The separation/distance between the three inductors used in this device also plays a role in the fine tuning process of its performance. The distances d1, d2 and d3 control coupling strength and therefore the pass-band and stop-band performance. From the circuit topology, the coupling (k AC ) Electronic Components and Technology Conference

4 between LA an LC is very weak, and from EM simulation the distance between LA and LC (d3) is not sensitive to this device s performance. Usually it takes 3-4 iterations to tune H=15; 25; 42; 75um E9 4.E9 6.E9 8.E9 1.E1 between the three inductors. In principle, narrow band response is expected from this device. Due to the symmetric design in layout (Figure 4), the two output ports connecting the two electrodes of the output capacitor (Cc) have almost perfect balanced properties. The wafer raw thickness is about 75. m before backgrinding. After the IPD wafer was made, probing measurement on the devices above was conducted. Then the wafer was then back-ground to about 425. m (17 mils) and re-measured. Finally, the wafer was back-ground to 15. m thickness. For a small IPD (like a LPF), there is almost no noticeable difference in the pass band performance for thickness variations like these. H=15; 25; 42; 75um -1 2.E9 3.E9 3.5E9 Figure 5. Simulated response of IPD with different substrate thickness. the performance back to meet electrical specifications. Detail scheme for designing this BPF can be found in [9]. Design of this device adopts weak coupling scheme E9 4.E9 6.E9 8.E9 1.E1 R=5; 1;.1;.1 Ohm-cm R=5; 1;.1;.1 Ohm-cm -1 2.E9 3.E9 Figure 6. Simulated response of IPD being stacked on to a CMOS chip with different substrate resistivity. Top Wafer (IPD) Bottom Wafer (CMOS) Figure 7. An IPD wafer (half) stacked on to a flipped CMOS wafer. However, for a large IPD (like this BPF), the performance difference is significant, and is sufficient to make difference between a workable and non-functional IPD. As can be seen in Figure 5, the performance of samples of 42. m and 75. m wafer thicknesses both cover the pass band well. But the performance from the sample of 15. m wafer thickness is impacted negatively, resulting in high insertion loss at the low side of the pass band. It is concluded that this BPF made with 15. m thickness (for example, putting it directly on a laminate substrate) will not have good electrical performance. In a stack-die packaging scenario, when this IPD is placed over another CMOS die, the electrical characteristics of the CMOS substrate may also have an impact on the IPD performance. For a typical p-type CMOS wafer used for making RF transceiver, the substrate resistivity is typically in 1. Ohmcm to 1. Ohm-cm range. Using the substrate resistivity of this range, we find there is almost no impact on the IPD s performance. Only when the substrate is nearly conductive (in very low resistivity), it starts to have considerable negative impact on the IPD s performance (mainly on insertion loss). Figure 6 shows the performance trend with the CMOS substrate resistivity on a BPF (in 15. m thickness) stacked on to a CMOS chip (in 27. m thickness). For the CMOS Electronic Components and Technology Conference

5 wafer resistivity from 1. Ohm-cm to 1. Ohm-cm, there is no appreciable impact on the IPD s electrical response. When the silicon substrate resistivity changes from 5. Ohm-cm to.1 Ohm-cm, the insertion loss at 2.5 GHz degrades from db to -6.5 db. Characterization for Stacked Die Package Wafers with some probable IPDs were made in raw substrate thickness (~75. m). Then they were back-ground to about 42. m, and 15. m thickness. The probing measurements were taken at each wafer thickness level (75. m, 42. m, and 15. m), in order to characterize the IPD s performance with IPD die thickness. For the stack-die probing measurement, an IPD wafer in 15. m thickness was used for the top wafer. A CMOS wafer (having resistivity around 1. Ohm-cm to 1. Ohmcm) with some metal patterns already deposited was used for the bottom wafer. Figure 7 shows the IPD wafer (in thickness of 15. m, partially cut) sitting on top of a CMOS wafer (in thickness of 27. m) for probing measurement. The IPD wafer was cut to half for the measurement due to some warpage resulted in from the thin IPD wafer (15. m). Tapes were used to stick these two wafers during the measurement. The CMOS wafer was facing down to represent the packaging scenario where a RF transceiver (bottom die) is in flip-chip configuration. The characterization scheme in this paper is summarized in Table II. Table II Characterization scheme. IPD Thickness ( m) 15 (#1), 42 (#2), 75 (#3) CMOS Die Thickness ( m) 27 (metal facing down, #4); 27 (metal facing up, #5) #1 IPD thickness effect #2 IPD thickness effect #3 IPD thickness effect #1 + #4 CMOS die effect #1 + #5 CMOS die effect A small IPD (low pass filter) in size of around 1. mm x 1. mm was used in this characterization. Probing measurement was conducted on the IPD in different die thickness (wafer thickness). As expected from simulation, there is no appreciable difference on the electrical performance with different IPD die thickness (measured response not shown). The 15. m thickness small IPD was also stacked onto a CMOS die and then probed. It is noted that adding a CMOS chip under this small IPD does not change its electrical behavior, as the CMOS chip is just making a secondary impact. A little larger device (a bandpass filter-bpf) in size of about 2. mm x 1.2 mm was used for the characterization too. db(s(7,8)) db(s(4,5)) db(s(1,2)) m16 2.5GHz db(s(1,2))=-6.44 db(s(7,8)) db(s(4,5)) db(s(1,2)) H=15; 42; 75um m17 2.5GHz db(s(4,5))= m17 m18 m16 m18 2.5GHz db(s(7,8))= Figure 9. Measured electrical responses. Red: 15. m wafer. Blue: 42. m wafer. Pink: 75. m wafer. Figure 8. Micrograph of the fabricated BPF with G-S- G probable pads. In this device, there are three inductors. The outer inductor has relatively big size/inner diameter (about 8. m). Theoretically, performance of a larger inductor is more impacted by a ground plane location than a smaller inductor. But quantitative analysis can be only obtained from EM simulation or experiment. Figure 8 is a micrograph of the BPF. The intrinsic size of the IPD (excluding the G-S-G probing pads) is about 2. mm x 1.2 mm. From the measurement data (Figure 9), at 42. m and 75. m die thicknesses, the performance is almost identical. But at 15. m die thickness, the low side of the pass band response is deteriorated very much, and unacceptable insertion loss is seen. In other words, the IPD in 15. um thickness alone does not have good response. This validates the trend obtained from simulation Electronic Components and Technology Conference

6 The 15. m thick IPD (wafer) was then stacked onto a CMOS chip (wafer). The CMOS wafer had been backgrinded to about 27. m. Therefore the ground plane for the IPD inductors is about =42. m. Figure 1 shows the results of this BPF in the stacked configuration. Importantly, the 15. m thick IPD, once being staked onto a CMOS die (in 27. m thickness), retrieves it good behavior as this IPD being 42. m thick alone. Another test was also conducted to see the effect when the bottom die (wafer) was facing up, which application could be represented by a wire-bonding CMOS die (bottom die) in a stack-die package. The electrical response from both facingup and facing-down configurations for the bottom die is depicted in Figure 11 for comparison. As shown in this figure, the difference between these two cases is significant (more than 1.5 db insertion loss difference!). The response from the lower side of the pass-band is severely impacted, mainly due to the presence of the metal patterns on the bottom CMOS die. It is concluded that the bottom die configuration (either wire-bonding or flip-chip) should be taken into account in early packaging design stages, and simply using the IPD design of flip-chip for wire-bonding configuration, or vice versa, would not achieve the expected electrical response. Besides experimental characterization, we have also simulated the IPD s electrical performance. In Figure 12, simulation and measurement for the BPF with 42. m Differential Mode (db) Retuen Loss (db) -1 m3 2.46GHz db(s(1,2))= m4 m3 m4 2.46GHz db(s(4,5))= Figure 11. CMOS die impact on IPD performance (measured). Red: bottom die with metal patterns facing up. Blue: bottom die with metal patterns facing down. m1 2.5GHz db(s(1,2))= m2 2.5GHz db(s(4,5))= m1 m2 Differential Mode E9 4.E9 6.E9 8.E9 1.E1 Differential Mode (db) m3 2.46GHz db(s(1,2))=-2.45 m3 m4 m4 2.46GHz db(s(4,5))= Single-end Return Loss Retuen Loss (db) E9 2.E9 3.E9 4.E Figure 1. Measured electrical responses. Blue: 15. m IPD wafer m CMOS wafer. Red: 42. m IPD wafer alone. Figure 12. Comparison between simulation and measurement on a 42. um thick IPD. Red: simulation. Blue: measurement Electronic Components and Technology Conference

7 thickness is compared. Excellent agreement between simulation and measurement is achieved. Simulations with other parameters, such as IPD die s thickness and CMOS die s presence are also carried out, and they all have good agreements with the measurement. Conclusions Several IPD candidates on the wafer of 15. m thickness were used for this stack-die packaging characterization. For some small IPDs in size less than 1. mm x 1. mm, such as LPF and balun, we found that the thickness of the CMOS die (bottom die) makes no appreciable difference on IPDs electrical behaviors. However, for some large IPD (2. mm x 1.2 mm, for example) with large inductor coils, the CMOS die thickness does have a noticeable impact on the IPDs performance, resulting in characteristics ranging from workable to failed against the specifications. In a stack-die package design, the elevation (distance to GND) of IPD inductors has to be taken into account, and a budget arrangement of package height in early design stages may be needed for IPDs with large inductor coils used in such stack-die package. Acknowledgments The authors acknowledge Padmanathan Meenakshi and Ma L Nang Htoi for their efforts in the sample fabrication and the measurement preparation for this work. References 1. Topper, Michael, etal, Low Cost Wafer-level 3D Integration without TSV, Proc 29 Electronic Components and Technology Conf, June 29, pp Zoschke, K., etal, Copper/Benzocyclobutene Multi Layer Wireing A Flexible Base Technology for Wafer level Integration of Passive Components, Proc 27 Electronics Packaging and Technology Conf, Dec. 27, pp Kripesh, K., etal, Design and Development of Multi Die Embedded Micro Wafer Level Package, Proc 28 Electronic Components and Technology Conf, pp Kumar, Aditya, etal, Wafer Level Embedding Technology for 3D Wafer Level Embedded Package, Proc 29 Electronic Components and Technology Conf, June 29, pp Liu, Kai and Frye, Robert, Full-circuit design optimization of a RF silicon integrated passive device, Proc 15 th IEEE Topical Meeting on Electrical Performance of Electrical Packageing (EPEP), Scottdale, AZ, Oct. 26, pp Liu, Kai; Frye, Robert; and Emigh, Roger, Compact Balanced Bandpass Filter for 3.3GHz 3.9GHz WiMAX Applications, Proc 29 Electronic Components and Technology Conf, June 29, pp Frye, Robert; Liu, Kai and Lin, Yaojian, Three stage bandpass filters implemented in silicon IPD tecjnology using magnetic coupling between resonators, Digest of 28 IEEE MTT-S International Microwave Symposium, June 28, pp Liu, Kai; Frye, Robert, and Emigh, Roger, Miniaturized ultra-wideband bandpass filter from silicon integrated passive device technology, Digest of 29 IEEE MTT-S International Microwave Symposium, June 29, pp Liu, Kai; Frye, Robert, and Billy Ahn, High Rejection BPF for WiMAX Applications from Silicon Integrated Passive Device Technology, To be published in 21 IEEE MTT-S International Microwave Symposium, May 23-28, Anaheim, CA Electronic Components and Technology Conference