Contact Resistance Reduction using Advanced Implant and Anneal Techniques for 7nm Node and Beyond Fareen Adeni Khaja Global Product Manager, Front End Products Transistor and Interconnect Group NCCAVS Junction Technology Group Semicon West Meeting July 14 th, 2016 Applied Materials External Use
Outline Motivation for Contact Resistivity (ρc) Reduction Advanced Implant Techniques for ρc Reduction Nanosecond Laser Anneal for PMOS and NMOS ρc Reduction Summary 2
Spacer Contact Contact resistivity (e -9 Ω cm 2 ) Low Contact Resistance Requirement for Transistor Continuous Scaling Intel 14nm, IEDM 2014 10 Parasitic resistance requirement for 10/7/5 nm nodes (Ω-um) 8 R plug Metal Gate 6 33 R interface R access silicide S (epi) D (epi) 4 Fin 2 +10% R Plug R Interface R access 0 N5 N7 2 6 10 14 18 Equivalent Contact CD (nm) 3
Impact of Scaling on External Resistance Fin pitch scaling reduces contact area increases Rc Tall fin height results in increase of S/D resistance (RSD) External resistance is limiting transistor performance Require Innovative doping and Annealing solutions for NFET & PFET to reduce Rc and RSD 4
Outline Motivation for Contact Resistivity (ρc) Reduction Advanced Implant Techniques for ρc Reduction Nanosecond Laser Anneal for PMOS and NMOS ρc Reduction Summary 5
Damage Engineering with Cryogenic Implants Physical Mechanism F. Khaja et al., APL 2012 Cryo Implants Reduced EOR & Defects, Improved Activation, Yielded Better Silicidation, Less Variability, High Drive Current 6
Damage Engineering with Thermal Implants Physical Mechanism RT Thermal interstitials (I) and vacancies (V) form amorphous pockets (AP) when they are within a capture distance Amorphous pockets (Is-Vs clusters) evolve to form Amorphous layer I-V fast recombination (jump frequency when T ) M. Togo et al., IMEC, VLSI 2013 M. Togo et al., IMEC, VLSI 2013 Hot implant reduces Amorphous Pocket Growth Hot Implant enhances dynamic annealing Thermal implant reduces Damage Improve Device performance >15% Thermal Implant Reduces Crystal Damage, Reduces Device Leakage 7
Plasma Doping: Shallow & Conformal Implant Fin top Fin bottom As concentration (at/cm -3) 1E+22 1E+21 1E+20 1E+19 1E+18 1E+17 1E+16 Conformality Corrected 1.5D SIMS with area Si 150 250 350 Depth (nm) 150 nm Applied Materials internal development Plasma doping enables high doping concentration on surface and is a promising enabler for conformal contact 8
Implant Effect to Rc on HDSiP >50% C.N.Ni et al., VLSI 2016 Plasma implant is a promising enabler for conformal contact 9
Outline Motivation for Contact Resistivity (ρc) Reduction Advanced Implant Techniques for ρc Reduction Nanosecond Laser Anneal for PMOS and NMOS ρc Reduction Summary 10
Metal Work-function (ev) Energy Band(eV) Energy (ev) Ge-rich contact interface for PMOS ρc reduction Band Gap Modulation by Ge in SiGe Lower Rc (SBH, DSS) High Surface Doping Narrow Bandgap(Ge) Pinning close to valence Fermi-level band pinning R c C C q exp B 1 1 2 N if Area Metal M/Si M/Ge 1 0 1.1 0.5 0 Conduction Band 100% 70% 45% 0 50 100 Ge% in SiGe Yang et al., Semi. Sci. Tech. 19, 1174 (2004) Ge% reduces PMOS contact SBH PMOS ρc reduction 11
Contact Resistivity vs. Ge% Ge% PMOS Rc AMAT Ti/SiGe contact test vehicle Ge Contact metal: TiN/Ti TiN/Ti TiSi x Ge y SiGe SiGe70% SiGe45% -9.0-8.5-8.0-7.5-7.0-6.5-6.0 Contact Resistivity (Ωcm 2 ) in Log C.N.Ni et al., VLSI-TSA 2016 P contact ρc reduces with increase in Ge at contact. ρ c = 3e-9 Ωcm 2 with Ge:B PSD 12
SIMS Ge concentration (%) Ge-rich Surface Formation by Nanosecond Laser Anneal Ge segregation at surface Ge depletion at bulk 70 60 50 40 Applied Materials internal development SPER SiGe SiGe Si Si 30 20 I/I I/I, nsec low energy I/I, nsec high energy 0 10 20 30 40 50 Distance from surface (nm) C.N.Ni et al., VLSI-TSA 2016 Ge is segregated towards SiGe surface with Implant + NLA 13
Ge% Laser energy Ge Segregation by Nanosecond Laser Anneal SiO 2 W TiSi x Ge y Al Laser Anneal vs. ρc I/I + nsec anneal SiGe45% 65% 45% -40 ~20nm -20 0 20 40 Distance (nm) SiGe45% Ref. -9.0-8.5-8.0-7.5-7.0 Contact resistivity (Ωcm 2 ) in Log C.N.Ni et al., VLSI-TSA 2016 Localized Ge segregation by nsec laser anneal 35% of ρc improvement
Si 0.3 Ge 0.7 :B Ultralow Contact Resistivity By Nanosecond Laser Anneal Test Structure Results Process Flow H.Yu et al., VLSI 2016 H.Yu et al., VLSI 2016 Optimization of Implant and nanosecond laser anneal resulted in ρc: ~2 10-9 Ω cm 2 15
Super-activation with Post Implant Nanosecond Anneal Fluence 370 410 430 Contact open implant 8e-10 Ωcm 2 0.7e -9 HDSiP + BL I/I + nsec Applied Materials internal development 15nm HDSiP W HDSiP + Plasma I/I 1e-9 Ωcm 2 HDSiP + BL I/I HDSiP ref. 2.5e -9 1e -9 1e -8 1e -7 Contact resistivity (Ωcm 2 ) Applied Materials internal development 15nm W Ti\TiN HDSiP C.N.Ni et al., VLSI 2016 Post implant nsec laser anneal brings NMOS to 1x10-9 Ωcm 2 16
Outline Motivation for Contact Resistivity (ρc) Reduction Advanced Implant Techniques for ρc Reduction Nanosecond Laser Anneal for PMOS and NMOS ρc Reduction Summary 17
Summary Implant and Anneal optimization is required for achieving low ρ C Implant defect recovery is the key for low contact resistance Plasma implant offers shallow/dopant-rich implanted surface and improved conformality PMOS ρc: Ge-rich contact interface benefits to PMOS Rc, with 3e-9 Ωcm 2 achieved with pure Ge (B@1e20 at/cm 3 ) nsec laser anneal after amorphization implant effectively segregates Ge towards SiGe surface NMOS ρc: Pathways for further ρ C reduction to < 1x10-9 Ωcm 2 and below is adding/optimizing post implant nsec laser anneal 18