Cost effective 300mm Large Scale ewlb (embedded Wafer Level BGA) Technology by Meenakshi Prashant, Seung Wook Yoon, Yaojian LIN and Pandi C. Marimuthu STATS ChipPAC Ltd. 5 Yishun Street 23, Singapore 768442 meenakshi.padmanathan@statschippac.com re 569059 Copyright 2011. Reprinted from 2011 Electronics Packaging Technology Conference (EPTC) Proceedings. The material is posted here by permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any STATS ChipPAC Ltd s products or services. Internal or personal use of this material is permitted, however, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or distribution must be obtained from the IEEE by writing to pubs-permission@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.
Cost effective 300mm large scale ewlb (embedded Wafer Level BGA) Technology Meenakshi PRASHANT, Seung Wook YOON, Yaojian LIN and Pandi C. MARIMUTHU STATS ChipPAC Ltd. 5 Yishun Street 23, Singapore 768442 Meenakshi.PADMANATHAN@Statschippac.com ABSTRACT This paper will highlight some of the recent advancements in 300mm ewlb wafer development. Compared to 200mm case, 300mm ewlb wafer has more warpage and process issues due to its area increase. Thermomechanical simulation shows 100~150% more warpage with 300mm ewlb wafer compared to 200mm. So various design parameters were studied to optimized warpage, such as dielectric materials and thickness, molding compound thickness etc. This paper also presents study of process optimization for 300mm ewlb and on overall warpage behavior in different process steps. Finally 300mm ewlb test vehicles are fabricated and tested in JEDEC standard test conditions. It also describes mechanical characterization, reliability data including component/board level, challenges encountered and overcome, and future steps. II. Introduction Wafer Level Packaging (WLP) applications are expanding into new areas and are segmenting based on I/O count and device. The foundation of passive, discrete, RF and memory device is expanding to logic ICs and MEMS. The WLP segment has matured over the past decade, with numerous sources delivering high-volume applications across multiple wafer diameters and expanding into various endmarket products. With infrastructure and high volumes in place, a major focus area is cost reduction. One of the most well known examples of a Fan Out Wafer Level Packaging is ewlb technology [1]. This technology uses a combination of front- and back-end manufacturing techniques with parallel processing of all the chips on a wafer, which can greatly reduce manufacturing costs. Its benefits include a smaller package footprint compared to conventional leadframe or laminate packages, medium to high I/O count, maximum connection density, as well as desirable electrical and thermal performance. It also offers a high-performance, power-efficient solution for the wireless market [2]. Furthermore, next generation 3D ewlb technology enables 3D IC and 3D SiP (System-in-Package) with vertical interconnection. 3D ewlb can be implemented with through silicon via (TSV) applications as well as discrete component embedding. II. ewlb TECHNOLOGY ewlb technology is addressing a wide range of factors in packaging. One aspect is the packaging cost along with testing costs. In parallel, there are physical constraints such as package footprint and height. Other aspects that were considered during the development phase included I/O density which especially is a challenge for small chips with high pin count density, the need for SiP integration approach, thermal issues related to power consumption and the device's electrical performance (including electrical parasitics and operating frequency). Figure 1. Structural comparison of FI-WLP and ewlb (Fan Out- Wafer Level Packgaing) The obvious solution to the challenges was some form of WLP. But two choices presented themselves: Fan-out or Fanin. Fan Out-Wafer Level Packaging is an interconnection system processed directly on the wafer and compatible with motherboard technology pitch requirements. It combines conventional front- and back-end manufacturing techniques, with parallel processing of all chips. There are three processing stages- reconstitution, re-distribution and backend process. Tested good dice are embedded in an artificial plastic wafer (carrier or reconstituted wafer) using a wafer level molding technique. In the sense, the Si die is surrounded by Epoxy Mold Compound (EMC) material so the additional package footprint outside the die area can be adjusted with this compound thus giving more flexibility to package size design. Front end isolation and metallization processes are then used to fan-out or re-distribute the die interconnections to the surrounding area with lithography and patterning wafer level processes to form package 2011 13 th Electronics Packaging Technology Conference
interconnections. The final stage is traditional back-end processes that include application of solder balls and wafer testing. At the final stage the wafers are sawn into individual units, which are directly assembled on the motherboard into the final product or module without the need for interposers or underfill. Figure 1 shows the structural comparison between FI- WLP and ewlb. ewlb has thick Cu-RDL, so UBM is not required. (UBM is optional for ewlb). Schematics of the reconstitution process. Die level interconnects are remap to higher distributed using metal and isolated layers to level of interconnections in the fan-out area and finally solder balls are applied. In the Fan-in Wafer Level Packaging approach, the number of interconnects and their pitch must be adapted to the chip's size. In contrast, the ewlb supports a fan out area to accommodate higher interconnects and has no restriction on ball pitch. III. 300mm ewlb wafer A. Challenge of 300mm ewlb wafer For 300mm ewlb, there is areaa increase of more than 230% compared to 200mm as shown in Figure 2. As shown Figure 3, GDPW (gross die per wafer), the net die count per reconstituted wafer is drastically increased i with 300mm reconstituted wafer size and big increase with large panel size. As reconstituted wafer size is increased, wafer handling and process stability will be a challenge. Besides, the overall warpage is most critical for larger scale wafer handling like in wafer fabrication process. Warpage affects wafer handling, processability, throughput process stability, thus impacting the yield. So it is critical to optimize and well control the warpage behavior. Figure 3 shows clear warpage difference between 200mm and 300mm ewlb wafers. With computational simulation work for 300mm ewlb, it showed more than twice the warpage of 200mm case. Figure 5 shows warpage change with different reconstituted wafer thickness in 300mm ewlb. It clearly showed trend of less warpage with optimized reconstituted wafer thickness by thermo-mechanical simulation as shown in Figure 5. Figure 2. 300mm ewlb carrier and Comparison of its size of 200 and 300mm ewlb carriers. Table 1. Advantage of ewlb packaging. Advantage of ewlb Technology The current BGA package technology is limited by the organic substrate capability. Moving to ewlb helps overcome such limitations and also simplifies the supply chain. Building the substrate on the package itself, allows for higher integration and routing density in lesss metal layers. ewlb is a next generation packaging platform that enables advanced integration, particularly for wireless devices and this packaging technology has a number of important features. Transition to ewlb packaging technology enables a significant reduction in recurring costs by eliminating the need for expensive substrates. The advantage of ewlb packaging can be summarized in Table 1. BGA packaging also faces a challenge with technology nodes beyond 65nm as the device performance density drives the need for flip chip. But advanced flip chip nodes drive fine pitch combined with weaker low-k dielectric structures resulting in flip chip becoming narrower in terms of packaging process margin,. In addition, there is a big trend in being environmentally friendly, driving lead free and halogen free, or green, material sets. With the ultra low-k and interconnects pitch becoming smaller and the shift to implement lead free materials, the technical limitations faced by the packaging industry are becoming more challenging. ewlb technology provides a window for packaging next generation devices in a generic, lead- free/halogen free, green packaging scheme. 1. The smallest and thinnest package other than fan-in WLCSP 2. Excellent electrical and thermal performance Great for high frequency application Excellent for RF and mixed signal due to low parasitics compared to any laminate-based packages The lowest thermal resistance 3. High density routing is easily implemented in RDL 4. No ELK damage issues for advanced Si nodes devices 5. Proven low cost path using a batch process & simple supply chain 6. Path to the flexible 3D packages any array patterns on the top 7. Scalable technology to a larger panel production Lower cost Figure 3. Comparison of gross die per wafer(carrier) as function of die size with 200 and 300mmm carriers 2011 13 th Electronics Packagingg Technology Conference
(Design of experiment), key parameters were identified such as dielectric materials and thickness, molding compound thickness etc. Based on those parameters, in-depth simulation was carried out for several combinations of each parameter. Figure 6 and 7 show the warpage behavior with different materials sets. With different set of materials, it showed significant warpage behaviors with maximum difference of 1000um (1mm). Figure 6. Computational mechanical warpage simulation data with different material DOE of 300mm ewlb. Figure 4. Warpage of 200mm and 300mm thermo-mechanical simulation ewlb with Figure 7. 300mm ewlb wafer warpage with different materials set DOEs. Figure 5. Warpage change with Si / molding thickness of wafer level molding in 300mm ewlb process. To optimize these warpage behaviors, various material/process parameters were studied. Each material has different physical properties like CTE (coefficient of thermal expansion), Young s modulus, and Poisson s ratio. So combination of each physical properties critically affect overall ewlb wafer warpage. After basic thermal-mechanical simulation study of these parameters with several DOE This warpage behavior is very critical for overall process flow, manufacturability and overall yield. But reliability is another key challenge for products. So reliability evaluation was also carried out for different material DOE sets to investigate best materials for 300mm ewlb packages. In the comprehensive study of reliability study, final material set was selected for final test vehicle fabrication. B. Comparison of process variation between 200mm and 300mm. With test vehicles of 5x5mm die in 8x8mm ewlb, each of the major process variables are monitored and compared. Figure 8 shows the die displacement or movement after wafer level molding and comparison of 200mm and 300mm carriers. As shown in figure, 300mm shows quite small die shift as similar as 200mm case after process optimization and 2011 13 th Electronics Packagingg Technology Conference
stabilization. Cu plating thickness, dielectrics thickness, ball shear strength are key comparison variables to investigate 300mm ewlb process stability as compared to 200mm ewlb. Figure 8. Comparison of die shift and movement after wafer level molding in 200mm reconstituted wafer and 300mm ewlb reconstituted wafers. 300mm ewlb has larger standard deviation than 200mm mainly due to 230% increase in area, but measured average value and its standard deviation values in 300mm ewlb is close to 200mm in most cases. These shows the stability of 300mm ewlb process developed and established from 200mm baseline. C. Component level and Board level reliability test result For 300mm ewlb package s reliability tests, test vehicle were prepared with 5x5mm die size in an 8x8mm package size with 183 solder balls. JEDEC standard reliability tests were carried and ewlb passed all reliability conditions. For board level reliability, JEDEC TCoB (temperature cycle on board) and drop test were carried out and it also successfully passed all test requirements. Figure 8 shows board level drop test performance and it showed first failure was over 100 drops in industry standard test conditions. Figure 9. Weibull plot of TCoB and Drop test reliability results of 300mm ewlb wafers. D. Next movement for large scale ewlb; panel approach Significant cost and productivity advantages can be achieved with the larger scale ewlb wafer format as compared to the existing WLB wafer format due to higher efficiency and economies of scale. For 12 x12 square panel, it has more than 30% more area compared to 300mm ewlb wafer because square panel can save corner space. Figure 10. Potential trend of area increase with panel scale approach; more throughput with lower cost and economies of scale Figure 11. Scale of economics of ewlb; moving to large scale; panel approach for further cost reduction Economies of scale arise when the cost per unit falls as output increases. Economies of scale are the main advantage of increasing the scale of production and becoming big. 2011 13 th Electronics Packaging Technology Conference
Firstly, because a large business can pass on lower costs to customers through lower prices and increase its share of a market. Secondly, a business could choose to maintain its current price for its product and accept higher profit margins. Based on Fan out-wafer Level Packaging cost comparison study from SavanSys Solutions and TechSearch [3], for all die sizes in the 6x6mm and 8x8mm ewlb packages, there is a significant cost advantage. However, the cost of fan out- WLP is much higher for larger packages. This is largely due to the fact that Fan Out-WLP technology is a semiconductor process, as opposed to flip chip and wire bond packaging which is primarily a printed circuit board (PCB) process. PCB processes use a large fabrication panel compared to the wafer used for a semiconductor process. For small packages, the wafer versus panel size difference is not as significant as with large packages. So moving to large scale ewlb with panel approach, ewlb would be on further cost-effective solution with inline batch process of fab technology. REFERNCES [1] M. Brunnbauer and Thorsten Meyer, Embedded Wafer Level Ball Grid Array (ewlb), IMAPS Device Packaging Conference 2008, 17-20 March 2008, Arizona, US (2008) [2] Graham pitcher, Good things in small packages, Newelectronics, 23 June 2009, p18-19 (2009) [3] Chet A. Palesko, Amy J. Palesko and E. Jan Vardaman, COST COMPARISON FOR FLIP CHIP, WIRE BOND, AND WAFER LEVEL PACKAGING, Proceedings of IWLP2010, Santa Clara, US (2010) V. CONCLUSION Advanced packaging plays a crucial role in driving products with increased performance, low power, lower cost and smaller form factor. The industry requires innovation in packaging technology and manufacturing to meet current demands and the ability to operate equipment in high volume with large throughput. ewlb technology is an enhancement to standard WLPs, allowing the next generation of a WLP platform due to its fan-out capability. ewlb is a low-cost solution with batch process and larger area utilization such as 300mm wafer and panel approaches. The ability to integrate passives like inductors, resistors and capacitors into the various thin film layers, active/passive devices into the mold compound and 3D vertical interconnection opens additional design possibilities for new Systems-in-Package (SiP) and 3D stacked packaging. Moreover, 3D ewlb technology provides more value-add in performance and promises to be a new packaging platform that can expand its application range to various types of devices as well as 3D TSV integration for true 3D SiP systems. For further cost reduction approach after 300mm ewlb, scaling-up such as panel approach would be next steps to move. It provides bbreakthrough productivity, compatible process for advanced Si node devices as well as functional Integration /combination of different node devices (32nm, 28nm or 22nm) with RF, discrete or memory devices. Electronic product differentiation today is driven by everexpanding functionality, feature sets, multi-functionality and faster communications. At the same time, consumers have made clear their desires for feature-rich products in compact form factors to enable maximum portability. ewlb technology is successfully enabling semiconductor manufacturers to provide the smallest possible, highestperforming semiconductors as cost-effective packaging solution. ACKNOWLEDGEMENT Authors appreciate Mr. Chow Seng Guan, for thermomechanical simulation of warpage behavior, design and characterization group in Statschippac LTD. 2011 13 th Electronics Packaging Technology Conference