EPRC 12 Project Proposal 3D Embedded WLP 15 th August 2012
Motivation Factors driving IC market Higher density, lower cost, high yield Fan-out WLP/eWLP advantages Small footprint, low profile Low cost, better performance Can ewlp play a bigger role in future 3D IC? Extend ewlp to higher pin count application in PoP format? Page 2 Yole report 2011
FO-PoP Challenge and Target Application ewlp Apple A4 processor in ipad PoP Pkg: 14 x 14 mm 2, 27x27 (729) depopulated BGA Die: 7.3 x 7.3 mm 2 Conventional PoP, with TMV Challenge: Digital + Memory modules, Analog + Digital + Memory modules, Wireless baseband SOC Higher pin count to ~800 Needs of multi RDL layers Cost Impact! PoP format Through Mold Via formation (Via first, Via middle or via last) Manufacturability Impact! Large embedded Package Warpage, thermal concerns, high stress and board level reliability issue 2011 ECTC Page 3
Project Objective To develop embedded wafer level packaging for low to high I/O applications, including the following: Fine pitch thru-mold-via process development Electrical design to achieve 600-800 I/O on 2 layer RDL with signal/power integrity consideration 60 GHz RF components including design of antenna-on-package (AOP), function modules, and EMI shielding (0 60 GHz) Thermal solution for FO-PoP with power dissipation 1-4 W Wafer level mold flow characterization and optimization for die + embedded passives Package- co-design and TMV effect study to reduce warpage/stress and enhance BLR Proposed Test Vehicle: FO-PoP with TMV for low/medium/high I/O To be finalized with members input Page 4
Challenges to be Addressed Fabrication of Thin Mold Wafer Use of carrier wafer; TBDB RDL adhesion on mold wafer Electrical Property Extraction Ring resonator New methodology to exclude conductor loss Thermal Management of 3D EMWLP Solution for 1-4 W power consumption Guideline to reduce thermal resistance High-freq RF Integrated in FO-PoP 60 GHz RF/antenna design 60 GHz EMI shielding design Embedded Passives Passives embedded inside molded compound during reconfiguration process Mold flow simulation to provide design input to the layout of the package to minimize shift of the components Solder Joint Reliability of TCOB Modeling of package structures Stress analysis of FO-PoP Corner Epoxy to enhance the SJR Medium to High I/O Count with 2 RDL layers Pkg+ co-design E-analysis to ensure SI/PI Fine Pitch Through Mold Via Fast throughput laser drilling Batch electroless/electroplating of copper along side wall of TMV Filling of the TMV Page 5
Proposed Test Vehicle FO-PoP with TMV for high I/O (for high I/O electrical design, process development, mechanical design and reliability test) FO-PoP with TMV for low/medium I/O (for high freq RF components and thermal enhancement design) Die Solder Die Top Package Bottom Package Die Size 5.5 x 5.5 mm 2 7.5 x 7.5 mm 2 Package Size Number of I/O Number of RDL Solder Ball Pitch 8 x 8 mm 2 14 x 14 mm 2 200 (Depopulated) 2 2 700 (Depopulated) 0.5 mm 0.5 mm Top Package Bottom Package Die Size 3 x 3 mm 2 4 x 4 mm 2 Package Size Number of I/O Number of RDL Solder Ball Pitch 5 x 5 mm 2 8 x8 mm 2 36 68 2 2 0.5 mm 0.5 mm Page 6 * Pending members input
RDL and TMV Fabrication Objective To develop multiple layers of re-distribution metal layers on both side of thin molded wafer To develop side wall plated through mold via Challenge Adhesion of copper layer on rough side wall of TMV Outgassing of mold compound inhibit the adhesion of RDL layers on Mold compound Dielectric material adhesion on mold compound Handling of thin molded wafer Alignment of the RDL with the pad on the dies due to die position shifted Chip capacitor attachment and interconnects with the chip Scope Understand the impact of surface roughness of the mold compound on RDL adhesion Study of out-gass of the organic material relationship with the thermal pretreatment Via formation study in terms of aspect ratio; side wall plating, via filling and reliability Study of the reconfiguration process (type of plate material, placement compensation, molding parameters) to minimise the magnitude of die shift 500um 2011 ECTC Side wall Plated TMV Page 7
High I/O Design and Dielectric Material Characterization Objective To achieve ~700 pin FO-PoP with 2 RDL while having signal and power integrity To enable signal channel of logic+mem for DDR2 application in FO-PoP To characterize dielectric constant and loss tangent of materials Challenge Routing difficulties with only 2 RDL layers. No place for signal and power ground, which result in signal/power integrity issues; Testing structure unavailable to accurately characterize dielectric property; Difficult to separate dielectric loss and conductor loss in printed structures Scope Develop methodology for pkg+ co-design to achieve ~700 pins with 2 RDL in package Data link characterization up to 10 GHz in proposed FO-WLP platform (return/insertion loss, coupling and impedance control) Power distribution network (PDN) analysis Signal channel enablement thru SI design (pulse response, crosstalk and eye diagram) Develop new wideband method to measure and benchmark dielectric properties (Dk and loss tan) of thin film and mold compound w/o conductor loss Page 8 Package + co-design Transmission line optimization Signal integrity Instrument to measure dielectric properties
60 GHz RF Components Design Objective To realize antenna-on-package (AOP) on FO-PoP for 60 GHz wireless application To develop low-cost electrical shielding solution to RF devices for <60 GHz EMI interference To design IPD functional blocks for 60GHz transceiver front-end Challenge Integration of antenna in the IC package with small footprint; RF chips are vulnerable to electromagnetic interference (EMI); Normal shielding techniques use additional metal case/plating which increase cost significantly Scope 60 GHz antenna design and testing with feeding structure on top of FO-PoP package EMI shielding design up to 60 GHz utilizing through-mold-via in FO-PoP package; Shielding Effectiveness (SE) simulation and optimization Design and characterization of IPD function blocks (resonator, filter and duplexer) for 60GHz transceiver front-end Antenna-on-package EMI Shielding Conductive coating Feeding Port Electrical TV1 Electrical TV2 (simulation) US Patent 7851894 Page 9
Thermal Modeling of 3D EMWLP Objective To provide thermal solution for for logic + memory with power dissipation of 1 4 W To develop design guidelines for FO-PoP to reduce thermal resistance and enhance thermal performance Challenge Increased heat flux in complete package Thermal cross-talk between top and bottom packages complicates heat removal Considerable thermal resistance between and through packages due to low conductive materials Scope Heat transfer and package-level thermal resistance modelling of FO-PoP Parametric study on the effect of solder ball array geometry and solder pad design on heat transfer Thermal management guidelines for reduction of inter-package thermal resistance and improved heat removal for 3D EMWLP, by analyzing the following: Effect of thermal enhancement structures Explore the impact of top-side thermal solutions (heatspreader, etc) Heat Heat Junction Temperature for Two types of Structures (Top: 1W & Bottom: 2W) Thermal Resistance between Packages CHALLENGES: Increased heat density, thermal cross-talk & interpackage thermal resistance Die Die Solder Proposed Thermal Enhanced Structures Proposed thermal enhanced Package Embedded Wafer Level BGA (ewlb) Top Package 84.1 C 116.4 C Bottom Package 75.6 C 111.3 C Page 10
Wafer Level Molding Modeling and Characterization Objective To develop methodology of mold flow simulation for compression molding To achieve full mold fill by optimizing the molding parameters To investigate the effect of die/decap size, distance between die and decaps and location/orientation of decaps on mold flow filling Scope Mold flow model development for embedded modules with various components inside it Generate a versatile model to adapt different sizes and placement of components Characterize time-dependent viscosity of mold compound and evaluate its effect of on mold flow. Mold compound exhibits complex behavior w.r.t time and temperature Validate and improve mold flow simulation model by comparison to experiment results Parametric study of the effect of die/decap size, distance between die and decaps, and placement of decaps on mold flow simulation results Design guidelines of achieving good mold fill in wafer level molding process Die Page 11 Location/orientation of passive wrt the die
Mechanical Design Proposal Top package Bottom package Objective To minimize package/wafer warpage and Enhance solder joint reliability through parameter optimization Package Level Warpage Scope Analysing the impact on warpage by balancing the structure through overmold/die/rdl thickness Pkg- co-design and parametric study on FO-PoP with thru-mold-via (TMV) to minimize warpage and enhance board level reliability (BLR) TMV placement, package design and solder joint interaction during TC Study the impact of corner adhesive in enhancing the BLR Generate dedicated design rule of TMV and FO- PoP structures for better solder fatigue life Electronic Components and Technology Conference (ECTC), 2010 Balanced structure ECTC, 2012 Solder Joint Reliability ICQR2MSE, 2011 Page 12
Project Flow Wafer Level Warpage Simulation PoP Warpage Analysis Solder Joint Reliability Analysis Thermal Solution Design Package & Co- Design Material Characterization Process Optimization Members Input Test Vehicles Specification Design & Analysis Wafer Level Process Assembly Process Reliability Testing & Failure Analysis Compression Molding Modeling and Process Fabrication Process including TMV and Embedded Passives Thin Wafer Handling Project time line and schedule: Nov 2012 April 2014 (18 months) Page 13
Possible Research Outcome Design, Simulation and Characterization Package + co-design to achieve 600 800 pins on 2 RDL layers with signal/power integrity consideration 60 GHz RF component: antenna-on-package; function blocks (filter, resonator and duplexer); EMI shielding 0 60 GHz Extraction of dielectric constant and loss tangent for thin film and mold compound excluding conductor loss Thermal solution and guideline for high pin count PoP with power dissipation 1-4W Wafer level mold flow characterization and optimization for memory die + 2 decaps Design rule to reduce stress and warpage, and enhance board level reliability Process Dielectric process development and characterization Dielectric/RDL adhesion on mold compound Lithographic process optimization Through mold via formation Laser drilling process study: different aspect ratio Copper adhesion on side wall of TMV Embedded passives in mold compound Package Assembly Evaluation of assembly material FO-PoP assembly process Package Reliability Evaluation Package reliability evaluation results and failure analysis Page 14
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