Pouzdření pro moderní elektronické aplikace Ing. Jiří Starý, SMT Plus 17. října 2011 1
Od čipu k pouzdru a aplikacím
Obsah přednášky Cu Wire, Multi-row QFN, Stacked Die, Flip Chip CSP, Cu Pillar Conventional IPD, Packages WLCSP, Fanout, Embedded Packages Deep Submicron (Low K, ELK, ULK), CPI, Si Interposer, TSV, TSV Die Assembly Large Die/Package FCBGA 3
Postup pouzdření Package Roadmap 4
25+ Years of Semiconductor Packaging Embedded FCBGA TSV WLCSP Polymer WLCSP IPD RF-Module P-DIP PLCC SOJ Enhanced QFP QFP SOP LQFP TQFP TSOP SSOP Enhance d BGA BGA Film BGA LBGA ubga TFBGA (mini BGA) Bumping BCC FCCSP LGA Finger Print COS BGA Sensor MCM BGA Stacked-BGA VFBGA WFBGA Hybrid FC+WB PIP PoP Fan out WLCSP FC PiP MAP- POP FC-POP as 3 BGA 3D-TSV FC-QFN QFN aqfn Leading edge CMOS node (approx): 0.25um 0.18um 0.13um 90nm 65nm 40nm 28nm 1985 1990 1995 2000 2005 2010 2015 Sophistication & diversification increasing over time 2011
Packaging Roadmap ASIC 1 st Generation LF & TAB 2 nd Generation BGA More Moore 90nm 3 rd Generation FC, WL & SiP 4 th Generation TSV, WL SiP 20 nm FCBGA LK 40nm LF LF 28nm ELK LF 20nm ULK 2.5D IC SiP Cu Pillar plating TSV 3D IC SiP QFP HD PBGA FCCSP Cu Wire aqfn CoC a-fccsp as 3 Module PDIP PLCC SOJ SOP W/B Package QFN FBGA MCP Stacked Die SBS FCCSP Hybrid CoC FC+WB FCCSP FCCSP Overmold module System Integration PiP / PoP PoP TRD PoP WLCSP WLCSP/aCS P MAP PoP awlp Conformal Shielding Bare-die FC PoP amap PoP Exposed-die Exposed-die amap FC PoP PoP SBS awlp awlp PoP CoC PoP awlp+discrete awlp PoP 3D IC PoP EDS PoP aedsi aedsi PoP 1984 1990 2000 2008 2009 2010 2011 2012 2015
Pouzdra na úrovni čipu Wafer Level Packaging (WLP) 7
WLP Packaging Technology 8
Vývoj pouzder kopírujících velikost čipu Integrated Wafer Level Packaging iwlp Wafer Level Chip Scale Package (WLCSP) Wafer Level Fan-out Package (awlp) Wafer Level Through Silicon Via (WLTSV) Wafer Level Integrated Passive Devices (WLIPD) Advanced Development iwlp Wafer Bumping Single Die awlp Memory Stacking Integrated R/L/C WLMEMS Ball on Nitride WLCSP Multi Die 2D 2 Die Side by Side Silicon Interposer Stacking Integrated xfrmr, Balun, Diplexer Additional WLP Development Repassivated WLCSP Through Vias Double sided RDL/Pads Multipurpose Die Stacking Integrated Die & Passives Current WLP Redistributed WLCSP Vertical Stacked Multi-die Modules Double Sided WLCSP New WLP Opportunities 9
Next Generation: WLCSP Fan-out WLP Fan-In WLCSP Fan-Out Molded Area Fan-Out WLP Chip RDL Metal RDL Dielectric Layers 10
awlp Basic Process Flow Wafer Saw Wafer Reconstitution Wafer Redistribution awlp Package with Solder Balls & Singulated 11
awlp Reconstituted Wafer - Infineon 12
Reconstituted Wafer
Advantages of awlp over FCCSP Improved electrical performance 66% reduction in Resistance & Inductance over FCCSP Better thermal performance >30% reduction in thermal resistance Size reduction 29% reduction in package volume Allows finer pitch pad array, allowing for die size reduction at advanced technology nodes FCCSP >=150µm awlp = 80µm Allows 2D & 3D Multiple die packages
Opportunities for awlp WLCSP Alternatives Allows the manufacture of WLCSP Like packages where the die is smaller than the ball array. FCCSP Migration of FCCSP to Fanout WLP. High Frequency Applications Infineon demonstrated 77 Ghz device in ewlb Multiple Die & SIP Solutions Combine die and/or discrete devices into multiple die packages using 2D and 3D structures. Through polymer vias for double-sided metallization and connectivity.
First ewlb/awlp Production Devices RDL routing and balls Examp le: AGOLD radio+ PG- WFWLB -216 Cross section - Infineon
awlp Evolution Roadmap Basic Single Die awlp Package 2D Multiple Die Package 2D Multiple Die/Passives Package awlp Package On Package (awlpop) Double-sided awlp Package with Backside components (3D Module)
Wafer Level Through Silicon Via (WLTSV) Integrated Wafer Level Packaging iwlp Wafer Level Chip Scale Package (WLCSP) Wafer Level Fanout Package (FOWLP) Wafer Level Through Silicon Via (WLTSV) Wafer Level Integrated Passive Devices (WLIPD) Advanced Development iwlp Allows Silicon die stacking, wafer stacking, and back side interconnections. ASE is developing this technology for: Silicon Interposers 3D Stacked wafers and/or die MEMS Wafer Level Packages Double sided WLCSPs -VTI Technologies
Wafer Level Integrated Passive Device (WLIPD) Integrated Wafer Level Packaging iwlp Wafer Level Chip Scale Package (WLCSP) Wafer Level Fanout Package (FOWLP) Wafer Level Through Silicon Via (WLTSV) Wafer Level Integrated Passive Devices (WLIPD) Advanced Development iwlp Allows integration of Inductors, Couplers, Resistors, and Capacitors into WLPs.
Kontaktování měděným drátkem Copper Wire Bond 20
Cu Wire Bond Proliferation: Advantages of Cu Wire bond becoming better known in industry, main driver is cost Migration from gold wire to cu wire for fine wire applications is moving quickly ASE conversion accounts for over 29% of total wire bond shipments, expected to reach >40% by end of 2011 21
Motivation: Significant cost benefit Expect 8% - 15% saving 100% Wire Cost Other Cost August 22 nd, 2011: 1,898$USD/ounce 50% 0% Wire Bond Package (Au Wire) Wire Bond Package (Cu Wire) Challenges : Surface Oxidation. Higher hardness. Al pad splash. Slow IMC growth. Cu Corrosion.
Cu Wire Bond Over three years in production 4+ billion units shipped: vast experience Multiples sites Taiwan, China, Korea, Japan, Malaysia Broad spectrum of market applications Cu wire bond at deep submicron nodes
Cu Wire Bond Technology 5000+ Cu Wire Bonder sets installed by Q2 2011 Aggressive ramp, culminating in 6700 sets by end of 2011 8000 6000 4000 2010 2011 4300 3700 3250 2500 5000 6000 6700 2000 1300 0 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Cu Wire Bond Shipments Billion units 5 4 3 2 More than 2 Billion units 2008 + 2009 + 2010 4.2 Billion units by the end of 2011 1 0 2008 2009 2010 2011 Estimates
Industry Migration by Package Cu wire bond shipments for QFNs 7.2% of 2010 unit shipments 19% of 2011 unit shipments Projected to be 78% in 2015 Cu wire bond shipments for PBGAs 4% of 2010 unit shipments 10% of 2011 unit shipments Projected to be 72% of unit shipments in 2015 Cu wire bond shipments for FBGAs 2.8% of 2010 unit shipments 8% of 2011 unit shipments Projected to be 36% of unit shipments by 2015 Cu wire bond shipments for stacked die CSPs Less than 1% of 2010 unit shipments 4.4% of 2011 unit shipments Projected to be 32% by 2015 Stacked die slowest application to transition, two-die stacks in early production, high number of die stacks remain in gold due to mechanical and material requirements of thin die Source: Techsearch International August 2011 26
Cu Wire Bond Package Type 2009 Shipment by Volume 2010 Shipment by Volume 2010 Shipment by Revenue FBGA 7% PBGA 4% SOIC/ PLCC 14% TQFP 8% aqfn 0.3% QFN 16% LQFP 43% PQFP 8% PBGA 12% FBGA 18% SO/PLCC 7% TQFP 7% aqfn 1.5% LQFP 24% QFN 25% PQFP 6% BGA 47% SOIC/ PLCC 4% Discrete 1% QFN; 15% QFP 33%
Cu Wire Bond Wafer Technology 2010 Wafer Technology 2009 Wafer Technology 0.35um 10% 0.25um 5% >=0.4um 14% 65/60 nm 2% 90/80 nm 10% 0.13um 22% 0.25um 3% 0.35um 9% >= 0.4um 12% 40/45 nm 1% 60/65 nm 7% 0.13um 18% 90/80 nm 14% 0.18um 37% 0.18um 36%
Cu Wire Bond - Applications 2010 Applications 2009 Applications Auto 0.2% Communic ation 21% Power 10% Computing 15% Communication 24% Power 8% Computing 20% Consumer 54% Consumer 48%
Technology Roadmap Technology HVM Available 2011 2012 2013 Min wire Dia. 18(um) 18 15 15 15 Die pad structure Tri-tiers/ Quadtiers Tri-tiers/ Quad-tiers Tri-tiers/ Quad-tiers Tri-tiers/ Quad-tiers Tri-tiers/ Quad-tiers Cu Wire Technology Min bond pad pitch Min bond pad opening Cu-LK wafer technology Bond pad surface Al Al 50(um) 45 40 40 40 40(um) 40 35 35 35 90/65(nm) 45/40 28 20 20 Al / Au / Ni-Au / Ni-Pd / Ni-Pd-Au Al / Au / Ni-Au / Ni-Pd / Ni-Pd-Au Al / Au / Ni-Au / Ni-Pd / Ni-Pd-Au Low loop 75um 75um 55um 45um 45um Pad to pad Au+Cu Au+Cu Cu only Cu only Cu only
2010 Worldwide Copper Capacity Addition In 2010, ASE was the most aggressive in Cu bonder addition Cu Bonder Installation by Region 2010 IDM & SATS combined: 13K to 15K total Korea 1% Japan 3% Thailand 1% Europe 0% America 0% Others 2% Singapore 4% OSAT: ASE, SPIL IDMs: STM, FCS China 12% Taiwan 39% ASE SPIL Philippines 18% IDMs: TI, Renesas, FCS, On Semi Malaysia 20% OSAT: Carsem, Unisem IDMs: TI, Renesas, FCS Source: Kulicke & Soffa, Feb 2011. Gartner, Dec 2010.
3D integrace s mezivrstvovými propojkami (TSV, Through Silicon VIA) 32
3D SiPs to Meet Product Trends - Technology Integration, Form Factor & Performance QFP
3D IC TSV Package Development in ASE TSV in development since 2007 CIS TSV since 2008 (Via Last) Image Sensor Digital Signal Processor Si interposer since 2008 MEMS TSV in 2010 (Via Last) Memory stack on Logics since 2008 Heterogeneous chip integration in 2010 + Memory Logic / CPU RF MEMS Memory Processor Si Interposer
Wafer Level Capabilities for 3D Via Formation Package Thin Wafer Handling - 100 um thick - 50 um under develop Double Side Photo- Litho - 15um/ 15um L/S qualified - 10um/10um L/S pro type - 2L metal layer - 20~100 um via - Aspect ratio 6~7 - Full-fill and lining available Microbump - 20um size/ 40um pitch - AR > 2.5 - Plating uniformity < 10% 40 um pitch Microbump
TSV Structure - with Polymer Isolation Isolation thickness up to 10 + um Good electrical performance & low leakage Good sidewall conformity & uniformity Low process temp. (<250ºC) Low via/ Si stress 12 um isolation/ 230um depth
Major Process Challenges & Capabilities Micro bumps (C2C/C2W) Solder bump (100um) C2C/C2W Bonding Thermo-sonic bonding Thermo-compression bonding High precision FC bonding (3um) TSV-Via Last Au stud bump (50um pitch) Cu pillar/cu post (40um pitch) Micro solder bump (100um) Au stud Top chip Bottom chip 40um pitch Cu pillar F2F w/ wire bond Thin Wafer Handling 100um chip-to-substrate (qualified) 50um chip-to-substrate (Prototype available) 50um chip-to-chip (under development) Encapsulation CUF (< 15um gap) NCP NCF Wafer level dispenser (12 ) Bump pitch (chip-to-substrate) Cu pillar bump 80um/40um (under development) Solder bump 150um Au stud bump 60um 60um
Assembly Process Flow ASIC with RDL & Bump Wafer Saw Substrate Wafer Backside Grinding Si interposer die FC Si interposer Wafer saw ASIC die FC Underfill dispensing & cure Reflow oven Ball Mount & Singulation
2,5 D Si mezivložka 2.5D Si Interposer 2.5D IC Middle-end & Assembly
Si Interposer Benefits Alleviate ELK/ ULK stress in large die Bridge organic substrate gap for dense & complex substrate Package advanced wafer node w/ tighter bump pitch Integrate multi-chip SiP platform Match advanced wafer pitch Fan-out to match existing substrate capability Chip 1 Chip 2 Si Interposer Si - Si to minimize CTE impact on ELK
Si Interposer Enabling Chip Integration Alternative SoC Solution (Allow IC designer to partition chips and re-organize in Si interposer platform) Provide platform for heterogeneous chip integration (IPD, MEMS, Sensor ) +
Si Interposer Incorporate IPD solution Prototype : June 10 Capacitor Capacitance: 824 pf /mm 2 Range: 0.6-4600pF Resistor Rs value: 85 ohm/sq Standard type: 12 10k ohm Inductor Inductance: 1~15nH Diplexer Balance Filter Band Pass Filter Balun
3D Si Mezivložka 3D Si Interposer 3D IC Middle-end & Assembly
Memory on ASIC Assembly Process Flow (D2S) Processor wafer 1. Processor Wafer (w/ Cu pillar bump) carrier 2. Mount processor wafer onto Carrier carrier 3. Middle-end Process carrier 4. Release Processor Wafer from Carrier 5. Processor Wafer Dicing 9. Marking, Ball Mount & Singulation Saw 8. Wafer Level Mold 7. Memory die TC Bonding to Processor * 6. Processor die TC Bonding to Substrate * ASE has developed a proprietary solution to control warpage
2.5D & 3D IC FC Assembly Capabilities C2C / C2W Bonding Micro Bumps (C2C / C2W) Thermo-sonic bonding Thermo-compression bonding High precision FC bonding (3um) Cu Pillar/Cu Post (Pitch=40um) Micro SnAg Solder Bump (Pitch=100um) Thin Wafer Handling C2S (H= 100 um, Ready) C2S (H=50 um, Prototype) C2C (H=50 um, Developing) Underfill CUF (< 15um Gap) Wafer Level Dispenser (8 ) MUF (Developing) Solder Bump (C2S) Cu Pillar Bump (Pitch=72um, Developing) Solder Bump (Pitch=150um)
2.5D & 3D IC FC Assembly Capabilities 50um thick bottom die 20um bump size/ 40um bump pitch 80um bump size/ 150um bump pitch
Concurrent Design on Electrical, Thermal & Mechanical Performance TSV RLC Modeling System Thermal Analysis 10% 9% Stress / Reliability Modeling Via R, L, C Modeling 81% Electro-Thermal Current Crowding Modeling Viscoplastic/ Creep Constitutive Model Darveaux/ Coffin-Manson Fatigue Model Validation Chip Substrate Maximum Stress Bump Crack Inter-delamination
Future 3D SiP Integration - Leverage building block portfolio (Ultimate SiP, System-in-a-Package) 3D TSV Embedded Actives Embedded Passives IPD EMI Shielding WLCSP Stacked Dies Advanced Materials (UF, MCP, Epoxy,..)
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