Material based challenge and study of 2.1, 2.5 and 3D integration

Similar documents
Novel Materials and Activities for Next Generation Package. Hitachi Chemical., Co.Ltd. Packaging Solution Center Hiroaki Miyajima

IME Technical Proposal. High Density FOWLP for Mobile Applications. 22 April High Density FOWLP Consortium Forum

Henkel Enabling Materials for Semiconductor and Sensor Assembly. TechLOUNGE, 14 November 2017

An Innovative High Throughput Thermal Compression Bonding Process

Chips Face-up Panelization Approach For Fan-out Packaging

3D Package Technologies Review with Gap Analysis for Mobile Application Requirements. Apr 22, 2014 STATS ChipPAC Japan

SLIM TM, High Density Wafer Level Fan-out Package Development with Submicron RDL

Copyright 2009 Year IEEE. Reprinted from 2009 Electronic Components and Technology Conference. Such permission of the IEEE does not in any way imply

Challenges and Solutions for Cost Effective Next Generation Advanced Packaging. H.P. Wirtz, Ph.D. MiNaPAD Conference, Grenoble April 2012

Avatrel Stress Buffer Coatings: Low Stress Passivation and Redistribution Applications

Cu Pillar Interconnect and Chip-Package-Interaction (CPI) for Advanced Cu Low K chip

Development and Characterization of 300mm Large Panel ewlb (embedded Wafer Level BGA)

TSV CHIP STACKING MEETS PRODUCTIVITY

IMPLEMENTATION OF A FULLY MOLDED FAN-OUT PACKAGING TECHNOLOGY

Panel Discussion: Advanced Packaging

TGV and Integrated Electronics

Die Attach Materials. Die Attach G, TECH. 2U. TECHNICAL R&D DIV.

3D-IC Integration using D2C or D2W Alignment Schemes together with Local Oxide Reduction

Recent Advances in Die Attach Film

Molding materials performances experimental study for the 3D interposer scheme

Encapsulation Materials Technology For SiP in Automotive

5. Packaging Technologies Trends

S/C Packaging Assembly Challenges Using Organic Substrate Technology

3DIC Integration with TSV Current Progress and Future Outlook

Challenges of Fan-Out WLP and Solution Alternatives John Almiranez

WF6317. A superactive low-volatile/high heat-resistant water-soluble flux for ball soldering

IME Proprietary. EPRC 12 Project Proposal. 3D Embedded WLP. 15 th August 2012

23 rd ASEMEP National Technical Symposium

Mechanical Behavior of Flip Chip Packages under Thermal Loading

Henkel Adhesive Solutions for SiP Packaging. October 17-19, 2018 Shanghai, China

II. A. Basic Concept of Package.

Next Gen Packaging & Integration Panel

First Demonstration of Panel Glass Fan-out (GFO) Packages for High I/O Density and High Frequency Multi-Chip Integration

Innovative Substrate Technologies in the Era of IoTs

Two Chips Vertical Direction Embedded Miniaturized Package

Outline. Market Size Industry Trends Material Segment Trends China Summary. Packaging Materials Market Trends, Issues and Opportunities

3D-WLCSP Package Technology: Processing and Reliability Characterization

Packaging Effect on Reliability for Cu/Low k Damascene Structures*

Challenges for Embedded Device Technologies for Package Level Integration

BGA Package Underfilm for Autoplacement. Jan Danvir Tom Klosowiak

Ultralow Residue Semiconductor Grade Fluxes for Copper Pillar Flip-Chip

MEPTEC Semiconductor Packaging Technology Symposium

Nanium Overview. Company Presentation

Anisotropic Conductive Films (ACFs)

Wafer Level Molded DDFN Package Project Duane Wilcoxen

Narrowing the Gap between Packaging and System

PoP/CSP Warpage Evaluation and Viscoelastic Modeling

Development of Super Thin TSV PoP

Cost effective 300mm Large Scale ewlb (embedded Wafer Level BGA) Technology

Warpage Mechanism of Thin Embedded LSI Packages

Glass Carrier for Fan Out Panel Level Package

Interconnection Reliability of HDI Printed Wiring Boards

Simulations and Characterizations for Stress Reduction Designs in Wafer Level Chip Scale Packages

Modelling Embedded Die Systems

Fraunhofer IZM Bump Bonding and Electronic Packaging

Board Level Reliability Improvement in ewlb (Embedded Wafer Level BGA) Packages

Flip Chip - Integrated In A Standard SMT Process

Wire-Bond CABGA A New Near Die Size Packaging Innovation Yeonho Choi February 1, 2017

Hitachi Anisotropic Conductive Film ANISOLM AC-8955YW. Issued 2007/03/30

Enabling Materials Technology for Multi-Die Integration

Flexible Substrates for Smart Sensor Applications

Sherlock 4.0 and Printed Circuit Boards

A Novel Material for High Layer Count and High Reliability Printed Circuit Boards

Power Electronics Packaging Solutions for Device Junction Temperature over 220 o C

A Flexible Vertical MEMs Probe Card Technology for Pre-Bump and ewlp Applications

Low Temperature Curable Positive Tone Photosensitive Polyimide Photoneece LT series. Toray Industries, Inc.

Assembly Challenges in Developing 3D IC Package with Ultra High Yield and High Reliability

FEM Analysis on Warpage and Stress at the Micro Joint of Multiple Chip Stacking

Bonding Technologies for 3D-Packaging

Advanced Analytical Techniques for Semiconductor Assembly Materials and Processes. Jason Chou and Sze Pei Lim Indium Corporation

Thermo-Mechanical Reliability of Through-Silicon Vias (TSVs)

Between 2D and 3D: WLFO Packaging Technologies and Applications

Electrical and Fluidic Microbumps and Interconnects for 3D-IC and Silicon Interposer

Semiconductor IC Packaging Technology Challenges: The Next Five Years

Basic PCB Level Assembly Process Methodology for 3D Package-on-Package

FABRICATION AND RELIABILITY OF ULTRA-FINE RDL STRUCTURES IN ADVANCED PACKAGING BY EXCIMER LASER ABLATION

Flip-Chip Process Improvements for Low Warpage

Encapsulation Selection, Characterization and Reliability for Fine Pitch BGA (fpbga )

Hot Chips: Stacking Tutorial

LTCC SYSTEMS and LTCC DESIGN RULES

Bare Die Assembly on Silicon Interposer at Room Temperature

ThunderClad 2. TU-883 HF Very Low Loss Material. Laminates & Prepregs Mass Lamination Service Insulated Metal Substrate Materials

LS720V Series. Comparison of crack progression between Sn-Cu-Ni-Ge and M773. Development of Ag-free/M773 alloy

Towards Industrialization of Fan-out Panel Level Packaging

Figure 1 Embedded Active and Passive Module (EMAP) Cross-section Schematic

Package Solutions and Innovations

Flip-Chip Process Improvements for Low Warpage

Selection and Application of Board Level Underfill Materials

Trends and Developments

Fine Pitch P4 Probe Cards

Hitachi Anisotropic Conductive Film ANISOLM AC-7106U

Optimized Cu plating in fan-out wafer-level packaging MultiPlate: a turnkey solution

Flip Chip Joining on FR-4 Substrate Using ACFs

The Development of a Novel Stacked Package: Package in Package

Statement of Work (SOW) inemi Packaging TIG SiP Module Moldability Project

Innovative Advanced Wafer Level Packaging with Smart Manufacturing Solutions YOON Seung Wook, Ph.D MBA

Technology Drivers for Plasma Prior to Wire Bonding

Modeling Printed Circuit Boards with Sherlock 3.2

TechARENA Packaging Exhibitor Session OCT/08, 2014 New WLP-Technology-Fusion Concept Steffen Kröhnert, Director of Technology, NANIUM S.A. V1.

Verifying The Reliability Of Connections In HDI PWBs

Transcription:

1 Material based challenge and study of 2.1, 2.5 and 3D integration Toshihisa Nonaka Packaging Solution Center R&D Headquarters Hitachi Chemical Co., Ltd., Sep. 8, 2016 Hitachi Chemical Co., Ltd. 2010. 2016. All rights reserved.

Outline 2 1. Hitachi Chemical Activity - Open Lab.- 2. Cu fine line fabrication regarding 2.1/2.5D 3. In-plane collective bonding with BFL film 4. Study of Vertical collective bonding 5. Summary H.Onozekii

HC Production Lineup 3 Dicing Tape Materials for Buffer Coating Interlayer Dielectric Materials Underfill Material Epoxy Molding Compounds CMP Slurry for Cu/Barrier Metal CMP Slurry for STI Die Bonding Film QFN Support tape Die Bonding Paste Photo Sensitive Dry Film High Density Interposer Printed wiring boards Liquid Encapusulant Solder Resist Build-up Materials Package Substrate

Activities of Packaging Solution Center Customer demands Customers Propose the total solution 4 Hitachi Chemical Packaging Materials / Adhesion / Elastic modulus / CTE etc. Material Properties Reliability Evaluation Hitachi Chemical Packaging Solution Center / Reflow resistance / TCT resistance / Warpage etc. Current Improvement Initial After MSL2 Initial After MSL2 / Stress Simulation / Warpage FEM : Finite Element Method Structure Analysis Package Assembly / Wafer dicing / D/B, TCB bonding / Mold (Transfer / Compression)

Activity of Open Laboratory Supports a materials & process in cooperation with customers Conventional Process New Process (Open Lab.) Material Presentation 5 Submission of Sample (Interaction) Customer s Evaluation Customer s approval Our Sample Offered customer s Device Assemble test in Open Lab. Fix the process condition & Propose the new materials combination / process with customer Customer s approval

Ex. Assembly Scheme in Open Lab. / Flip-chip, 3D, FO-WLP Chip 6 / FO-WLP (300 mm Wafer) Wafer (12inch) BG (Back grind) BG Tape/Temp. film DC (Blade Dicing) UF/DCT / Chip to Substrate / Chip to Chip / Chip to Wafer(300mm) FC PCB (Printed circuit Board) MCL/DFR/SR R/F TCB (Thermal compression bonding) Compres sion Mold MUF EMC RM UF High Accuracy Analyze CUF FC- PKG FC bonder(cow/tcb acceptable) NCP/UF film

High Accuracy Analysis Equipment IR Microscope Void Observation 3D X-rays Bump Connection 7 Shadow Moire Warpage &CTE Evaluation Spec Magnification : < X 1,000 Resolution : 0.65 μm 300 / 200 mm wafer SAM Delamination Observation Spec Resolution : < 0.10 μm Magnification : < X 2000 Sample : 508 x 444 mm SEM X-section Spec Sample : 400 X 400 mm Resolution : 3 μm XYZ axis strain and CTE calculation Strain Measuring Equipment Strain Evaluation Spec Sample : 350 x 350 mm Resolution 0.5μm Scan : 1,000 mm / sec Spec Resolution : 3.0 nm Magnification : X 5 ~ X 300,000 Spec Magnification : < X 1,000 Sample size : φ 50 mm, Sample Thickness : 10 mm Temperature : -100 ~ 420 o C

Evaluation Examples for Advanced PKG Table. Evaluation examples for each advanced PKG in Open Lab. 8 No. Items Specification Hitachi chemical materials TEG Image 1 Ultra-fine pitch FC PKG /Silicone & Organic interposer / Low stress underfill (2.1D/2.5D/3D PKG) / L/S=2/2 (w/customer) / RDL (Redistributed dielectrics) Top 4 stacked Bottom die Substrate / Chip to Wafer to Substrate (CoWoS) (Fine patterning, Low Dk type) / Bump pitch ; Min. 40 um / Ultra-low CTE core (CTE : <2ppm) / Dry film resist of fine-pitch (L/S=2/2) / High Tg Solder resist (Liquid/Film) 2 Thin stacked PKC / Die thickness : Min. 15 umt / Prepreg (Min. thickness : 15um) (Coreless PKG) / DAF thickness : Min. 3 umt / Low CTE & High modulus 32 Die Stack / Coreless prepreg : Min. 15 umt Solder resist film / Max. 32 Die stacked / Thin DAF (Thickness : Min. 3-5um) 3 WLP / 12 inch / Mold (Powder, Liquid, Film) (Fan out, Fan in type) / Panel size : Max. 640 x 495mm / Temporary bonding film / RDL first & RDL last process / RDL (Liquid, Film) Panel mold (640x495) Chip (1564 chip) 4 Wearable PKG / Flip-chip assembly to FPC / Low modulus mold materials / Bendable & Expandable (Liquid, Film & High transparency) / Low stress underfill / Low temp. curable conductive paste LED Flip chip (Paste, Film : 150 o C bonding)

9 1. Hitachi Chemical Activity - Open Lab.- 2. Cu fine line fabrication regarding 2.1/2.5D 3. In-plane collective bonding with BFL film 4. Study of vertical collective bonding 5. Summary

Background of Cu fine line interposer 10 Source: Yole D Fine line oraganic interposer technology is required.

Evaluation specification of Cu fine line 11 Structure of the test vehicle Si substrate Cu wiring was prepared by Semi-additive process Organic substrate AS500HS AS500HS AS-500HS: Low loss dielectric material Multi Layer structure Primer layer New high-functional resin system Material properties Items Properties Tg (TMA) 201 o C CTE (30-120 o C) / (200-250 o C) 18 / 42 ppm/ o C Elastic modulus (40 o C) 11.0 GPa Dk / Df (5GHz) 3.3 / 0.0034

Cu fine line fabrication on Si & Organic Sub. 12 Test vehicle Comb electrode L/S-2/2 (mm) Si substrate Organic substrate

Cu fine line fabrication results on Si (Cross section) 13

Cu fine line fabrication results on Si (Top view) 14

Laser via drilling and b-hast evaluation results 15 Top view of via Cross section of filled via Cu Si AS500HS AS500HS Laser : 355 nm Via diameter: 83 mm (Top) 77 mm (Bottom) b-hast evaluation results of L/S=2/2 mm 130 o C, 85%Rh, 3.3V Microscopic observation results after b-hast Degradation of insulation wasn t observed at 130 o C / 85%Rh for 200 hours.

16 1. Hitachi Chemical Activity - Open Lab.- 2. Cu fine line fabrication regarding 2.1/2.5D 3. In-plane collective bonding with BFL film 4. Study of vertical collective bonding 5. Summary

Status of 2.5/3D technology 17 Source:Yole D 3D die stacking usually uses TCB (Thermal Compression Bonding). TCB has many advantages in flip chip bonding, The productivity isn t high enough. 2.5/3D technology has been adopted only for high end products. Productivity enhancement of 2.5/3D may contribute to expand the market.

Bonding technology for 2.5/3D 18 Thermal compression bonding (TCB) is used for 2.5/3D die stacking TCB process for flip chip bonding. Item TCB process Mass reflow process Fine pitch interconnection Good Fair Warped die assembly Good Poor Productivity Poor Good C4: Mass Reflow Process TCB: Compression Bonding Line process One by one process Improvement of the low productivity is important to meet the various demands of the advanced packages like 2.5 and 3D multi die stacking.

How to enhance TCB productivity? 19 One die bonding by one process Plural die bonding by one process Bonding type Process image Concern Material solution In-plane collective Height deviation of bump and pad Substrate topology BFL (bonding force leveling) Film Vertical collective Temperature deviation among dies High thermal conductive material 3D collective Height deviation of bump and pad Substrate topology Temperature deviation among dies Combination of above 2?

Improvement of productivity in TCB process 20 Conventional TCB process Die TCB TCB head The die by die sequential process steps Die pick up Pre-bonding Substrate In-plane collective bonding Die placement Mounter head Main bonding Head cooling The improvement process of productivity Die pick up Large TCB head In-plane collective TCB Pre-bonding Multi dies main bonding

The concern of in-plane collective bonding 21 Die shift Less bonding force There are unevennesses of bump height and pad thickness, unflatness of substrate surface and unparallelism of bonding head to the stage. Those may cause the die shift and the less bonding force.

Idea of bonding force leveling (BFL) film 22 A conventional in plane collective bonding The die placement Mounter head In-plane collective bonding with BFLfilm In plane collective bonding Large TCB head Bonding force leveling film The difference in level on dies The eliminating difference in level on dies The new film inserted between the head and the dies can level the applied bonding force among the multi pre-placed dies.

Simulation study of leveling performance (model) 23 Items Evaluation of leveling performance of insertion film by smashed Au bump. Model Die size: 7.3 mm x 7.3 mm Die thickness: 300 μm Bump: Plated Au Bump count: 544 Bump pitch: 50 μm (peripheral) Bump height: 16 μm Method & condition Analysis method : FEM analysis Elastic-plastic Simulation Head Stage Die 10 μm Film Au bump The head was inclined to one corner which was 10 μm lower than the diagonal corner. Bonding force :0-100N (vertical direction) Film Head (Rigid body) Die Si E=183 GPa Au bump E=75 GPa (Yield stress=180 MPa) Various types of the films were evaluated.

Simulation Results of leveling performance 24 Film Without film Thermoplastic resin film Thermosetting resin film Modulus of film (at 25 o C) - 500 MPa 1.0 GPa Model of Contact Head Die Head Die Film Head Die Film Deformation of Au bump The maximum difference 7.8 μm 7.0 μm 1.9 μm : The position of head was inclined to one corner which was 10 μm lower than the diagonal corner. The thermosetting resin film insertion was very effective to the leveling of the bonding force.

Function thermosetting BFL film 25 Large TCB head BFL film Unevenness Unparallelism The BFL film is set up between the head and the dies which are pre placed on the substrate. Firstly, the compensating the height difference among the dies where the thermosetting resin layer melts and flows, and then cured Next, the multi die bonding where the bonding force is applied through the cured resin layer to change the shape of the resin to fit each die height.

The bonding force leveling effect by BFL film 26 Head Stage Die Film Au bump 10 μm Die size: 7.3 mm x 7.3 mm Die thickness: 300 μm Bump: Au plated Bump pitch: 50 μm (peripheral) Bump height: 16 μm Au bump Die Bonding head was inclined to one corner which was 10 μm lower than the diagonal corner.* 1 Die was forced to the stage by the head at 260 o C for 5s. Film Without film PTEF film BFL film (Thermosetting resin layer) Smashed bump height *1 Maximum difference 9.3 μm 7.1 μm 3.5 μm The film less press reflected the incline of the head to the bump height. The insertion of BFL film made the bump height deviation smaller than that of PTFE film.

Difference of bump height (μm) The effect of the elastic modulus of thermosetting resin layer on BFL 27 Head Stage Die 5 types of the cured BFL film which had different elastic modulus Au bump Die size: 7.3 mm x 7.3 mm Die thickness: 300 μm Bump: Plated Au Bump pitch: 50 μm (peripheral) Bump height: 16 μm Au bump Die A B Au bump Die Die was forced by the head to the stage at 260 o C for 5s. Observed difference of bump height = A - B (The density of Au bump is different from A in B) 8 7 6 5 4 3 2 1 0 1.0E+06 1.0E+07 1.0E+08 1.0E+09 1.0E+10 Elastic modulus (Pa) Elastic modulus of the cured thermosetting resin layer has higher bonding force leveling performance.

In-plane collective bonding experiment 28 Bonding condition Methods of Bonding Bonding force Bonding temperature Stage temperature Die placement Pulse heat Multi bonding 1st step 2nd step Die placement Constant heat Multi bonding N/die 50 50 50 50 50 s 5 6 15 10 20 o C 80 185 300 180 300 s 5 6 15 10 20 o C 80 80 80 80 80 Equipment Die placement: LFB-2301 (Shinkawa Ltd.) Multi dies main bonding: HTB-MM (Alpha Design Co., Ltd) Bonding head temperature: max. 450 o C (Pulse heating) max. 300 o C (Constant heating) Bonding force: 100 N - 5000 N Head size: 60 mm x 70 mm (Pulse heating) 100 mm x 100 mm (Constant heating) HTB-MM

Set up of in-plane collective bonding 29 Die size: 7.3 mm x 7.3 mm Die thickness: 100 μm Bump: Cu pillar Bump pitch: 80 μm (Peripheral) + 300 μm (Core area) Bump height: 45 μm Cu trace of substrate: 15 μm Substrate thickness: 0.36 mm 5 singulated die and substrate (D) (A) (C) (B) (E) 15 dies on a single substrate Pulse heating (A) (C) (B) (D) (E) Constant heating

In-plane collective bonding with BFL film <5 dies of singulated test vehicles> 30 Item Without film PTFE film BFL film Daisy chain test (NG/Total) 0/5 0/5 0/5 Die shift of the bonding Average of die shift 14.0 μm 11.1 μm 3.1 μm Void Void C-SAM observation of die A The BFL film shows good performance not only in the daisy chain test, but also die shift and C-SAM observation.

In-plane collective bonding with BFL film <15 dies on a single substrate > 31 Item Without film PTFE film BFL film Daisy chain test (NG/Total) 14/15 7/15 0/15 Die shift of the bonding Average of die shift 29.4 μm 26.6 μm 5.3 μm C-SAM observation of die A Void The BFL film suppressed the die shift more effectively than the others at 15 dies collective bonding. The through put of the process based on the main bonding condition was calculated to be 2700 UPH.

32 Thank you for attention!

33 The entry contents of these data based on the results of our experiment done until April. 2016 do not guarantee their characteristic values. The contents may be revised according to new findings if necessary. Please examine the process and the condition carefully and SEMICON confirm before Taiwan mass production. 2016