Apéndice 2. Programas. PLD GAL16v8

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Abigayle Ursula Allen
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1 Apéndice 2 Programas PLD GAL16v8 Name Daniel Ortega G; PartNo 00; Date 21/11/2005; Revision 01 ; Designer Engineer ; Company personal ; Assembly None ; Location ; Device g16v8 ; /* *************** INPUT PINS ******************** PIN 2 =p1 ; /* PIN 3 =p12 ; /* PIN 4 =s1 ; /* PIN 5 =s2 ; /* PIN 6 =s3 ; /* PIN 7 =os1 ; /* PIN 8 =os2 ; /* PIN 9 =os3 ; /* /* *************** OUTPUT PINS ******************** PIN 12 =s3_ ; /* PIN 13 =s2_ ; /* PIN 14 =s1_ ; /* PIN 15 =s33 ; /* PIN 16 =s22 ; /* PIN 17 =s11 ; /* s2_ = p1 $ p12; s3_ =!(p12); s1_ = p1 ; 89

2 s11 =!(!(os3) & s1) ; s22 =!(!(os1) & s2) ; s33 =!(!(os2) & s3) ; PIC 16F877 ;============================================================================= ;============================================================================= ; Author: Daniel Ortega G. ; Company: UDLAP. ; Revision: 1.00 ; Date: 2005 ; Assembled using MPASMWIN V3.20 ;============================================================================= list p=16f877 ;list directive to define processor #include <p16f877.inc> ;processor specific definitions errorlevel -302 ;suppress "not in bank 0" message CONFIG _CP_OFF & _WDT_OFF & _BODEN_OFF & _PWRTE_ON & _XT_OSC & _WRT_ENABLE_OFF & _LVP_OFF & _DEBUG_OFF & _CPD_OFF ; ;Bit Definitions flag equ 10 adover equ 0 adif equ 1 adgo equ 2 adie equ 6 gie equ 7 rp0 equ 5 ; ; Macros to select the register bank ; Many bank changes can be optimized when only one STATUS bit changes Bank0 MACRO ;macro to select data RAM bank 0 bcf STATUS,RP0 bcf STATUS,RP1 ENDM Bank1 MACRO ;macro to select data RAM bank 1 bsf STATUS,RP0 bcf STATUS,RP1 ENDM Bank2 MACRO ;macro to select data RAM bank 2 bcf STATUS,RP0 bsf STATUS,RP1 ENDM Bank3 MACRO ;macro to select data RAM bank 3 bsf STATUS,RP0 bsf STATUS,RP1 90

3 ENDM ; ;This code executes when a reset occurs. ando equ H'20' dor equ H'21' prod_h equ H'22' prod_l equ H'23' ando_h equ H'24' conta equ H'25' INDICE2 EQU 0X43 INDICE EQU 0X26 dd1 equ 0x27 dd2 equ 0x28 tmp equ 0x29 ddina equ 0x30 m1 equ 0x31 m2 equ 0x32 baja equ 0x33 dda equ 0x34 dd2_ equ 0x35 ddinb equ 0x36 signo equ 0x37 off equ 0x38 regtmp equ 0x39 pwma equ 0x40 ACC0 equ 0x41 ORG 0x0000 ;place code at reset vector pa dd12 dd3 ACC1 equ 0x42 equ 0x43 equ 0x44 equ 0x45 resulthi equ 0x46 resultlo equ 0x47 x equ 0x48 y equ 0x49 res_lo equ 0x50 ResetCode: clrf PCLATH ;select program memory page 0 goto Main ;go to beginning of program ; ;Main routine checks for for reception of a <CR> and ;s a routine to move the data to transmit back. Main: Bank0 clrf PORTA ; Initialize PORTA by clearing output Bank1 movlw 0xCF ; Value used to initialize data direction movwf TRISA ; PORTA<3:0> = inputs PORTA<5:4> = outputs ; TRISA<7:6> always read as '0' Bank0 clrf PORTB ;Initialize PORTB by clearing output data latches clrf PORTA ;Initialize PORTB by clearing output data latches clrf PORTD clrf baja; Bank1 movlw 0xFF; movwf TRISA; clrf TRISB ; PortB as outputs clrf TRISD 91

4 Bank0 initad initpwm LOOP MOVLW.249 MOVWF INDICE selectch1 convert addlw.16 movwf ddina; delayfrec delayfrec delayfrec selectch2 convert addlw.16 movwf ddinb movlw HIGH fasec ;load high 8-bit;address of Table movwf PCLATH ;into PCLATH MOVF INDICE,0 CALL fasec movwf PORTB movlw HIGH faseb ;load high 8-bit;address of Table movwf PCLATH ;into PCLATH MOVF INDICE,0 CALL faseb movwf PORTD movlw HIGH fasea ;load high 8-bit;address of Table movwf PCLATH ;into PCLATH MOVF INDICE,0 CALL fasea movwf dda; ;movwf PORTD movf ddina,0 modula_dd movwf dd1; ;movwf PORTD ;movlw 0x00 movf ddinb,0 modula_dd movwf dd2; movf addwf movwf dd12 ; xorwf dd1,0 ; movwf dd3 dd1,0 dd2,0 match BTFSS PIR1, TMR2IF GOTO match BCF PIR1, TMR2IF MOVF dd1,0; MOVWF CCPR1L MOVF dd12,0; MOVWF CCPR2L DECFSZ INDICE ; YA ES LA ULTIMA GOTO LOOP MOVLW.249 MOVWF INDICE ; APUNTA A LA 1A. MUESTRA 92

5 modula_dd GOTO LOOP clrf signo offset i2; ;para checar la alimentacion de 15 volts movwf movf mul8x8 resultlo dda,0 offset movf resulthi,0 addlw.127 resta sigue_ sublw.255 btfsc signo,0 goto resta goto sigue_ movwf pa; movlw.64 subwf pa,1 movf pa,0 i2; divw3 i2; movwf pa; ; movwf PORTB ;//////////////////////////////////////////////////////////////////////////// complemento2 movwf regtmp; comf regtmp,0; addlw.1 complemento incf signo,1 movwf regtmp; comf regtmp,0; addlw.1 offset movwf off; movlw.127 subwf off,0 btfss STATUS,C complemento initpwm MOVLW MOVWF MOVLW MOVWF MOVWF BSF MOVLW MOVWF BCF T2CON CCP1CON CCP2CON TMR2 0Xff PR2 0Xff CCPR1L CCPR2L INTCON STATUS, RP0 0Xff PR2 TRISC PIE1 STATUS, RP0 PIR1 93

6 MODE MOVLW 0X01C ; Bits 5-4(Least significant) Bits 3-0 =11xx PWM MOVWF CCP1CON MOVWF CCP2CON movlw B' ' khz khz movwf T2CON; ; BSF T2CON, TMR2ON ORG 0X100 fasea ;Prender 4 el TIMER 2 (ultimos LBS bits),,, PR =FF ;00 Prescaler ;01 Prescaler ;1x Prescaler khz ADDWF PCL,1 RETLW 0x7F.. ORG 0X200 fasec ADDWF PCL,1 RETLW 0xC5.. ORG 0X300 faseb ADDWF PCL,1 RETLW 0xEE ; ;Set up serial port and buffers. convert delay ; provide necessary sampling time bsf ADCON0, adgo ; start new A/D conversion loop btfsc ADCON0, adgo ; A/D over? btfsc ADCON0, 2 ; A/D over? goto loop ; no then loop movf ADRESH, W ; yes then get A/D value ;InitializeAD, initializes and sets up the A/D hardware. ;select ch0 to ch3, RC OSC., a/d interrupt. initad Bank1; clrf ADCON1; Bank0; movlw B' ' ;select:rc osc,ch0... movwf ADCON0 ;turn on a/d clrf ADRESH ;clr result reg. selectch1 Bank0; bcf bcf bcf ADCON0,CHS0 ADCON0,CHS1 ADCON0,CHS2 94

7 ;clrf ADRESH selectch2 Bank0; bsf ADCON0,CHS0 bcf ADCON0,CHS1 bcf ADCON0,CHS2 ;clrf ADRESH i2 rlf ACC0, f clrf ACC1 rlf ACC1, f movf ACC0,0 divw3 Bank0 movwf ACC0 movf ACC0, w addwf ACC0, f addwf ACC0, f addwf ACC0, f addwf ACC0, f incf ACC0,1 movf ACC0,0 mul8x8 ;* 2 cycles for - instruction MACRO btfsc STATUS,C addwf resulthi,1 rrf resulthi,1 rrf resultlo,1 ENDM clrf resulthi ;* 1 cycle rrf resultlo,f ;* 1 cycle ; retlw 0 ;* 2 cycles movf resultlo,0 ;This routine is a software delay of 10uS for the a/d setup. ;At 4Mhz clock, the loop takes 3uS, so initialize TEMp with ;a value of 3 to give 9uS, plus the move etc should result in 95

8 ;a total time of > 10uS. delay SD movlw.5 movwf tmp delayfrec SD2 decfsz tmp, F goto SD movlw.200 movwf tmp decfsz tmp, F goto SD2 END 96

; < [PROGRAM] > LIST P=18F452, R=DEC INCLUDE "p18f452.inc"

; < [PROGRAM] > LIST P=18F452, R=DEC INCLUDE p18f452.inc PROGRAM LISTING 7: MPASM EDGE DETECTION PROGRAM By Malcolm Stagg ; ; Edges Controller (EC) ; With Non-Maximal Suppression # ; [Source Code] # ; ---------------------------------- # ; By Malcolm Stagg #