Processor. A Brief Introduction Micron Technology, Inc. March 13, 2014

Transcription

1 Micron Automata Processor A Brief Introduction 2013 Micron Technology, Inc. All rights reserved. Products are warranted only to meet Micron s production data sheet specifications. Information, products, and/or specifications are subject to change without notice. All information is provided on an AS IS basis without warranties of any kind. Dates are estimates only. Drawings are not to scale. Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. March 13, Micron Technology, Inc. 1

2 Breaking the Cycle : The Consistent Message The Response Memory is the bottleneck! We need faster memory! Sure, we can do that! CPU Vendor System OEM Memory Industry 2007: Big Data Problems Begin The Response Memory is the bottleneck! We need faster memory! Why? Let s dig into this a little more CPU Vendor System OEM Micron Technology March 13, Micron Technology, Inc. 2

3 Asking Why? Took Us Back to the Beginning Memory CONTROL ALU IN OUT Reconfiguration of ENIAC Conceptual description of storing machine instructions in system memory The von Neumann Architecture The modern relationship between processor and memory was conceived to avoid complications associated with physical reconfiguration of ENIAC Since the mid 1940 s, most computer systems have been built on this basic architectural concept. The role of memory in systems was firmly cast Micron concluded that important advancements can be made if we challenge this deeply rooted historical concept March 13, Micron Technology, Inc. 3

4 Challenge Everything Can memory be used for purposes other than storage of data and CPU instructions? Is software comprised of sequential Are traditional machine multi-core concepts instructions the the best way to best solution? Is achieve massive this software even parallelism? necessary? Is it conceivable that the Memory Wall is not actually a memory problem at all? What causes the Wall? Can user-designed machines be more powerful than commercially developed CPU s? March 13, Micron Technology, Inc. 4

5 Introduction to Automata Processing The Automata t Processor (AP) is a programmable silicon device capable of performing very high-speed, comprehensive search and analysis of complex, unstructured data streams. Hardware implementation of non-deterministic finite automata (plus some extra features) A scalable two dimensional fabric comprised of ~50,000 simple processing elements per chip, each programmed to perform a pattern matching and activation task each cycle Exploits the very high and natural level of parallelism found in Micron s semiconductor devices Addresses complex computational problems with unprecedented parallelism and performance March 13, Micron Technology, Inc. 5

6 How Does it Work? Enables the FULL capacity of a ROW activation to be used on every memory cycle (~50, bit word size) Each memory element is an independent pattern-matching engine Provides the basis for massively parallel comparison operations and parallel random access memory cycle Implements high speed spatial & temporal pattern matching functionality Allows for complex automata to be implemented in parallel with self-synchronized operation March 13, Micron Technology, Inc. 6

7 Automata Processor Hardware Building Blocks per chip State Transition Element (STE) 49,152 Counter Element 768 Boolean Logic Element 2,304 Nine Programmable Functions Parallel event output virtual pins 6,144

8 Run-length Encoding Pattern-matching based compression technique Sequences (patterns) in which the same data value occurs in many consecutive data elements are stored as a single data value and count Setup a dictionary including all combinations of symbol and count as words When one word matched, report that word How to differentiate a5 and a6? Only report after the consecutive symbols end

9 Run-Length Encoding aabbcccccccccaabb a2b2c4c4c1a2b2

10 Problems Aligned with the Automata Processor Applications requiring deep analysis of data streams containing spatial and temporal information are often impacted by the memory wall and will benefit from the processing efficiency and parallelism of the Automata Processor Network Security: Millions of patterns Real-time results Unstructured data Bioinformatics: Large operands Complex patterns Unstructured data Video Analytics: Highly parallel operation Real-time results Unstructured data Data Analytics: Highly parallel operation Real-time results Unstructured data March 13, Micron Technology, Inc. 10

11 Network Traffic Analytics Network Security Regular Expression signature traffic inspection Service Provider Network Analytics 4-core CPU 2.4GHz* Automata Processor** Performance 192Mbps 1Gbps Power 80W 4W Cost 1x 0.1x Deep packet inspection to *Test benchmark: 534 complex PCRE rules with 35% edge traversal monetize traffic est be c a 53 co p e C u es t 35% edge t a e sa from Snort NIDS. Publication: Evaluating Regular Expression Matching Engines on Network and General Purpose Processors Becchi et al. ** Micron rule set compilation and performance estimate Dr. Michela Becchi, a leading authority on performance analysis of pattern matching engines UoM network security benchmark rule-set compiled on Micron Automata Processor March 13, Micron Technology, Inc. 11

12 Cyber Security Application using PCRE Regular Expressions (REGEX s) are used to concisely specify a set of symbol sequences, aka patterns REGEX s use common operators to define these sets Boolean OR Wildcards Escapes Grouping Assertions Anchors Quantification Modifiers Classes Any digit Infinite Number of Patterns Delimiter 1 or more Alternation Close Group /PICS-version\s+(\d{5,8} \d(\x2e\d){10,})\s*\x29\s+/ Literal Text Open Group Quantification (5 to 8 inclusive) 0 or more August Micron Technology, Inc. 12

13 Patterns A Graphical & Netlist View /PICS-version\s+(\d{5,8} \d(\x2e\d){10,})\s*\x29\s+/ Memory & Switch Programming Instructions s Compiler converts Netlist is created Fully Programmed expression to automata. representing graph Device August Micron Technology, Inc. 13

14 Natural Parallelization of Automatons Pattern #1 Pattern #2 Pattern #3 Parallelization of automatons requires no special consideration by the user. Each automaton operates independently upon the input data stream. March 13, Micron Technology, Inc. 14

15 Bioinformatics Massively parallel l problem space Human genome mapping ~100 base pair reads to 3.2 billion base pair reference genome Comparisons across genomes Professor Srinivas Aluru is leading research on Automata Processors in bioinformatics applications Prosite protein sequence patterns mapped to Micron Automata Processor March 13, Micron Technology, Inc. 15

16 Planted Motif Search Problem Breakthrough Performance Automata Processor UCONN - BECAT Hornet Cluster Processors 48 (PCIe Board)+CPU 48 CPU (Cluster/OpenMPI) Power 245W-315W 1 >2,000W 1 Cost TBD ~$20,000 1 Performance (25,10) minutes minutes Performance (26,11) minutes hours Performance (36,16) minutes 2 Unsolved Planted Motif Search - a leading NP Complete problem in bioinformatics Solutions involving high match lengths and substitution counts are often presented to HPC clusters for processing Independent research predicts the Micron Automata Processor significantly outperforms a multi-core HPC cluster in speed, power and estimated cost 1 Micron Technology Estimates, Not including Memory of 4GB DRAM /Core 2 Research conducted by Georgia Tech (Roy/Aluru) March 13, Micron Technology, Inc. 16

17 Automata Processor Hardware Concurrency Each column represents one STE Each row represents the response of every STE to a specific input symbol All operations for active elements performed concurrently Computes Next State Enable Vector for all state transitions and Match Vector for output on each cycle Each output can be routed to activate other STEs Has deterministic processing performance irrespective of the complexity of the automata Well suited for combinatorial problems Next State Enable Vector Automata Routing Matrix Stream Input Input Decoder R 1 R 2 R 3 R 4 R 5 R 6 R 7 R 8 R n-1 R n Match Vector

18 Automata Processor Multichip Scaling Distributes the input data between all chips within a rank every cycle

19 Automata Processor Multichip Input Concurrency 8 input streams 4 input streams With same number of chips: chose between multiple input stream concurrency or more automata capacity applied to fewer input streams 2 input stream 1 input stream

20 Basic Specifications 1st Silicon has been fabricated in Micron s 300mm manufacturing facility in Manassas, VA First generation device is produced on a trailing edge (50nm) commodity DRAM process Basic Specs: 6.6T path decisions/second 4W Max TPD (estimated) 512 Entry State Vector Cache Inter-chip bus to facilitate scaling DDR3 physical interface < 150 mm2 die size March 13, Micron Technology, Inc. 20

21 Graph Connectivity Check, e.g. Social Networks Check whether two nodes are connected to each other and how their distance from each other Dijkstra s algorithm with Fibonacci heap: O(E + V log V) AP implementation: min(e, V-1) Graph Graph Connection AP Implements Routing Node STE Output Reporting element

22 Graph Connectivity Check Example checks the connection from b node to g node AP Can check many start-destination pairs in parallel b a c d e f h g

23 Automata Processor: Support & Tools PCIe Development Board Industry Standard PCIe bus interface Capacity for up to 48 AP s Large FPGA capacity DDR3 for local storage Software Development Kit AP Optimization, loading & debugging tools Workbench Tool Converts schematic automata to Micron ANML description language March 13, Micron Technology, Inc. 23

24 Automata Processor Development Board PCIe, 6 Ranks, 48 chips, 2.36M STEs

25 Automata Processor Software Integration Compiler Hardware resource optimization Pre-compiled automata macros Automata either PCRE or ANML dev stream 1 stream2 lcg 0 lcg 1 chip chip chip chip chip chip chip chip auto1 lcg 1 auto2 data concurrency chip chip chip chip 0x08 0x04 0x02 0x01 rto1 dynamic automata loading Runtime Manages concurrent, independent d input streams to multiple chips per rank and ranks per device Stops, swaps, and reloads input streams Dynamic loading of compiled automata Dynamic modification of automata characteristics Device Driver Micron Technology, Inc. 25

26 Other Application Experience, Next Steps Have also implemented stack (i.e., memory) and cellular automata Shows that AP is Turing-complete, much more powerful than NFA Encoding/decoding Graph algorithms Bioinformaticsi Frequent-set mining and other combinatorial problems Image feature detection looks promising Treat object features as symbols in an alphabet Treat variations as additional symbols Look for related features as strings Now we can treat this as a regular language g New programming models, languages

27 Goals of the U.Va. Center U.Va. Center for Automata Computing (CAC) founded in Nov. with seed funding from Micron and U.Va. Build critical mass of academic/industry collaborations Provide early access to cluster of Aps Training and programming support Develop foundational, open-source building blocks IP sharing Proposal teaming Clearing house for industry-academic funding

28 In Summary By reconsidering decades old architectural concepts, Micron has fully exploited the inherent parallelism found in memory This parallelism can be harnessed and focused on leading problems across multiple application domains The non-von-neumann design of the Automata Processor delivers the rare trifecta of improved power consumption, performance and cost Micron will lead the industry through continued advancement and development of the AP architecture t U.Va. s CAC will be a nexus for AP research March 13, Micron Technology, Inc. 28