Trends, Challenges, and Solutions in Advanced SoC Wafer Probe

Transcription

1 Design file: MSFT DIFF CLOCK WITH TERMINATORREV2.FFS Designer: Microsoft HyperLynx V8.0 Comment: 650MHz at clk input, J10, fixture attached Time (ps) Date: Wednesday Mar. 3, 2010 Time: 14:16:09 V [U3.1 (at pin)] OSCILLOSCOPE V ol t ag e -mv - Trends, Challenges, and Solutions in Advanced SoC Wafer Probe Mike Slessor, Jarek Kister, Ben Eldridge, Andy McFarland, Chris Gould, Tin Nguyen, and Amy Leong 1

2 Outline/Summary Rapid recent adoption of advanced packaging Copper pillar and C4 flipchip Driven by mobile cost and performance roadmaps Customers relying on more-than-moore advances Presents significant challenges for wafer test and probe Layouts are fully-populated 2-D arrays at sub-100um pitches Contacts are delicate structures made of new and diverse materials Electrical performance (AC&DC) requirements continue to advance Industry requires a Moore-like cost trajectory Solutions rely on a mixture of technologies from diverse areas MEMS processing, materials science, signal integrity, etc. 2

3 Contemporary Packaging Layouts Demand a Vertical Probe Architecture 3 ~80um min pitch (some 4-row designs in 13) Minimal (~250um) corner keepouts Full 2-D Array ~300um pitch Example x2 Card for 80um Copper Pillar Device 3

4 These 2-D Layouts Populated With Structures That Require Low Probe Forces Typical SnAg damage (d) requirement <50% of pillar diameter (D) Additional requirements on probe mark topology (notching, smearing, etc.) Imposed by assembly constraints (reliability) Met with probe forces of 2-3g for 30um < D < 40um 4

5 At Low Force, Probe Material & Geometry Optimization Required for Stable Electrical Contact Bare Copper Pillar MEMS Probe #1 MEMS Probe #2 SnAg Bump Silicon Valley Test Conference Source: Wittig et al, SWTW 2011

6 Overall Cost Also Strongly Influenced by Probe Material and Geometry 4x difference in wear/lifetime for different probes Same (standard HVM) cleaning recipe used 6

7 Dimensional Control Improved With MEMS-Based Fabrication Processes Mechanically Formed MEMS Fabbed Raw as-fabbed distributions Indicative of natural process capability 7

8 For Sub-100um Pitches, MEMS-based Dimensional Control Offers Significant Advantages MEMS Mechanically Formed Reduction in as-produced dimensional errors can be used in different ways: Larger probe for a given design pitch - for 80um example above, D=25um Better electrical performance (current, impedance) and longer lifetime Smaller minimum-viable pitch for a given probe for improved design coverage Higher probe/guideplate component yield for cost reduction 8

9 Composite MEMS Probes Enable Optimization of Mechanical and Electrical Characteristics Different materials, in different locations, doing different jobs Analogous approach to composite design in other fields (eg, aerospace) Fabricated with semiconductor/mems lithography & direct-write technologies Dimensional control ~5x improved over mechanical forming Short cycle time customization 9

10 And On Top of It All, There are More and More of These Probes in Each Card Implications Card will sample tails of probe+guideplate distributions Cpk > 1.33 processes req d Or, cost and leadtime suffer Quality and process control systems become critical Source: Internal MP/FFI MEMS Shipment Data Two primary drivers/causes (roughly equal influences) 1. Increased parallelism more DUTs for test cost reduction 2. Increased probes per DUT more test content and complexity per DUT 10

11 Component Count Increase a Reflection of Complexity-Per-DUT Increase Source: Internal MP/FFI MEMS Shipment Data Implications Increase in PCB complexity design, validation, and fab Simulation and validation tools/processes key to error reduction (leadtime/otd) Deploying PCB assembly+test technologies from other areas Rapid advancement of standard SoC probecard PCB processes Primarily driven by increase in number and performance of critical power supplies Particularly evident in low-power multi-core architectures 11

12 Impedance Performance of Power Supplies Critical to Yield of Low-Power Mobile Devices AC impedance of critical power supplies limiting wafer sort yield Full 3-D simulation of probe-to-tester interconnect standard validation Continued advances in interconnect (MLC/MLO) required Wired space transformers (and low-end MLCs) not viable in these apps 12

13 Summary Trends, Challenges, and Solutions Trends and Challenges are directionally familiar But, these familiar directions are rapidly accelerating 2-D Grid Array pitches below 100um Bump/pad materials and structures demanding <2-3g of probe force Continued improvement in contact stability performance AC impedance reduction of 10x in 3 years Exploding probe (2x in 2 years) and component (4x in 2 years) counts Continuing cost and leadtime reductions Solutions encompass a spectrum of technologies & processes Composite MEMS structures Sophisticated electrical design, validation, and test tools+processes Semiconductor-inspired process control and quality systems 13