ARCHIVE Navid Shahriari Director of Sort Test Technology Development Intel Corporation ABSTRACT

Transcription

1 ARCHIVE 2009 BREAKING TRADITIONAL BOUNDARIES - OUR INDUSTRY CHALLENGES AT TEST by Navid Shahriari Director of Sort Test Technology Development Intel Corporation S ABSTRACT uccess in the semiconductor market is never predictable but it always involves being faster, cheaper or better than your competition. This maxim holds especially true when it comes to microprocessor test. While Moore s Law has spawned a profusion of product features and functions through ever cheaper and abundant transistors, it has left test with increasing complexity and cost. Additionally, market forces necessitate ever-smaller form factors as mobile products become ubiquitous. This combination of shrinking geometry, increasing bandwidth and expanding features creates a confluence of mechanical, electrical and thermal challenges that run head-on into a severely cost constrained environment in the midst of an economic downturn. Meeting these stringent technical challenges while providing cost effective solutions, requires a collaborative response from the whole industry. Customers and suppliers alike. An outlook on the key technology drivers, leadtime, and total test costs, as well as what can be done between the suppliers and customers, to accelerate improvements beyond normal evolution, will be shared with the audience. COPYRIGHT NOTICE The papers in this publication comprise the proceedings of the 2007 BiTS Workshop. They reflect the authors opinions and are reproduced as presented, without change. Their inclusion in this publication does not constitute an endorsement by the BiTS Workshop, the sponsors, BiTS Workshop LLC, or the authors. There is NO copyright protection claimed by this publication or the authors. However, each presentation is the work of the authors and their respective companies: as such, it is strongly suggested that any use reflect proper acknowledgement to the appropriate source. Any questions regarding the use of any materials presented should be directed to the author/s or their companies. All photographs in this archive are copyrighted by BiTS Workshop LLC. The BiTS logo and Burn-in & Test Socket Workshop are trademarks of BiTS Workshop LLC. BiTS Workshop 2009 Archive

2 Breaking Traditional Boundaries OUR Industry Challenges at Test Navid Shahriari Director - Sort/Test Technology Development 2009 BiTS Workshop March 8-11, 2009 Today s presentation contains forward-looking statements. All statements made that are not historical facts are subject to a number of risks and uncertainties, and actual results may differ materially. Please refer to our most recent Earnings Release and our most recent Form 10- Q or 10-K filing for more information on the risk factors that could cause actual results to differ. 3/2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 2 March 8-11,

3 Key Messages Agenda The Environment Test Challenges Test Innovations Required Call To Action 3/2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 3 Key Messages Moore s Law is Alive and Well It all comes together at the test interface Expect the Rate of Change to Accelerate Business, Electrical, Thermal, and Package Handling Cost & Cycle Time Continue to Challenge the Industry We must work together to meet the future needs 3/2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 4 March 8-11,

4 Thank You To The Industry For many years of excellent support. We could not do what we do without you! We have relied heavily on many of you to solve our most pressing test interface challenges 3/2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 5 Together, We Have Created Great Solutions A Couple Of Examples: 3/2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 6 March 8-11,

5 Low Cost Test Topside Contact Package on Package (POP) Top Contacts PoP Package POP Package Bottom Contacts Signal paths Good Solutions Starting to Emerge in the Industry 3/2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 7 Cost Reduction by Increased Parallelism Lower Test Cost per Time 1 Minimum parallelism Relative Cost 0.8 Moderate parallelism Massive parallelism Normalized Test Time Increased Parallelism Drives Lower Test Costs 3/2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 8 March 8-11,

6 The Environment Continues To Get More Complex 3/2009 Breaking Traditional Boundaries OUR Industry Challenges at Test Technology Innovations Continue to Sustain Moore s Law Feature Size (um) 10 9 Transistor Count Price per Transistor ($) More transistors, increased performance, lower cost /2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 10 March 8-11,

7 Growing Complexity In Design Advanced CPU Multiple heterogeneous programmable cores Complex subsystems (e.g., Video, Graphics) High bandwidth/ throughput IOs Multiple comms CPU Core Mem 1 Memory Controller CPU Core Mem 2 ISP/Camera Graphics Video Audio IO blocks Media Display Comms.. New Levels of HW Integration and Complexity 3/2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 11 Packaging Multiplies the Challenges at Test DECREASING Power, Size INCREASING Performance, Power 8mm X 8mm 80mm X 80mm 3/2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 12 March 8-11,

8 Miniaturization drives Z-reduction 1.2 Mobility Thicknesses (inches) Tablet Subnote MID ipod 30G Zune Smart Phone ipod Nano U.S. Nickel Smaller Packaging Required by New Markets 3/2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 13 Cost Pressures Increase Mobile Internet Device Low-cost PC 2008 Avg. Market Price 2012 Avg. Market Price Desktop PC $726 $566 Mobile PC $1,009 $701 Ultra Mobile PC $1,095 $693 Net Books $329 $152 Consumer Electronics Mobile Internet Device Source IDC & ABI Research $335 $135 Future Growth Markets Require Lower Cost Structure 3/2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 14 March 8-11,

9 New Customers, New Expectations Corporate Road Warrior c MHz 10-15W CPU pwr 9.5M transistors 5-6 lbs $1849 Classmate PC, GHz <2W CPU pwr 47M transistors 2.8 lbs $449 3/2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 15 Test Challenges Continue To Multiply Is Industry Innovation Keeping Up? 3/2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 16 March 8-11,

10 I/O Trends High Speed Serial Clock embedded/derived Uni-directional, point-to to-point PCI Express I/O Data Rate (Gbps) Infiniband 2 Serial-ATA 1 FBDIMM GDDR5 PCI Express FBDIMM GDDR4 Serial-ATA GDDR3 PCI Express DDR4 DDR3 DDR DDR /2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 17 I/O Trends High Speed Single-ended ended Source synchronous, becoming more serial-like like (training, etc) Bi-directional, trending toward point-to to-point PCI Express I/O Data Rate (Gbps) Infiniband 2 Serial-ATA 1 FBDIMM GDDR5 PCI Express FBDIMM GDDR4 Serial-ATA GDDR3 PCI Express DDR4 DDR3 DDR DDR /2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 18 March 8-11,

11 Channel Density Continues to Rise Normalized I/O per length I/O Density Density Impacts Substrate Routing 3/2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 19 Pitch continues to shrink Package Pitch Trends Higher Density, Smaller Footprint Means Tighter Pitch 3/2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 20 March 8-11,

12 More Contacts in the Same Footprint Topside Contact Pitch Trends 2 Gbps 5 Gbps 10 Gbps Pitch Topside Contact Drives Test Complexity and Cost 3/2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 21 Power Delivery Sensitive to Socket/Path Impedance Profile Test environment needs to align to end application March 8-11,

13 Test Thermal Challenge Therm al Density Max Power for Bare Die Test 90nm 65nm 45nm 32nm 25nm Technology Node Silicon scaling results in higher thermal density Bare die brings major thermal control challenges Fast transients Spatial uniformity 3/2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 23 Thin package handling Load on Die Load on substrate Keep Out Zone Warpage w/ Load MIN Pin Compression Pin reactant force Force balance = f (warpage) Any Test induced damage is unacceptable MAX Pin Compression Die cracking Package damage 3/2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 24 March 8-11,

14 Bare Die Thermals: Focus on Die-Pedestal Interface Bare Die Pedestal Die Temporary Interface Small effective area Curved Surface Dry interface Relative Interfacial Resistance R_23 R_12 Thermal Water Block 80% of thermal constraint at die-pedestal interface T 3 R 23 T 2 R 12 T 1 TIU Center Corner New Compliant TIM Better Test Thermal Interface Materials are Needed 3/2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 25 We Need To Do Much More Call to Action 3/2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 26 March 8-11,

15 Reduce Complexity Very Few Pre-competitive Standards Each piece of tooling is custom built No Fully Integrated Test Solutions Off-the-Shelf We have to manage many interfaces and suppliers Too Many New Solutions for the same Old Problems 3/2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 27 Cost Reduction Tooling Costs vs. Selling Price Normalized Tooling Cost ? Normalized ASP Tooling Costs must go down in parallel to platform costs 3/2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 28 March 8-11,

16 Need Improvement in Lead-time Typical Test Tooling 1st Article Lead Times Weeks Sort Burn-In Test Package form-factor factor is a competitive advantage Quick-turn test tooling is a differentiator 3/2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 29 You Improve What You Measure 100 Cycle Time Efficiency Performance to Goal W X Y Z Supplier Need to improve cycle times efficiency! 3/2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 30 March 8-11,

17 Engage Early 1-2 Years 1-2 Years 1-2 Years Pathfinding Development Deployment Not Here Start Here Invest in Roadmap Opportunities and Accept the Risks Required to Innovate 3/2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 31 Summary Moore s s Law is alive and well Technical challenges continue to multiply The Rate of Innovation Needs to Increase Need to reduce costs and cycle times We need total solutions instead of many pieces Engage early Develop pre-competitive standards to allow for industry level collaboration 3/2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 32 March 8-11,

18 Risk Factors This presentation contains forward-looking statements that involve a number of risks and uncertainties. These statements do not reflect the potential impact of any mergers, acquisitions, divestitures, investments or other similar transactions that may be completed in the future. The information presented is accurate only as of today s date and will not be updated. In addition to any factors discussed in the presentation, the important factors that could cause actual results to differ materially include the following: Intel operates in intensely competitive industries that are characterized by a high percentage of costs that are fixed or difficult to reduce in the short term, significant pricing pressures, and product demand that is highly variable and difficult to forecast. Revenue and the gross margin percentage are affected by the timing of new Intel product introductions and the demand for and market acceptance of Intel's products; actions taken by Intel's competitors, including product offerings, marketing programs and pricing pressures and Intel s response to such actions; Intel s ability to respond quickly to technological developments and to incorporate new features into its products; and the availability of sufficient components from suppliers to meet demand. Factors that could cause demand to be different from Intel's expectations include customer acceptance of Intel and competitors products; changes in customer order patterns, including order cancellations; changes in the level of inventory at customers; and changes in business and economic conditions. The gross margin percentage could vary significantly from expectations based on changes in revenue levels; product mix and pricing; capacity utilization; variations in inventory valuation; excess or obsolete inventory; manufacturing yields; changes in unit costs; impairments of long-lived assets, including manufacturing, assembly/test and intangible assets; and the timing and execution of the manufacturing ramp and associated costs, including start-up costs. Expenses, particularly certain marketing and compensation expenses, vary depending on the level of demand for Intel's products, the level of revenue and profits and impairments of long-lived assets. Intel is in the midst of a structure and efficiency program which is resulting in several actions that could have an impact on expected expense levels and gross margin. The tax rate expectation is based on current tax law and current expected income. The tax rate may be affected by the closing of acquisitions or divestitures; the jurisdictions in which profits are determined to be earned and taxed; changes in the estimates of credits, benefits and deductions; the resolution of issues arising from tax audits with various tax authorities, including payment of interest and penalties; and the ability to realize deferred tax assets. Gains or losses from equity securities and interest and other could vary from expectations depending on equity market levels and volatility; gains or losses realized on the sale or exchange of securities; gains or losses from equity method investments; impairment charges related to marketable, non-marketable and other investments; interest rates; cash balances; and changes in fair value of derivative instruments. Intel s results could be affected by the amount, type, and valuation of share-based awards granted as well as the amount of awards cancelled due to employee turnover and the timing of award exercises by employees. Intel's results could be impacted by unexpected economic, social, political and physical/infrastructure conditions in the countries in which Intel, its customers or its suppliers operate, including military conflict and other security risks, natural disasters, infrastructure disruptions, health concerns and fluctuations in currency exchange rates. Intel's results could be affected by adverse effects associated with product defects and errata (deviations from published specifications), and by litigation or regulatory matters involving intellectual property, stockholder, consumer, antitrust and other issues, such as the litigation and regulatory matters described in Intel's SEC reports. Please refer to Intel s most recent Earnings Release and most recent Form 10-K or 10-Q filing for more information on the risk factors that could cause actual results to differ materially. 3/2009 Breaking Traditional Boundaries OUR Industry Challenges at Test 33 March 8-11,