Low cost production of monocrystalline equivalent silicon wafers for PV cells

Transcription

1 Low cost production of monocrystalline equivalent silicon wafers for PV cells Alain Straboni, CEO S Tile - Pôle des Éco-industries - 3, rue Raoul Follereau F Poitiers France Ecosummit Düsseldorf November 15, 2012

2 ABOUT S TILE Founded in Highly Experienced Team 4.5 M Seed and A rounds & R&D Grants Proprietary Silicon Tile Technology Silicon film on Sintered silicon wafers : 2 exclusive licenses from CNRS 6 PCT Patents (pending and granted) Located in Poitiers - West of France 11 employees Shareholders Alain Straboni and S tile s key people Emertec Gestion PCI (local venture capital) Poitou-Charentes region

3 BOARD OF DIRECTORS AND SUPERVISORY BOARD Prof. ALAIN STRABONI / CEO and Founder Prof. in material physics. more than 25 years of experience in microelectronics & photovoltaics 80 scientific papers- 25 patents FLORENT DUPONT / R&D Manager ENSMA/EUREC Engineer 3 years in PV industry DR. JEAN-PHILIPPE STEFANINI General Partner Emertec 20 years R&D in aeronautical industry DR. VOLKER HOFFMANN R&D manager at Q-Cells from 2001 to 2009 Consulting expertise in photovoltaics JEAN-BAPTISTE BRETTE / Head of Industrialization ESIM/EUREC Engineer 5 years in automotive industry 3 years solar industry EMMANUEL TURLOT 20 years in photovoltaics and semiconductors CEO at Thompson Multimedia CEO at Unaxis-Nextal

4 SOLAR PHOTOVOLTAIC MARKET Even if Chaotic, total world s installed capacity increased by 13GW in H growing by 35% compared to 2011*, Germany adding 4.4 GW. Photovoltaics : Give me a reason to invest in PV? One : the market s6ll increases. Second : some big players leaving : free places to keep *

5 COST STRUCTURE OF CRYSTALLINE MODULES Silicon wafers 90% of market High efficiency 16-20% Lifetime 25 years BUT Cell 24 % Module 24 % Wafer 52 % Pure Si 24 % Sawing 24 % Ingot 4 % In module cost, wafer is 50% mainly due to materials : Pure silicon and sawing consumables In addition capital costs* for wafering and pure silicon, even in China is 1.5 times greater than in the Cell * Taiwanese polysilicon - Pv Magazine p.80 -Sept 2012

6 STANDARD MONOCRYSTALLINE WAFER WHY USING A SO THICK WAFER as PHOTONS ARE CONVERTED into ELECTRONS IN THE FIRST TENS MICRONS? Sawing less than 150 µm is impossible : too much breakage during sawing and cell fabrication. 200 µm Solution : Peel the mono Wafer and transfer it on a low cost substrate. And 200 µm lost during sawing

7 A NEW CONCEPT OF MONO Equivalent WAFER Our solution : A wafer pressed/ sintered from MG powders with a monocrystalline film on top S Tile Cell No Silicon purification & no sawing = Low production cost And Low Capex Seed layer With Advantages of Silicon of High efficiencies & Lifetime Sintered metallurgical silicon substrate Crystalline pure Si active layer 15 to 25 µm thick

8 THE PROCESS Step 1 Silicon grinding Grinding chunks or direct supply of low cost silicon powder (3 5 / kg) Step 2 Press/Sintering Sintering of silicon bed powder to form a wafer Step 3 Seed Layer Transferring a mono crystalline silicon seed film on top of the sintered substrate Step 4 Epitraxy CVD Step 5 Standard Cell A 25 µm thick mono crystalline layer is deposited by CVD (process developed by Fraunhofer ISE) At this stage, a standard crystalline silicon cell production process can be carried-out

9 A NEW CONCEPT OF PV MONO Equivalent WAFER Reducing Both COST and CAPEX Standard Monocrystalline Wafer S Tile Mono Equivalent Wafer Silicon 11 (Solar Grade) 2,5 (Metal. Grade) Substrate - 5 Wafering / Epi Total Cost (c /W) 26* 15 Total Capex (c /W) 84-93** 46 * Centrotherm Data in Photon Magazine August 2012 ** HSBC Global Research company report (sept 2011) + internal data

10 KERFLESS WAFERING COMPETITORS Technology Leader Advantages Limits/risks Peeling No epitaxy Peeling with metal AstrowaP Simple process, low cost High risk of metal contamina6ons Ion implanta6on Twin Creeks, SiGen High efficiency poten6al Very high Capex : High flux implantor Peeling and epitaxy Film transfered on foreign substrate (glass or plas6cs) Crystal Solar, Solexcell Low cost produc6on, low capex High risk of breakage Non standard Cell/module processes / SiEpitaxial layer on Substrate is recognized as the most promizing market size together with the highest impact on the cost reduction : Lux research report 2012

11 ROUND B FUND RAISING Reinforce the management, Experts to install the pilot line, capacity 15 MW Budget to Finance the line R&D/Pilot design Running Pilot Start new lines k Total cost Total With revenues (40) The phase is financed by 3.5 M of public funds, mainly OSEO, credit tax and 3 FP7 European programs. We look for 2 M increase capital. A second fundraising of 3 M is planned at Q with also a large public support.

12 CONCLUSIONS With the Mono Equivalent wafer disruptive technology S Tile would be able to reduce significantly production and capital costs Thanks to EU and French OSEO subsidies, VC s and industrial investors, this round B will finance a pilot of 15 MW capacity starting its production H Thank you for your attention contact@silicontile.com