Nanium Overview. Company Presentation

Similar documents
System-in-Package (SiP) on Wafer Level, Enabled by Fan-Out WLP (ewlb)

IMPLEMENTATION OF A FULLY MOLDED FAN-OUT PACKAGING TECHNOLOGY

Chips Face-up Panelization Approach For Fan-out Packaging

Wire-Bond CABGA A New Near Die Size Packaging Innovation Yeonho Choi February 1, 2017

Challenges and Solutions for Cost Effective Next Generation Advanced Packaging. H.P. Wirtz, Ph.D. MiNaPAD Conference, Grenoble April 2012

IME Technical Proposal. High Density FOWLP for Mobile Applications. 22 April High Density FOWLP Consortium Forum

Cost effective 300mm Large Scale ewlb (embedded Wafer Level BGA) Technology

3D Package Technologies Review with Gap Analysis for Mobile Application Requirements. Apr 22, 2014 STATS ChipPAC Japan

Innovative Advanced Wafer Level Packaging with Smart Manufacturing Solutions YOON Seung Wook, Ph.D MBA

SEMI Networking Day 2013 Rudolph Corporate Introduction

3D Integrated ewlb /FO-WLP Technology for PoP & SiP

Flexible Carrier Enables Automated Test-in-Tray. Dr. Tom Di Stefano Centipede Systems

Hot Chips: Stacking Tutorial

Semiconductor IC Packaging Technology Challenges: The Next Five Years

System in Package: Identified Technology Needs from the 2004 inemi Roadmap

Board Level Reliability Improvement in ewlb (Embedded Wafer Level BGA) Packages

Close supply chain collaboration enables easy implementation of chip embedded power SiP

Innovative Integration Solutions for SiP Packages Using Fan-Out Wafer Level ewlb Technology

Thin Wafers Bonding & Processing

3D-WLCSP Package Technology: Processing and Reliability Characterization

Thales vision & needs in advanced packaging for high end applications

Chip Packaging for Wearables Choosing the Lowest Cost Package

Forschung für die Elektroniksysteme von morgen

Copyright 2009 Year IEEE. Reprinted from 2009 Electronic Components and Technology Conference. Such permission of the IEEE does not in any way imply

Fan-out Wafer Level ewlb Technology as an Advanced System-in- Package Solution

Failure Modes in Wire bonded and Flip Chip Packages

SEMI MEMS Tech Seminar (Sept 26, Cornaredo, Italy)

Glass Carrier for Fan Out Panel Level Package

RF System in Packages using Integrated Passive Devices

Roundtable 3DIC & TSV: Ready for HVM? European 3D TSV Summit

Bridging Supply Chain Gap for Exempt High-Reliability OEM s

Chapter 3 Silicon Device Fabrication Technology

Challenges for Embedded Device Technologies for Package Level Integration

9 rue Alfred Kastler - BP Nantes Cedex 3 - France Phone : +33 (0) website :

"ewlb Technology: Advanced Semiconductor Packaging Solutions"

Novel Materials and Activities for Next Generation Package. Hitachi Chemical., Co.Ltd. Packaging Solution Center Hiroaki Miyajima

KGC SCIENTIFIC Making of a Chip

Design for Flip-Chip and Chip-Size Package Technology

Panel Discussion: Advanced Packaging

Design and Assembly Process Implementation of 3D Components

YOUR Strategic TESTING ENGINEERING CONCEPT SMT FLIP CHIP PRODUCTION OPTO PACKAGING PROCESS DEVELOPMENT CHIP ON BOARD SUPPLY CHAIN MANAGEMENT

Flip Chip - Integrated In A Standard SMT Process

FRAUNHOFER INSTITUTE FOR RELIABILITY AND MICROINTEGRATION IZM DEPARTMENT WAFER LEVEL SYSTEM INTEGRATION BERLIN

Development of Next-Generation ewlb Packaging

Advanced Analytical Techniques for Semiconductor Assembly Materials and Processes. Jason Chou and Sze Pei Lim Indium Corporation

3D Wirebondless IGBT Module for High Power Applications Dr. Ziyang GAO Jun. 20, 2014

Next Generation ewlb (embedded Wafer Level BGA) Packaging

Ultra Fine Pitch Bumping Using e-ni/au and Sn Lift-Off Processes

Advancements In Packaging Technology Driven By Global Market Return. M. G. Todd

Semiconductor Packaging and Assembly 2002 Review and Outlook

The Packaging and Reliability Qualification of MEMS Resonator Devices

Silicon Wafer Processing PAKAGING AND TEST

FLIP CHIP CHIP ON BOARD SMT ENGINEERING OPTO PACKAGING SUPPLY CHAIN MANAGEMENT TESTING YOUR INNOVATIVE TECHNOLOGY PARTNER PRODUCTION CONCEPT

Package Solutions and Innovations

LED Die Attach Selection Considerations

Forecast of Used Equipment Market Based on Demand & Supply

Fanout Flipchip ewlb (embedded Wafer Level Ball Grid Array) Technology as 2.5D Packaging Solution

Graser User Conference Only

Defining The Future Through Partnerships

Quality Starts With Me

Basic PCB Level Assembly Process Methodology for 3D Package-on-Package

Wafer Level Chip Scale Package (WLCSP)

FABRICATION AND RELIABILITY OF ULTRA-FINE RDL STRUCTURES IN ADVANCED PACKAGING BY EXCIMER LASER ABLATION

3D & 2½D Test Challenges Getting to Known Good Die & Known Good Stack

Die Attach Materials. Die Attach G, TECH. 2U. TECHNICAL R&D DIV.

FOR SEMICONDUCTORS 2007 EDITION

Development of Exposed Die Large Body to Die Size Ratio Wafer Level Package Technology

Recommendation for Handling and Assembly of Infineon Hallsensor PG-SSO Packages

AN Handling and processing of sawn wafers on UV dicing tape. Document information. Sawn wafers, UV dicing tape, handling and processing

New Technology for High-Density LSI Mounting in Consumer Products

IC Integrated Manufacturing Outsourcing Solution

Mobile Device Passive Integration from Wafer Process

APPLICATION NOTE 1891 Understanding the Basics of the Wafer-Level Chip-Scale Package (WL-CSP)

Development of System in Package

Recent Advances in Die Attach Film

Encapsulation Selection, Characterization and Reliability for Fine Pitch BGA (fpbga )

Low Cost Wafer Bumping of GaAs Wafers

EECS130 Integrated Circuit Devices

Innovative Substrate Technologies in the Era of IoTs

ALTERNATIVES TO SOLDER IN INTERCONNECT, PACKAGING, AND ASSEMBLY

EPOXY FLUX MATERIAL AND PROCESS FOR ENHANCING ELECTRICAL INTERCONNECTIONS

Simulation Study on the Warpage Behavior and Board-level Temperature Cycling Reliability of PoP Potentially for High-speed Memory Packaging

Electronic Costing & Technology Experts

A New Company & Approach In MEMS Semiconductor Materials & Engineering Services

Great Team Backend Foundry, Inc. ltd.com

Simulation of Embedded Components in PCB Environment and Verification of Board Reliability

Enabling Technology in Thin Wafer Dicing

Investor presentation 24 April 2013

Effects of Design, Structure and Material on Thermal-Mechanical Reliability of Large Array Wafer Level Packages

NSOP Reduction for QFN RFIC Packages

Power Electronics Packaging Solutions for Device Junction Temperature over 220 o C

EMS Electronic Manufacturing Services Excellence in quality and reliability.

MTS Semiconductor Solution

Recent Trends of Package Warpage and Measurement Metrologies (inemi Warpage Characterization Project Phase 3)

Embedding Passive and Active Components: PCB Design and Fabrication Process Variations

HYPRES. Hypres MCM Process Design Rules 04/12/2016

TSV Interposer Process Flow with IME 300mm Facilities

Nondestructive Internal Inspection. The World s Leading Acoustic Micro Imaging Lab

Copper Wire Packaging Reliability for Automotive and High Voltage

Transcription:

Nanium Overview Company Presentation

Nanium Overview Our name and logo nano prefix of Greek origin referring to small objects ium suffix of Latin origin that includes the formation of scientific terms such as the name of elements The logo suggests a crystalline atomic structure as a unifying symbol of different resources 2

1996-1999 1999-2006 NANIUM s historical background 2006-2009 1996 1999 2006 2010 NANIUM is an independent company in the semiconductor market, providing contract Assembly and Engineering Services for WLP, Packaging, Assembly & Test. Qimonda Portugal s Restructuring Plan was approved on 25th November 2009 with a new and stable shareholder structure: Tex t Tex t Portuguese State 41,06% 17,88% 41,06% Tex t

NANIUM s differentiated value proposition High Quality High Volume / Cost effective manufacturing High Flexibility / Fast prototyping capability Large technology diversity Complete engineering service offer World-class facilities & equipment Big projects start small

A world-class facility in Europe A state-of-the-art facility located in Portugal, near Porto. with > $1B cumulated investment!

NANIUM s overall infrastructure Labs & Engineering 200/300mm WLP & RDL Wafer test Package Assembly Final test Shipping Electrical characterization Material analysis Qualification Reliability Failure analysis Lithography Sputtering Plating Wet Etching Furnace Wafer molding Wafer thinning Ball dropping Probe test Parametric wafer test Laser repair Grinding Dicing Die attach SMT for modules Wire bonding Pick, flip & place Molding Plating Trim & form Marking Singulation Final test Burn-in Modules test Inspection systems Packing (trays, Tape & reel) Preconditioning Shipping A world-class facility for die / wafer / module level assembly, test & packaging Plus associated labs for characterization, reliability & failure analysis

NANIUM s Four Business Offers 1-High volume Packaging, Assembly & Test services 2-High volume 200mm / 300mm WLP & Wafer Test services Lead frame based Laminate based MCP, MCM, stacked dies SiP RDL Fan-in WLP Fan-Out WLP Wafer Test Wafer Thinning Wafer Molding Wafer Bumping Fast prototype and qualification runs Production of small series Innovative package prototypes Flexible technology diversity management Technology transfer Package development Test engineering & development Quality & Supply Chain Management consulting services Laboratories 3-Flexible pilot line for Packaging, Test & SMT 4-Turnkey engineering services Package & Test development, Lab and Consulting

Lead frame based Laminate based MCP, MCM, stacked dies SiP 1 - High volume Packaging, Assembly & Test services

Packaging, Assembly & Test services Lead frames & Laminates Package portfolio include Leadframe-based TSOP, QFP, QFN, SO Laminate-based LGA, BGA Interconnections available Wire-Bonding, Flip-Chip

Packaging, Assembly & Test services Multi Chip Packages (MCP) / Micromodules NANIUM also has extensive volume manufacturing experience of multi-chip memory packages, combining Wafer-level RDL techniques (redistribution) with multiple die stacking in a package. NANIUM s large technology portfolio combined with its strong engineering knowhow and experience enable new innovative MCP/SiP configurations (stacked, sideby-side, MEMS, Sensors, cpv, HB-LED Packages) SiP / MCM Complex MCP Micromodules / Chip on board COB MEMS & Sensor packages

2 - High volume 200mm / 300mm WLP & Wafer Test services RDL Fan-in WLP Fan-Out WLP Wafer Test Wafer Thinning Wafer Molding Wafer Bumping

Sample for a product: New Packaging Technologies Wafer Level Packaging (WLP) 200mm / 300mm Fan-in WLCSP Fan-in WLCSP Technology Features Bare-die handling Full wafer ball-apply Assembly of WLP on DIMM PCB & over-mold (Wafer Level Package on Board) Pitch 0.500-0.800mm Ball size 0.300-0.450 Standard component test & burn-in (FBGA like) Si Chip Si Chip Metal II Photo-IMID RDL-ISOI RDL-metal traces RDL-ISOII Solder ball bond pad WLP WLPoB NANIUM has long time experience in WLCSP development and manufacturing memory applications WLCSP services offer include: RDL / UBM / Balling / Test + other BE steps (such as marking, singulation and tape&reel) 12

New Packaging Technology 300mm Fan-Out WLP (FO-WLP) Reconstitution Re-building of artificial wafer of dies and mold compound Molded artificial wafer is the starting point for thin-film technology Redistribution Using thin-film-technologies for application of dielectric, metal line and solder stop Ball Apply and Singulation Standard BGA-Ball apply Test, Mark, Scan, Pack Standard or wafer level based test flow

First ever 300mm Fan-out WLP realization! (1/2) Based on Infineon s ewlb technology Production line ramping in high volume production by Q3-2010!

First ever 300mm Fan-out WLP realization! (2/2) 300mm Recon-Wafer (chip backside) Overmolded (before backside grinding) 300mm Recon-Wafer (active chip side) Solder Spheres placed Epoxy mold compound Recon-Wafer = Chip Carrier

Fast prototype and qualification runs Production of small series Innovative package prototypes 3 - Flexible pilot line for Packaging, Test & SMT Flexible technology diversity management Technology transfer

Flexible pilot line for Packaging, Test & SMT Modules & Micro-modules NANIUM is set to become a one-stop-shop for module design, qualification and manufacturing across a very wide range of applications as the company is based on A strong experience of volume manufacturing of memory modules A wide internal technology portfolio (including SMT mounting) High engineering skills NANIUM s services include Fast prototype and Qualification runs Production of small series Innovative package prototypes: SiP, MCM, HB-LED, MEMS, sensors, c-pv Technology transfer and Flexible technology diversity management

Flexible pilot line for Packaging, Test & SMT From concept to production ramp-up New package Technologies Fast Prototyping Proof of concept, design validation, customer sampling Qualification runs Electrical characterization, reliability stress tests Packaged IC or module Production of small series Flow enhancement, yield tracking, early failure rate analysis NANIUM has long experience in transferring new package technologies in HVM to third-parties in Asia! Technology transfer To industrial partner

4 - Turnkey engineering services Package / test development, Lab & Consulting Package development Test engineering & development Quality & Supply Chain Management consulting services Laboratories

Turnkey engineering services for Package & Test development, Lab and Consulting Complete semiconductor Business line Marketing IC/system Design Product Engineering Test Engineering Supply Chain Management Quality Engineering Package design Definition of production flow Co-design & thermomechanical modeling Test program development DfM, DfT Yield tracking Electrical characterization Choice and follow-up of contracted partners Production planning Follow-up of production quality and reliability Handling of customer returns Failure analysis Root cause tracking Containment plan Qualification NANIUM s Turnkey engineering services Rely on NANIUM s full engineering services for part or all of your business line engineering tasks and focus on your value adding priorities: marketing and IC / System design!

Thank you for your attention NANIUM S.A. Avenida 1 de Maio 801 4485-629 Vila do Conde Portugal