Narrowing the Gap between Packaging and System Meptec Symposium 2015 ASE (US) Inc Ou Li Nov 10 th, 2015
Outline Industry Dynamics The Need for System Integrators IC/Pkg/System Collaboration Summary 2
Market Trend IOT, Mobile leading the growth. Internet of Everything We are in connected world - Big Data, Cloud in future Diverging Innovation Market, Application, Technology Increasing Competition- Performance, Cost, Time to market 3
Industry Dynamics Vertical Integration Hardware OEM establish IC and supply chain ownership Content and Service provider develop hardware platforms Moore s Law slow down. Fab consolidation on advanced node System company looking for platform Integrators SiP/SiM and heterogeneous Integration for broad applications Opportunities Integration solution being key differentiator OSAT in unique position to realize platform integration Chip- Packaging- System Collaboration Joint Development and Partnership 4
Re-defining the Supply Chain The need for Integrators 5 IC Packaging and Testing SiP/ SiM Development System Integration Package Design IC Substrate Assembly Testing Circuit Design Layout Design BOM Module ASM Module test Wafer Fab Semiconductor ASE Group System OEM Software/Service IC/Pkg/SiP/SiM solution User 5
Chip/Pkg/System collaboration System Architecture Package platform Platform design support Co- Design, Co- Simulation Enabling Packaging Technologies 6
Platform Architecture - MCM or SiP Module MCM SiP Silicon centric, or Package centric module Encapsulation: Exposed die, Selective/irregular mold, Double side mold EMI Shielding: Metal lid, Conformal, Compartment shielding High density SMT, Embedded technology, Antenna on Package Applications: WLAN/WWAN, FEM, BT, PMIC, Transceiver, Mobile TV, etc 7
Platform Architecture 2.5D Thin wafer, double side handling Fine pitch bumping and RDL TSV Technology CoW + Chip Last assembly Multiple test insertion on FT and SLT Large Pkg warpage control 2.5D Si interposer HVM for GPU+HBM GPU: 1.05Ghz, HBM 1.0Ghz, BW 512 GB/S Pkg Size 55x55 mm 2 Interposer: TSV 11um, die size 36x28 mm 2 Microbump pitch: 45 um Interconnect and Packaging solution to enable platform architecture 8
Platform Architecture Wafer level FO Advantage High density, Form Factor Substrate- less Short connections between chip and passive Character and Property Chip first, or Chip last Embedded chip and passives w/ molding compound Fine pitch assembly and SMT process Application Mid- end : BB, RF, PMIC, MEMs High- end : Networking, GPU, APU 9
Chip/Pkg/System collaboration System Architecture Package platform Platform design support Co- Design, Co- Simulation Enabling Packaging Technologies 10
Package Design Conventional Model System PCB IC Design House OSAT -Chip I/O and PCB ball map fixed before pkg design start -Pkg not optimized due to limitation -Pkg may not catch the wafer out schedule -Product Performance suffered 11
Co- Design, Co- Simulation IC Design House -IC/Pkg/PCB early engagement in planning -Layout iterations with SI/PI analysis -Pkg Design Optimized -Schedule in Sync -Product performance met System PCB OSAT Ø Optimized Performance. Cycle time reduction. Ø Cost reduction. Time to market. 12
Design Activities Design EDA Substrate Layout Simulation RLC extraction SI and PI analysis Electrical Characterization Crosstalk/jitter/skew analysis Impedance measurement Eye-diagram measurement Power integrity measurement Thermal and Mechanical Analysis Thermal Simulation and characterization Stress and Warpage simulation and characterization 13
Co-design - IC/PKG/System n Co- works with customer to solve the dynamic DDR power issue and provide the solution ü ü Chip/PKG/System Co- simulation Optimize package design and the decoupling cap on the package C1 DDR Power C2 DDR Package Package on PCB 14
Co-Design IC/PKG/System n Based on impedance file and current profile to optimize PKG decoupling cap, meet customer ±5% spec finally. 2.00 m1 XY Plot 1 Original: P2P = 254mV Dynamic_IR ANSOFT Curve Inf o V(V_die) NexximTransient 1.95 1.90 V(V_die) [V] 1.85 1.80 1.75 m2 1.70 1.65 1.89 1.88 Name X Y m1 86.5687 1.9552 m2 89.9993 1.7003 0.00 100.00 200.00 300.00 400.00 500.00 Time [ns] m1 XY Plot 1 Optimize: P2P = 128mV Dynamic_IR_cap_test Curve Inf o V(V_die) NexximTransient ANSOFT Reduce 50% 1.86 1.84 Original design Optimize design V(V_die) [V] 1.82 1.80 1.78 1.76 1.74 m2 Name X Y m1 73.2424 1.8765 m2 87.9382 1.7481 0.00 100.00 200.00 300.00 400.00 500.00 Time [ns] 15
Co-design IC/PKG/System n n n Package information : FC TFBGA 4L 17x17 mm Application : Tablet DDR3 data rate : 1066 Mbps 4L PKG model PKG- on- PCB full model DRAM1 AP Chip DRAM2 1.70 1.65 P2P = 138mV XY Plot 1 Circuit1 Curve Inf o max min pk2pk V(asic1v5) HSPICETransient 1.5538 1.4157 0.1381 1.60 1.55 V(asic1v5) [V] 1.50 1.45 1.40 1.35 DQ skew + jitter : 112.3 ps DQS jitter : 34.9 ps 1.30 1.25 0.00 25.00 50.00 75.00 100.00 125.00 150.00 175.00 200.00 Time [ns] 16
Co-design IC/PKG/System n n n Cost down version : FC TFBGA 2L 17x17 mm The electrical performance for 2L substrate is similar with using 4L substrate Optimize design on SI and PI 4L PKG model 2L PKG model 17
Simulation to Measurement Correlation WLCSP Diplexer on substrate Insertion loss 18
Package Level High Frequency Measurement - SerDes Bottom Side Top Side Material Property: The S 21 and S DD21 simulation results have good correlation with measurement for both magnitude and phase. 19
System Level High Frequency Measurement - SerDes System measurement environment for package on print circuit board (PCB) sample SDD21 Magnitude Comparison for PKGonPCB A simplified model of signal line on system board with package simulation model has a good prediction. ASE Group. All r ights r eserved. 20
SiP Module Analysis Low Band/high Band channel analysis and optimization for WiFi SiP module on board to meet the electrical specification 21
SiP Module EMI Analysis n Conformal shielding applied on QFN: n WiFi MIMO SiP Module: The higher EMI radiation is on bottom side of pkg by using conformal shielding. Using near field scanner to find the location of main EMI radiation and root cause, then re- design it to meet the specification. ASE Group. All r ights r eserved. 22
Chip/Pkg/System collaboration System Architecture Package platform Platform design support Co- Design, Co- Simulation Characterization Simulation to Measurement Correlation Enabling Packaging Technologies 23
Enabling Technologies for System in Package Shielding - Board or package level - Compartmental Interconnection - Flip chip (MR & TCB) - Wire Bond Antenna - Package integration for 2.4G/5G/60GHz Molding - MUF - Exposed die - Double side SMT - Passives - Components - Connectors Passives / IPD - Integrated Passive Devices Wafer Bumping / WLP - Leadfree / Cu Pillar - Bare die package Embedded Technology - Passive component - Active device Die / Pkg Stacking - Die thinning - Die interconnect Mechanical Assy - Laser welding - Flex bending ASE Confidential 24
Summary IOT, Big data, Cloud computing define our future world System integration and miniaturization continue to grow for performance, power, form factor, cost and time to market Vertical integration from system house for SiP/SiM solution OSAT is in best position as value added Integrators IC/Pkg/System collaboration are key for product success 25
Thank You www.aseglobal.com 26