Temperature-Constrained Power Control for Chip

Transcription

1 Temperature-Constraned Power Control for Chp Multprocessors wth Onlne Model Estmaton Yefu Wang, Ka Ma, Xaoru Wang Department of EECS Unversty of Tennessee, Knoxvlle

2 Introducton o Power and temperature are serous concerns for processors Processors consume a major part of power n computer systems System falure due to overheatng Cost of thermal packagng Increased level l of core ntegraton makes t worse Power control for chp multprocessors Peak power needs to be controlled Temperature must be kept lower than a threshold The performance delvered per watt needs to be maxmzed [Mesa-Martnez 08] Page 2

3 State of the Art Power control for CMP Open-loop search or optmzaton [Isc 06] 06], [Teodorescu 08] 08], etc. Hghly dependent on the accuracy of the system model Heurstcs [Isc 06], [Meng 08], etc. No theoretcal guarantee of control accuracy/stablty Chp-wde DVFS (Dynamc Voltage and Frequency Scalng) [McGowen 06], [Floyd 07], etc. Suboptmal n performance Dynamc thermal management Heurstcs or feedback control theory [Brooks 01], [Skadron 03], etc. Power and temperature are controlled separately Power/temperature management for server systems Server-level [Mnerck 02], [Lefurgy 07], [Skadron 02], [Kephart 07], etc Server-rack-level [Kusc 16], [Wang 08], [Ranganathan 08], [Femal 05], etc Datacenter-level [Wang 09], [Fan 07], etc. Page 3

4 Our Soluton o Actuator: per-core DVFS Manage power and temperature together wth performance optmzaton Power shftng among cores Core varaton and heterogenety should be utlzed to optmze processor performance Control-theoretc theoretc desgn Mult-Input-Mult-Output (MIMO) control To decde the DVFS levels of multple cores Model predctve control (MPC) theory Well-establshed MIMO control theory wth constrant Theoretcal guaranteed control performance and stablty Onlne model estmaton and correcton Emprcal results on hardware testbed Page 4

5 Temperature-Constraned e a ed Power Control o Loop MIMO control loop nvoked perodcally Power montor sends the chp-level power consumpton to the controller Controller reads temperature and performance metrcs of each core Controller computes new DVFS levels based on MPC control theory New per-core DVFS levels are sent to the cores Onlne model estmator updates the power model Page 5

6 Steps of Model Predctve e Control o 1. System modelng Power model 2. Modelng the constrants Temperature constrant Physcal frequency constrant Power budget 3. Controller desgn and analyss Problem formulaton and soluton Stablty analyss Page 6

7 Power Model Core level [Lefurgy 07] 07], [Raghavendra 08] p ( k) = a f ( k) + c p ( k + 1) = p ( k) + a Δf ( k) Chp level cp( k + 1) = cp( k) + [ a K a ] 1 N Δ f1(k ) M Δ f k N ( ) Total Power Frequency Vector Model estmaton and valdaton System dentfcaton Whte nose nput P ower (W) Measured Model Tme (s) Page 7

8 Temperature e Model and Constrant t From power to temperature [Han 07], [Brooks 07] t(k + 1) = AT t(k) + B T p(k) From frequency to temperature p ( k) = a f ( k) + c Δt(k) = ATΔt(k 1) + BΔf ( k 1) Model estmaton and valdaton Whte nose nput System dentfcaton Temperature constrant t < T f (k + 1) < max B Ch hange n Tempe erature ( C) s ) Measured Model Tme (s) Constants Page 8

9 Model Predctve e Controller o Desgn Control objectve: mnmze the cost functon Model predcton Reference trajectory V ( k) = P = 1 cp( k + k) ref ( k + k) 2 M 1 Q( ) + = 0 Δf(k + k) + f(k + k) F max 2 R() Control Accuracy Performance Optmzaton Constrants: F mn, j f cp( k) P j s ( k + 1) Fmax, B f(k + 1) < s f ( k + 1) = f ( k + 1) j j Physcal frequency Power budget Overheatng protecton Other desgn requrements Page 9

10 Model Varaton Actual system model changes sgnfcantly at runtme Unpredctable workload affects power behavor Controller can be used on a dfferent CMP Stablty range System s proven to be stable when the system model changes n a wde range Inaccurate model leads to degraded performance Overshoot Long settlng tme Use a standard recursve least square (RLS) estmator to correct the model perodcally Page 10

11 System Implementaton e Testbed CPU: Xeon X5365 Power montor [Isc 03], [Wu 06] Power lnes (Current sgnal) Current probe (1mv/A) Temperature sensor: coretemp drver Smulaton envronment USB nterface CPU smulator: SESC wth per-core DVFS support Power smulator: Wattch Workload: SPEC CPU 2006 Core frequency modulator 4 dscrete freq levels to approxmate a fractonal level? For 2.89GHz, use 2.67, 3, 3, 2.67, 3, 3 on a smaller tmescale (subntervals) Page 11

12 Accurate Power Control o Budget Change Power(W) MPC St Setpont t 0 60 Tme (s) MPC can precsely control the power of the CMP, wth a standard devaton smaller than 1 W Page 12

13 Better Applcaton Performance Predcton-based Predct the power/performance of every DVFS combnaton based on an offlne analyss. Select DVFS levels wth the best performance under the power constrant Ad Hoc: tral and error Power > budget: select a core and decrease ts DVFS level by 1 Power < budget: select a core and ncrease ts DVFS level by 1 More accurate power control and better applcaton performance Confrmed by smulaton results wth 4, 8 and 16 cores (More results avalable n paper) Page 13

14 Temperature e Constrant t Emulate a thermal emergency by lowerng the temperature constrant Temperatures are quckly constraned to stay below the desred value Power consumpton reduced for temperature reducton perature (ºC) Tem Core 1 Core Tme (s) Powe er (W) Power Setpont 0 60 Tme (s) Page 14

15 Concluson cuso A temperature-constraned chp-level power controller Desgned based on MPC control theory Accurately controls power consumpton Temperatures of the cores are lmted to stay below the constrant. An onlne model estmator perodcally updates the system model Compared wth state-of-the-art work More accurate power control Better applcaton performance Page 15

16 Acknowledgement e Ths work was supported by NSF CAREER Award CNS NSF CSR Grant CNS Power-Aware Computng Award, Mcrosoft Research Offce of Naval Research (N ) Page 16