Computer UCSC. The MASC Group

Transcription

1 Computer UCSC The MASC Group Department of Computer Engineering, University of California Santa Cruz

2 MASC Projects 2

3 MASC Projects 3

4 MASC Projects 4

5 Thermal Measurements & Simulations

6 Measurements Thermal Measurements Performance not the only first order design parameter Energy consumption & thermal issues Power & Temperature must be measured 6

7 Measurements Thermal Measurements AMD 2.2GHz running matrix multiply 7

8 Measurements Our Experimental Setup 8

9 Thermal Infrastructure Applications Extract power maps from a given thermal profile ISCA 07: Power Model Validation Through Thermal Measurements, Francisco J. Mesa-Martinez, Joseph Nayfach-Battilan, and, International Symposium on Computer Architecture (ISCA), June Validate thermal modeling infrastructure ISLPED 09: SOI, Interconnect, Package, and Mainboard Thermal Characterization, Joseph NayfachBattilana and, International Symposium on Low Power Electronics and Design (ISLPED), August 2009 Characterizing processor thermal behavior ASPLOS 10: Characterizing Processor Thermal Behavior, Francisco J. Mesa-Martinez, Ehsan Ardestani, and, Fifteenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March Locate hot spots and thermal sensor insights NVIDIA and Sun collaboration 9

10 Measurements NVIDIA G92 Hotspot Characterization

11 Simulations Full Simulation for Multicores 11

12 Complexity Models & Architectural Solutions

13 Design Time Simulation Architectural proposal characteristics Design workflow Engineers 13

14 Small Processor Example 4 Engineers Single Engineer ISQED 11: A Design Time Simulator for Computer Architects, Sangeetha Sudhakrishnan, Francisco J. Mesa-Martinez, and, IEEE International Symposium on Quality Electronic Design (ISQED), March

15 What if we have a Bug Tolerant Processor? 15

16 MURN Project Multi-University Research Network

17 MURN: Sharing Academic Tape-outs NURN Shares: IO, Network, PLL, jtag interface... Common synthesis flow (28nm Catalyst) Common test and bring up infrastructure 17

18 MURN: Shared Die Resources Project led by UCSC (blue boxes) 18

19 st 1 Tape-out 3Q11: 28nm First MURN project Shared infrastructure Ring interconnect network Blocks from UCSC and UCSD Catalyst (28nm GFI) synthesis flow UCSC (Prof. ) 8 simple core 1GHz FPU 2GHz Several basic SCOORE 2GHz UCSD (Prof. Michael Taylor) Android MIPS based multicore C-Cores (Energy efficiency) 19

20 nd 2 Tape-out nd Late 2012 or early 2013: 2 28nm (or 22nm) tape-out UCSC (Prof. and Prof. Matthew Guthaus) SCOORE CMP High speed clocking UCSD (Prof. Michael Taylor) C-Cores android Hardvard (Prof. David Brooks and Prof. Gu-Yeon Wei) Power and gating blocks Cornell (Prof. Christopher Batten) Scalable CMP networks 20

21 Santa Cruz Out-of-Order RISC Engine

22 SCOORE: Main Parameters 12-stage pipeline 4-way superscalar Out-of-Order (256-entry ROB) Memory speculation, load-hit speculation Performance targets: Over 28nm ~1mm2 As complex as top of the line industry cores IBM Power7, Intel i7, AMD K

23 Early Technology Adoption Motivation Early technology adoption is challenging. It can result in low yield Sources of low yield Timing, power, stuck-at faults, catastrophic... Proposal Novel architectures to improve or tolerate low yield 23

24 Yield Improvement Techniques Tandem-like architecture Retry Allow any pipeline stage to change the number of cycles at runtime Redirection and partial power gating Allow to disable defective resources Leverage redundant structures available in processors... 24

25 Other Projects Research: Power Saving Clock and power gating techniques to reduce design overhead Research: Variability Add techniques to tolerate process variability Research: Compilers Simplify parallel programing semantics (no preemption) 25

26 Current Students 26

27 MASC Summary Large computer architecture group 11 PhD and 8 MS students I have interesting open MS thesis, contact me if looking for a topic Several topics in computer architecture with a focus on Power/Thermal Measure, simulate, improve Complexity Design, programing language, tolerate bugs... MURN tape-out a 28nm 27

28 Questions? Department of Computer Architecture University of California Santa Cruz

29 Team Size Impact Increasing time size Decreases design time (not linear) Reduces unpredictability 29

30 Team Size Impact Adding a person late to the project may not be good 30

31 Further Insights with Simulator Simulation follows existing software models 31

32 Complex System Results Sample result for Sun Niagara II processor 40 engineers over 18 months (360 days) 32

33 Sample Utilization Estimate design time for an issue logic proposal SEED [Martinez et al PACT06] Original paper Frequency, area, and power improvements Replaced the Illinois Verilog Model (EV6-like) for SEED 8% total design time increase or 1.5 additional months 33

34 SCOORE Overview Santa Cruz Out-of-Order pipeline 34