Key Electronic Products Driving Notable DFT Methodologies

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1 Key Electronic Products Driving Notable DFT Methodologies May 2016 Kurian Varghese DFT Applications Engineer

1 (JTAG), circa 1990 Provided standard access to test capabilities

2 Key Test Technology Milestones Provided Universal Benefits Scan Design, circa 1980 Enabled broad use of structural test IEEE (JTAG), circa 1990 Provided standard access to test capabilities ATPG Compression, circa 2000 Kept test costs in line with overall product costs 2

solutions to maximize effectiveness Two notable

3 Need for Targeted Test Strategies Growing design complexities driving need for specialized test solutions to maximize effectiveness Two notable segments needing attention: 3 Automotive ICs Giga-gate Designs

4 Automotive ICs Test Challenges and Unique Solutions 4

5 A New Automotive Era Coming Years Technology and electronics explosion 20 th Century Incremental Mechanical Improvements 5

6 Fastest Growing Market Segment Automotive Comm Ind/Med All ICs Computer Consumer IC Market Growth by Application ( CAGR) 0% 2% 4% 6% 8% Source: IC Insights 6

7 Automotive IC Suppliers Increasingly Diverse Field 13.2% Others 46.8% 8.9% 9.6% 11.5% 10.0% Many new players beyond traditional automotive suppliers Source: IC Insights data for

8 What s the Impact to Semiconductors? Devices must meet quality, reliability & safety requirements Driven by standards like ISO & AEC 100 Key requirements Zero DPM In-field Self-Test Field return analysis 8

9 Tessent Solutions for Automotive Zero DPM In-Field Self-Test Field Return Analysis 9

10 Tessent Solutions for Automotive Zero DPM In-Field Self-Test Field Return Analysis 10

Cell-Aware ATPG Traditional ATPG uses fault models that do not target defects inside each cell Cell-aware ATPG improves detection of defects internal to standard cells Electrical defects mapped to

11 Cell-Aware ATPG Traditional ATPG uses fault models that do not target defects inside each cell Cell-aware ATPG improves detection of defects internal to standard cells Electrical defects mapped to cell-level transistor models Spice simulation maps fault effects to Cell-Aware fault model ATPG engine targets Cell-Aware faults Spice Simulation D0 D1 ATPG logical view Z D2 S 0 S 1 D 0 D 1 D 2 Z S0 S x x x x 1 x 1 x x 0 0 x 1 x x x 0 x x 1 x 1 CA Model 11

Cell-Aware Results Customer Technology Wafer / Package Test

fallout 114 DPPM Over 50 Million parts tested 32nm 880 DPPM

fallout Over 20 companies 350 nm down to less than 28nm Over

12 Cell-Aware Results Customer Technology Wafer / Package Test 350 nm 32 nm 28 nm 1 Million parts tested Additional test fallout 114 DPPM Over 50 Million parts tested 32nm 880 DPPM 28nm 1500 DPPM 130 nm 4 Million parts tested Unique CAT test fallout Over 20 companies 350 nm down to less than 28nm Over 100 Million parts tested with high additional test fallout 12

13 Customer Activity Won Bob Madge Innovation Award at last year s ITC Close to a dozen customers already using this technology Over a dozen published joint papers with customers International Test Conference DATE conference European Test Symposium Asian Test Symposium ISTFA Conference Transactions of CAD Cell-aware Experiences in a High-Quality Automotive Test Suite M.Beck 1, F.Hapke 2, R.Arnold 1 M.Baby 1, S.Straehle 1, J.F.Goncalves 1, A.Panait 1, R.Behr 1, G.Maugard 1, A.Prashanthi 1, J.Schloeffel 2, W.Redemund 2, A.Glowatz 2, A.Fast 2, J.Rajski 2 1 Cell-aware Production Test Results from a 350nm Automotive Design Friedrich Hapke 1, Marek Hustava 2 Juergen Schloeffel 1, Vilem Bucek 2, Wilfried Redemund 1, Pieterjan Vyncke 2, Anja Fast 1, Radek Pospisil 2, Janusz Rajski

14 Tessent Solutions for Automotive Very low DPM In-Field Self-Test Field Return Analysis 14

15 Logic Test Solution Targeting Safety Critical Applications Manufacturing In-System High quality (0 DPM) test Power-on self-test 15

16 Hybrid TK/LBIST Integrated ATPG compression and LBIST (both IP and flow) Enables maximum optimization of defect coverage vs. test time Addresses both manufacturing and in-system test needs 16

Power-On Self-Test POST key for addressing ISO 26262 requirements

memory Data for the BIST registers provided via the IJTAG network

17 Power-On Self-Test POST key for addressing ISO requirements Programmable POST solution P2S conversion of instructions/data from memory Data for the BIST registers provided via the IJTAG network Complete flexibility on how the BIST controllers are run during POST session 17

high-quality solution for both production test and Power- On

18 Customer Feedback Over 20 customers already using this solution The combination of compressed scan test and logic BIST gives Renesas a high-quality solution for both production test and Power- On Self-Test, which is required by the ISO standard in the automotive industry, 18

19 Tessent Solutions for Automotive Very low DPM In-Field Self-Test Field Return Analysis 19

20 Layout-Aware Diagnosis: Improves Resolution and Accuracy Logic diagnosis Layout-aware diagnosis The search area is reduced to 11% or less of the original area Y.-J. Chang, et.al. (MGC, UMC, AMD), Experiences with Layout-Aware Diagnosis, EDFA Magazine, May 2010 This directly results in more die becoming suitable for PFA M. Sharma, et.al. (MGC, TSMC, AMD), Layoutaware Diagnosis Leads to Efficient and Effective Physical Failure Analysis, ISTFA

Cell-Aware Diagnosis: Transistor Level Diagnosis

Works for all pattern types Leverages cell-aware

excitation conditions Data collection and diagnosis

21 Cell-Aware Diagnosis: Transistor Level Diagnosis Improve resolution to defect locations inside cells Works for all pattern types Leverages cell-aware fault model Internal defects mapped to input excitation conditions Data collection and diagnosis flow identical to traditional layout-aware diagnosis ITC 2012 ATS

Customer Feedback Several automotive customers using these solutions

analysis features of Tessent YieldInsight we are able to identify

FA success rate Tool helped identify exact location of failure on

22 Customer Feedback Several automotive customers using these solutions 85% reduction in root cause cycle time Using the statistical analysis features of Tessent YieldInsight we are able to identify yield issues in days as well as determining the impact of process modifications. Davide Appello, STMicroelectronics ST, ISTFA 2011 From 10% to ~100% FA success rate Tool helped identify exact location of failure on layout and coordinates for debugging PFA candidates. Close to 100% success on PFA. Avadh Tibrawal, Cypress Semiconductor Cypress, U2U

23 Giga-Gate Designs Test Challenges and Unique Solutions 23

24 Unique Challenges for Giga-gate Designs ATPG run time Multiple weeks to months not uncommon for large designs Often in critical path to tapeout Memory footprint Very large memory footprint limits machine availability Test pattern volume Directly impacts test (and product) cost 24

25 Tessent Solutions for Giga-Gate Designs ATPG run time Hierarchical ATPG TestKompress & EDT Test Points ATPG memory footprint Test pattern volume 25

first generated for each design core in isolation.

26 Hierarchical ATPG Divide-and-conquer approach to break down the overall ATPG task into smaller, more manageable pieces Patterns are first generated for each design core in isolation. Patterns are then automatically retargeted to the chip level and merged to minimize test time 26

27 Hierarchical ATPG Main Benefits Significant reduction in run times Significant reduction in compute resources Reduction in pattern volume Allows block-level ATPG early in flow Takes ATPG out of critical path 27

28 Hierarchical ATPG Typical Customer Results 5X+ reduction in ATPG runtime >5X reduction in CPU memory required Saved 100 s of hours in gate-level simulation 50% reduction in pattern count 28

General business information TM Customer Feedback Over 15

Mentor s Tessent hierarchical ATPG flow has allowed us to

Because this solution is highly scalable, we expect to

Engineering, Mellanox Technologies Hierarchical DFT

29 General business information TM Customer Feedback Over 15 customers already using hierarchical ATPG solution Moving to Mentor s Tessent hierarchical ATPG flow has allowed us to significantly reduce turnaround time on current designs. Because this solution is highly scalable, we expect to continue using it on our future designs Evelyn Landman, VP Engineering, Mellanox Technologies Hierarchical DFT Implementation at Freescale Israel Shlomi Sde-Paz Freescale Israel J a n

30 TestKompress & EDT Test Points Improving Test Compression Unlike traditional test points that target test coverage improvements, EDT Test Points target compression 30

31 Impact of EDT Test Points Average 2-4X improvement in compression On top of the average TestKompress base compression of 85X 31

Customer Feedback Over a dozen customers already using EDT Test Points

was approved for use on all production devices in our design center With

32 Customer Feedback Over a dozen customers already using EDT Test Points We ve not seen a block that doesn t benefit in terms of pattern count reduction from EDT Test Points. 32 EDT Test Points results were presented to our CTO and the technology was approved for use on all production devices in our design center With the 4X reduction we re seeing from EDT Test Points, we don t see any issues with data volume for the next 5-6 years.

33 Summary Increasing design complexities require targeted test solutions for maximum effectiveness Automotive ICs require very high quality and reliability driven by ISO standard Giga-gate designs pushing limits of ATPG runtime and memory usage Tessent provides unique solutions to address these new challenges 33

34 THANK YOU!

Kun Young Chung Design Technology Team System LSI Samsung Electronics

2012 Test Technology Workshop (Oct. 31, 2012) IDC-System LSI Business 0 Kun Young Chung Design Technology Team System LSI Samsung Electronics An Overview: Test Challenges in 3D ICs Design (Design-for-Test)