Making Sense of Thermoelectrics for Processor Thermal Management and Energy Harvesting

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1 Making Sense of Thermoelectrics for Processor Thermal Management and Energy Harvesting Sriram Jayakumar School of Engineering Brown University Providence, RI 91 sriram Sherief Reda School of Engineering Brown University Providence, RI 91 sherief Abstract A thermoelectric (TE) device can be used as a heat pump that consumes electric power to cool a processor chip, or it can be used as a heat engine that generates electricity from the heat dissipated during processor operation. To better understand the use of TE devices, we develop a fully instrumented processorbased system with controllable TE devices. We first examine the use of TE devices for energy harvesting. We identify a pitfall in previous works that can lead to wrong conclusions for TEG use by demonstrating that TEGs increase the processor s leakage power which offsets their harvested power. For thermoelectric cooling (TEC), we elucidate the intricate relationships between the processor power, thermoelectric power, and fan power. We propose a dynamic thermal management scheme (DTM) that maximizes performance under thermal constraints and given total power budgets by controlling the processor s dynamic frequency and voltage scaling (DVFS), TEC current, and fan speed. For the evaluated thermal constraints, our results demonstrate good improvements to performance at the cost of additional cooling power compared to standard DVFS+fan DTM techniques. I. INTRODUCTION The performance of most modern processors is thermally constrained, where the frequency and voltage of operation are controlled to prevent high temperatures that can compromise reliability. Modern processors make use of turbo modes, where a dynamic thermal management (DTM) system boosts the frequency of operation based on the available thermal slack. In addition to thermal constraints, it is also important for computing systems to operate within a power budget to minimize energy consumption and to prolong operational time especially for battery-operated systems. Thermoelectric (TE) devices are made of an array of p-type and n-type semiconductor, e.g., bismuth-tellurides, thermocouples that are connected electrically in series but thermally in parallel. In processor-based systems, the TE device is usually inserted between the processor and the heat sink. TE devices can operate as thermoelectric coolers (TECs) by pumping heat from the chip side to the heat sink side, where the amount of heat pumping is linearly proportional to the TEC s electric current. The TEC electrical current leads to Joule heating which must be dissipated by the heat sink as well. A TE device can be also used as a thermoelectric generator (TEG), where it generates electricity from the heat dissipated during chip operation. In this case the TEG uses the natural thermal gradient across it from the hot chip to the colder sink to generate voltage that is proportional to the gradient. TE devices provide an exciting opportunity for computing systems as they can enable higher performance levels through improved cooling and/or they can be used as electrical generators by harvesting the heat waste of computer chips. In this paper we create a real system that uses a TE device with a nm quad-core processor to elucidate the intricacies of using TE devices with processors. The contributions of this paper are as follows. We examine the use of TEGs in a processor context. We analyze the thermal impact of using TEGs to extract energy and its ramifications on the leakage power of the processor. Compared to a standard setup which does not use TEGs, we demonstrate an increase in leakage power when TEGs are used, and as a result we conclude that previous studies overestimated the benefits of TEGs because the harvested power is offset by an increase in leakage power. To demonstrate TE potential as a TEC, we first characterize our system under a wide range of settings for dynamic voltage and frequency scaling (DVFS), fan speed and TEC current, and elucidate the intricate relationships between the processor power, thermoelectric power, and fan power. Based on these relationships, we devise a DTM algorithm that maximizes performance subject to thermal constraints for a given total (computing and cooling) power budget. Our algorithm controls DVFS, fan speed and TEC current to achieve its aims. We implement our methods on a real system based on a nm Ivy Bridge Intel Core i5 processor (CPU) equipped with a TE device and a traditional fan. The system is fully instrumented to monitor the CPU power consumption and internal thermal sensors, and to control the TEC s supply current and the fan speed. All measurements are collected on the system itself providing an ideal testbed for DTM algorithms. Given a thermal constraint, our experiments demonstrate an average 19.6% performance increase with an additional 9.15 W of TEC cooling compared to standard DVFS+fan DTM techniques across a number of benchmarks. The organization of this paper is as follows. In section II we provide an overview of the relevant work in the literature. Section III elaborates our setup that is used for our analyses and experiments. In section IV we analyze the use of TE devices for energy harvesting, and in Section V we analyze their use for cooling and we propose a new DTM method. In Section VI, we summarize the main conclusions of this work.

2 II. III. BACKGROUND Cooling Processors. To analyze the impact of TEC cooling on processors, Koester et al. examined the use of TECs to cool hot spots of processors as a function of TEC current [11]. Chowdhury et al. demonstrated the first use of a high figure-ofmerit superlattice TEC on cooling a processor [5]. Compared to bulk TE devices, superlattice or thin-film TECs achieve a higher figure of merit by increasing the electrical conductivity and reducing the thermal conductivity through nano structuring fabrication methods. Chaparro et al. evaluated the prospect of thin-film TECs for dynamic thermal management in a simulation environment, where the DVFS of a core is increased to leverage the thermal slack that is created when a TEC is enabled [3]. Alexandrov et al. provided compact models for thin-film TECs and use the models to simulate the transient time required to establish steady-state temperatures [], while Sullivan et al. analyzed the use of multiple TECs to cool multiple hot spots [1]. Paterna and Reda investigated the use of per-core thin-film TECs to mitigate dark silicon problems in multi-core processors [8]. Dousti and Pedram formulated the problem of identifying the TEC current and fan speed to minimize the total power subject to a thermal constraint [6], [7]. The model formulation of the problem is based on design information, and then the formulation is solved using activeset sequential quadratic programming and results are verified in simulation. Energy Harvesting. A number of works examine the use of TE devices as TEGs in processor-based systems [1], [13], [4]. Using simulations and models, Choday et al. evaluate the energy harvested from a TEG and the cooling achieved by a TEC as a function of the workload running on a processor. Alexandrov el. demonstrates a system in which the TE device is used for energy harvesting when the chip temperature is low, but it is used for cooling when the chip s temperature increases [1]. Wu analyzed the harvested power and the impact of increase in temperature from using the TEG on the processor s reliability [13]. Shortcomings. We observe that previous works have a number of shortcomings. First, many ignore or miscalculate the impact of the additional thermal resistance of the TEG devices, which leads to higher processor temperature than predicted by simulations. None of the previous works considered the impact of this temperature increase on leakage power of the processor. This higher leakage can offset the benefits of TEGs as we will demonstrate in this paper. Second, all thin-film TEC papers use or assume substandard thermal grease for the thermal interface material (TIM) with a thermal conductivity of 1.75 W/mK in the models, and as a result replacing the standard thermal grease by the thinfilm TE device (with effective 17 W/mK thermal conductivity) leads to a smaller thermal resistance (even in passive mode) in comparison to a baseline case without TEC. As a result, the passive cooling effect of thin film TECs may not occur when good TIMs are used. In fact, most modern processors use higher quality TIMs, where silver-based compounds reach a thermal conductivity 8.5 W/mK and Indium-based solders used in high-power processors each 3 5 W/mK [1]. These TIMs are also cheaper than TE devices. S YSTEM S ETUP AND D ESIGN To assess the use of TE devices in computing systems, we put a fully instrumented setup (shown in Figure 1) that consists of following main components. A motherboard which hosts an nm FinFET-based Intel i5-345s Ivy Bridge processor. The processor comes with a standard heat sink and a fan that has a rotational speed that can be controlled from 5 rpm to 6 rpm. The system runs Ubuntu 1.4. To measure the processor s power consumption, we intercept the 1 V DC supply lines to the processor with 1 mv/a shunt resistor, and use Agilent A3441A digital multimeter to measure the electric current to the processor. The measurements are relayed over USB to our system. An additional Agilent A3441A digital multimeter is used to measure the output voltage when the TE device is used in TEG mode. RMT 1MC6-14-3AN5 TE devices. Each device is 6.5 mm 1 mm, with.4 mm thermocouple thickness. We special ordered thin AlN ceramic pads instead of standard Al O3 ceramic pads to reduce the thermal resistance of the pads. The entire device has a thickness of.9 mm. A programmable Tektronix 45 power supply is used to control the current to the TE device in cooling mode. The power supply is connected over USB to the motherboard to enable real-time programming from our DTM system. Throughout the paper we consider two setups for comparison. We consider the baseline system without the TE devices as shown in Figure.a, and in the setup of Figure.b, we consider the TE devices placed between the heat spreader and the heat sink & fan. We use two TE devices that are thermally in parallel but electrically in series, which reduces the passive thermal resistance and the processor s temperature. The two TE devices occupy an area of 6.5 mm 4 mm. IV. M AKING S ENSE OF TEG S FOR E NERGY H ARVESTING Comparing to the baseline system without TE devices, the higher thermal resistance arising from the insertion of the TE device in the heat removal path creates a challenging problem because it increases the temperature and leakage power of the processor. Previous works analyzed the increase in temperature and its impact on reliability [1], [13], [4], but did not analyze the impact on leakage. Analyzing leakage power is the most CPU power monitor CPU, TE device and fan assembly TEC programmable current supply Fig. 1. Setup for studying use of TE devices.

3 heat spreader processor die heat spreader processor die Heat sink & Fan (a) Heat Sink & Fan (b) TECs Fig.. Processor and heat removal assembly with and without TECs. Silverbased TIM (Arctic Silver 5) is used at the interfaces of all objects. important issue because it can offset the benefits of using TEGs for energy harvesting. To assess this possibility, we create a 4-threaded microkernel application with an extremely stable nature. We run this workload on the baseline system at various DVFS settings and record the temperatures from the sensors and power of the processor after reaching steady state. We fixed the fan speed at 6 rpm. We re-do the same runs after inserting the TEG into the system, and again record the processor power, the temperature sensors, and TEG output voltage. The TEG open-circuit output voltage is equal to ns T, where n is the number of thermocouples electrically in series, S is Seebeck coefficient, and T is the thermal gradient across the TEG. The maximum power generation occurs when the the load resistance matches TEG s internal resistance. However, the internal resistance is a function of the TEG s temperature. Thus for every experiment, the TEG output voltage is recorded for the open-circuit case (denoted V 1 ) and under a load R L (denoted V ), and the maximum TEG power is then given by V1 /(4R L (V 1 /V 1)) [9]. This maximum power will be delivered to an external load only when the load s impedance matches the TEC s internal impedance. Our open-circuit voltage ranged from V, and the voltage ranged from.7 V with a 1 Ω load resistor. We plot in Figure 3.a the temperatures of the baseline setup, and the setup where the TEG is connected to a load Power (mw) Temp (C) (a) Temperatures in standard setup vs TEG setup 7 TEG CPU Temp (C) 6 baseline CPU Temp(C) DVFS (GHz) (b) TEG vs leakage power increase TEG harvested (mw) additional leakage (mw) DVFS(GHz) Fig. 3. Impact of TEGs on temperature and leakage power. CPU power (W) y = 6e-5*x *x +.45*x Temperature (C) Fig. 4. Quantifying leakage for evaluated Core i5 processor. as a function of DVFS. The open-circuit TEG exhibits worse results. The plot shows that the inserting the TE device leads to about C increase in temperature. We then plot in Figure 3.b the difference in the processor s power between the TE setup and the baseline setup, and we plot the maximum power harvested from the TEG. The results show that the harvested power by the TEG is offset by a much larger increase in the processor s leakage power. In the plot, the TEG has a peak power generation of in the range mw depending on DVFS, but leakage increase ranges by mw. Thus, there is no net power generation compared to the baseline setup without TEG. TEG power generation is ultimately in conflict with leakage, because the generated voltage is linearly proportional to T, and higher T implies higher temperature for the processor; however, leakage is exponentially dependent on temperature. That is why the gap between power generation and leakage widens with increasing DVFS. Our results demonstrate that previous work ignored the crucial impact of the TEG on the leakage power of the processor. Despite this negative result, future thinner TE devices with higher figure of merit may mitigate this problem by reducing the thermal impact on the processor and increasing the TEG s energy generation. Our results show that it is important to model or measure the processor s leakage power of the processor. We observe that using the TE device in TEC mode and the fan can quantify the entire leakage power profile of the processor as a function of its temperature. We execute our stable microkernel application and fix the DVFS setting at.8 GHz. We then sweep the fan speed (5 6 rpm) and the current of the TEC ( A) and record the average temperature from the thermal sensors and the processor s total power at the steady state for every combination. Figure 4 gives the power of the processor as a function of its average temperature. Note that the changes in the processor s power are attributed entirely to leakage power since the dynamic power is fixed by the stable nature of our application and the fixed voltage setting of DVFS. V. MAKING SENSE OF TECS FOR DTM DVFS and fan speeds have been the main knobs for DTM, where DVFS is typically increased until a thermal constraint is reached, and the fan speed is adjusted depending on the sensed temperatures. In TEC-based systems, a heat sink and a fan are still required to remove the pumped heat from the processor and the TEC s own heat. Our goal is to devise DTM systems that leverage three knobs: DVFS settings, TEC currents and fan speeds. We observe that the presence of TECs can lead to large power consumption for cooling. Given that most computing systems have a power budget, we consider

4 a DTM system that seeks to maximize performance while subject to both a total power budget and a thermal constraint, where the total power budget is the sum of both computing by the processor and cooling by the TEC and fan. We first analyze the effectiveness of the TEC and fan in Subsection V-A, and then analyze the relationship between DVFS and TEC-based cooling in Subsection V-B, which leads to our devised DTM method in Subsection V-C. A. Cooling: TEC and Fan In this subsection our objective is to study the impact of settings for the TEC and the fan on the temperature of the processor and total power. The amount of heat q c that a TEC can pump is controlled by its input current, I, where at steady state q c = ST c I K T 1 I R, (1) where T c is the temperature of the cold side, K is the TEC thermal conductance, T is the thermal gradient across the TEC, and R is the internal electrical resistance of the TEC. The power consumption of the TEC is equal to P tec = S T I + I R. () For the fan, its power consumption, P fan, is equal to P fan ω 3, where ω is its rotational speed. In computer chips, the fan is connected to a 1 V supply line from the motherboard, and the speed is adjusted using pulse width modulation, which lowers the effective voltage of the fan. To study the impact of I and ω, we use our stable 4- threaded microkernel application to activate all cores at the highest DVFS setting. We then apply various combinations of ω and I to the fan and TEC respectively. For each combination, we wait until the steady state and record the average processor temperature from its four sensors, the power consumption of the TEC and the power consumption of the fan. These measurements are averaged over 3 seconds at steady state. From the results, we make the following four key observations. First, increasing the fan speed will always reduce the temperature and leakage of the processor though with diminishing returns trends as shown in Figure 5. However, increasing the TEC current will first lead to a reduction in temperature because of the higher heat pump as given by Equation 1, but later large TEC currents will lead to larger Joule heating for the TEC as given by Equation, which increases the temperature of the heat sink and the processor [5]. This latter increase is not shown in the figure as it requires large amounts of current in excess of A in our setup. Second, we plot in Figure 6 the total system power (i.e., processor, fan and TEC) as a function of TEC current and fan speed. The figure shows that activating the TEC with I =.3 A and the fan with ω = 175 rpm will minimize the total power by 7.5% compared to the setting that minimizes just cooling power (i.e., I = A and ω = 5 rpm). This result is attained from savings in leakage power from the processor despite the TEC and fan joint power consumption. Thus, operating at these settings should be default for DTM, because operating with less TEC current or fan speed will simultaneously increase total power consumption and the processor s temperature. Note that this point will be slightly impacted by the nature of the workload and DVFS. It is also worth Fig. 5. Fig. 6. Temperature (C) TEC current (A) Fan speed (rpm) Die average temperature as a function of fan speed. Total system power (W) TEC current (A) Fan speed (rpm) 5 Total system power as a function of fan speed and TEC current. noting that TECs have much larger operational and power consumption range than fans. Thus, fans are likely to reach their maximum limits much earlier than TECs. For instance, while the fan in our system consumes in the range of 1.75 W depending on its speed, the TEC consumes between 9 W depending on its current and thermal gradient. Third, there is a subtle interaction between the fan speed and the TEC power consumption. For a fixed TEC current, increasing the fan speed reduces the TEC power consumption, because increasing the fan speed reduces the temperature gradient across the TEC, which reduces the TEC s voltage and power consumption as given by Equation. In our results, increasing the fan from 5 rpm to 6 rpm reduced the TEC power consumption by 8 11% depending on the TEC current and CPU power. Fourth, TECs offer much more rapid control of the processor s temperature compared to regular fans because the TEC cold side is in touch directly with the processor and the TEC is a solid-state device with faster reaction time than the fan s mechanical motor. We illustrate the dynamic behavior in Subsection V-C. B. DVFS and Cooling Power Tradeoff Using the same setup as in the previous subsection, we plot the thermal contour plots as a function of the processor DVFS and TEC current (for fixed fan 175 rpm) in Figure 7. The plot gives the trade-off between processor performance as given by DVFS and TEC current to achieve a target temperature. From the figure, we observe that for a fixed frequency, the plots get increasingly spaced as current increases. For instance, at.8 GHz, reducing the temperature by 4 C from 6 C to 58 C requires an additional.175 A, but reducing from 4 C to 38 C requires an additional.3 A. This observation matches up the observation in the previous section which states that increasing TEC current has diminishing returns. Another insight from the contour plot is that for a fixed temperature, as

5 TEC Current (A) Fig DVFS (GHz) 58 Temperature contours as a function of DVFS setting and TEC current. CPU DVFS increases, more and more TEC current is required. The effect is more pronounced at lower temperatures compared to higher temperatures. For instance, increasing the frequency from. GHz to.8 GHz requires an additional of.4 A at the 5 C contour, but requires an additional.5 A at the 38 C contour. The reason for this behavior is that lower temperature thresholds require higher heat pumping by the TEC which necessitates increasing its current. However, the TEC s Joule heating increases as a byproduct as given in Equation, which requires additional amount of current to maintain the same temperature. Thus, maintaining a fixed temperature requires disproportionately more power from the TEC to sustain performance increases. DVFS though delivers faster response than the TEC because it leads to fast (1- µs) reduction in the processor s power. We plot the maximum attained DVFS as a function of the power budget in Figure 8 for two thermal constraints 65 C and 45 C. We also plot in Figure 8.b the breakdown of the power budget among the CPU, TEC and fan as a function of the power budget for the 45 C case. The plots show that lower temperature constraints require higher power budgets to deliver more TEC current for cooling. This is why each of the plots starts at a different point. Consider a fixed temperature constraint: at lower frequencies, increasing the power budget slightly gives larger gains in performance, compared to increasing the power budget by the same amount at a higher frequency. Additionally, for lower temperature constraints, the growth rate of frequency as a function of power budget is lower. Compare the T max = 45 C and T max = 65 C plots: at the lowest power budget available, the 45 C plot starts out growing slower compared to the 6 C plot. The power breakdown also shows that the TEC consuming an expanding portion of the total power that is changing at a higher rate than the CPU portion as the power budget max DVFS (GHz) (a) Impact of power budget on DVFS Fig. 8. T=65 C T=45 C Total power budget (W) Power breakdown (W) (b) Breakdown of power budget 4 cpu (W) tec (W) fan (W) Total power budget (W) Impact of power budget on performance and its breakdown. and performance increase. For instance, at 3 W, the TEC consumes 13% of the total budget, but at 4 W, the TEC consumes 18% of the total power budget. C. Dynamic Thermal Management The goal of DTM is to maximize performance based on a given thermal constraint T max and power budget P max. Based on our analysis in Subsection V-A, our DTM always uses a minimum bound of I min =.3A for the TEC and ω min = 175 rpm for the fan. We limit the maximum value for I is I max = A and the maximum value for ω is ω max = 6 rpm. Our DTM is invoked periodically every 1 second, and at every invocation k, it measures the maximum sensor temperature across all cores, T (k), and the total (TEC, CPU & fan) power consumption P (k). Utilizing the insights from our analysis in Subsection V-A and Subsection V-B, the DTM then sets DVFS, the TEC current and fan speed based on the following cases. case #1: if T (k) < T max and P (k) < P max then increase DVFS if possible else decrease cooling if I > I min or ω > ω min. case #: if T (k) T max and P (k) > P max then decrease cooling if I > I min or ω > ω min else decrease DVFS. case #3: if T (k) > T max and P (k) < P max then increase cooling if I < I max or ω < ω max else decrease DVFS. case #4: if T (k) > T max and P (k) P max then decrease DVFS. Case 1 seeks to boost performance but if the maximum DVFS is reached then it will attempt to decrease cooling to reduce power consumption. In case, the DTM reduces the cooling to meet the power budget, which is reasonable given the availability of thermal slack, but if the the TEC and fan are at their minima, then DTM is forced to reduce DVFS. In case 3, the slack in power budget is used to increase cooling to reduce the thermal violation, but if cooling is at its maximum, then DVFS has to be decreased. The last case is when the thermal and power budget constraints are both violated which triggers a reduction in DVFS. When we change the cooling level, we always prioritize TEC over the fan. We use a P- controller for the adjustment of DVFS, I and ω settings, though a PI controller is also possible. In this first experiment we illustrate our DTM approach in our real system. We launch four instances of the povray benchmark from SPEC CPU6 suite to keep all cores utilized. We show four metrics over time in Figure 9: the maximum sensor temperature, the total power consumption; the TEC I setting, and the DVFS setting. For space considerations, we skip the fan which operates between rpm. At the beginning we set a thermal threshold of 5 C and a 4 W power budget, thus, DVFS increases while the TEC and fan are engaged to bring the temperature below the threshold. After 1 minute, we impose a power budget of 3 W. As a result the TEC current has to be scaled back which forces DVFS to decrease to avoid violating the thermal constraint. After minutes, we relax the thermal constraint to 65 C, which enables TEC current to decrease creating room for DVFS to increase within the same budget, and finally after 3 minutes, we increase the power budget to 4 W, which enables further improvements to DVFS with no need to engage the TEC. The

6 temp (C) total power (W) TEC I (A) DVFS (GHz) Tmax=55 Pmax=4 Tmax=55 Pmax=3 Tmax=65 Pmax=3 Tmax=65 Pmax= Fig. 9. DTM under various maximum temperature and power budgets for povray from SPEC CPU6. traces show that our DTM controller is effectively able to maximize DVFS subject to time-varying thermal constraints and power budgets. In the second experiment we apply our method on five SPEC6 CPU benchmarks: astar, bzip, calculix, gcc and tonto. We select these benchmarks because they display the most interesting variations in power and temperature during execution. We consider a DTM scenario with T max = 45 C and P max = 45 W. We compare the setup where the TEC is used (e.g., Figure.b) and the case where the TEC is not inserted (e.g., Figure.a). For the latter setup, we consider a similar DTM method, where we only use DVFS and the fan. We report in Table I the average DVFS setting throughout execution, the percentage of runtime where the benchmark had thermal violations, and the average cooling power as measured by sum of the TEC power and fan power for the TEC setup and just fan power for the no-tec setup. Our results show that using the TEC-based DTM boosts DVFS on average by 19.6% with an additional 9.15 W on average for cooling. Thus, TECbased cooling alleviates the thermal constraints on computing, which enable DVFS to increase; however, this performance benefit comes at increased cooling power consumption. VI. CONCLUSIONS In this paper we studied the effectiveness of using thermoelectric devices for both energy harvesting and dynamic thermal management in processors. We first analyzed their use as TEGs and concluded that TEGs increase the processor s temperature and leakage power, and that the additional leakage power reduces their benefit as energy harvesters as demonstrated on our nm multi-core processor. For the role as TECs, we argued that TECs have to be examined alongside DTM methods such as fans and DVFS. Consequently we elaborated the relationship between these three control methods, and as a result proposed a DTM method that is able to simultaneously determine the values for DVFS, TEC current and fan speed to maximize performance subject to thermal constraints and power budgets. We implemented our method T max = 45 C and P max = 45 W DTM with TEC DTM (no TEC inserted) benchmark mean thermal mean cool mean thermal mean cool DVFS viol. (%) pwr (W) DVFS viol. (%) pwr (W) astar bzip gcc tonto calculix Average TABLE I. COMPARISON DTM WITH TEC AND WITHOUT TEC FOR T max = 45 C AND TOTAL POWER BUDGET 45W. mean DVFS IS REPORTED IN GHZ. mean cooling pwr GIVES THE SUM OF TEC AND FAN POWER. thermal viol. IS THE PERCENTAGE OF TIME THE BENCHMARK SPENT ABOVE THE MAXIMUM TEMPERATURE DURING EXECUTION. using state-of-the-art infrastructure, and we concluded that using thermoelectrics as TECs can provide boosts to performance with additional power consumption. In our experiments with a real nm quad-core processor, we demonstrated about 19.6% to performance at the cost of additional cooling power compared to standard DVFS+fan DTM techniques. Acknowledgments: This research is partially supported by NSF grants and REFERENCES [1] B. Alexandrov, K. Z. Ahmed, and S. Mukhopadhyay, An on-chip autonomous thermoelectric energy management system for energyefficient active cooling, in ISLPED, 14, pp [] B. Alexandrov, O. Sullivan, S. Kumar, and S. Mukhopadhyay, Prospects of active cooling with integrated super-lattice based thinfilm thermoelectric devices for mitigating hotspot challenges in microprocessors, in ASP-DAC, 1, pp [3] P. Chaparro, J. Gonzalez, Q. Cai, and G. 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