Dr Yang Yongbo Infineon Technologies, Singapore

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1 Die Attach Void Impact Study on IC Package Thermal Behavior with ANSYS Mechanical Dr Yang Yongbo Infineon Technologies, Singapore

Biography Author Job Title Department : YANG YONGBO : Staff Engineer : IFAP OP BE DEV SIN VDS Biography: Graduated from Nanyang technological University (NTU) Singapore with Ph.

2 Biography Author Job Title Department : YANG YONGBO : Staff Engineer : IFAP OP BE DEV SIN VDS Biography: Graduated from Nanyang technological University (NTU) Singapore with Ph. D degree in mechanical engineering in Aug 2006; Aug 2006-Sep 2009 Field process engineer of plasma etching in Lam Research supporting UMC, SSMC and Chartered Semiconductor; Sep 2009-July 2013 RnD mechanical engineer in UTAC taking care thermo-mechanical simulation and mechanical test; July Present Mechanical engineer for thermo/mechanical simulation in Infineon. 2

Infineon- Part of your life. Part of tomorrow Infineon Technologies, headquarter in Neubiberg near Munich, Germany, a world leader in semiconductor solutions that make life easier, safer and greener.

3 Infineon- Part of your life. Part of tomorrow Infineon Technologies, headquarter in Neubiberg near Munich, Germany, a world leader in semiconductor solutions that make life easier, safer and greener. The key business is about microelectronics : offering semiconductors and systems for Automotive, Industrial Power Control, Power Management & Multimarket as well as Chip Card & Security The simulation team compromises about 20 members, working on visual prototying and development services including thermal, mechanical and mold flow simulation/measurement. In Singapore, there are 4 people. Infineon Technologies Asia Pacific Pte. Ltd (Singapore) 3

4 IC package thermal concept Typical thermal dissipation with die pad grounded Typical leadframe package 4

Problem description Chip Leadframe CDAF void Experimental setup For power IC packages, the thermal dispense is critical to overall package performance.

5 Problem description Chip Leadframe CDAF void Experimental setup For power IC packages, the thermal dispense is critical to overall package performance. Here the die attach is a high conductive die attach film (CDAF) which has high content of silver (Ag). After assembly, some microvoid was found in the CDAF layer. If the void affect the chip temperature by 10%, the package will be rejected. An IR camera is used to select package, as shown in the illustration. Problem: the camera didn t detect clear temperature difference (10%) at mold compound top surface. Thermal simulation to see the reason 5

DMOS (power) Void assumption cases Case Description Illustration 1 No air void Thermal source

6 Thermal modeling cases Total 6 cases, with extreme conditions on void assumption, the temperature response on chip and mold cap top is studied. DMOS (power) Void assumption cases Case Description Illustration 1 No air void Thermal source (DMOS) 2 Center 1/4 area 3 Center 1/2 area 4 Full power area Chip surface powered area (DMOS) 5 Full non-power area 6 Center 1/2 area,top half DA 6

FEM Modeling Half of the package is modelled. The bottom exposed pad area is connected to cooling pad of temperature 25 o C. The void part is defined with air property A power of w=1.

7 FEM Modeling Half of the package is modelled. The bottom exposed pad area is connected to cooling pad of temperature 25 o C. The void part is defined with air property A power of w=1.0w is applied to DMOS area in all cases, and a transient study with steady convection is done. An internal developed film coefficient applied at package surface for convection flow. Package thermal model Chip Inside structure 7

8 Temperature plotting With full void beneath DMOS area, it can cause 9.0 degree difference on chip. Case 1 Unit:Kelvin Case 3 Case 4 Case 5 8

9 Maximum temperature comparison The maximum temp. on chip and minimum temp. on mold cap top are compared. Only case 4 (full void beneath DMOS area) shows significant temperature difference. Junction temperature Case (mold cap) temperature Mold cap top corner Chip top maximum temp 9

10 Average temperature comparison Only case 4 shows big difference on average temperature of DMOS area. if only focused on chip area at mold cap top, the difference is around 3.0 degree. DMOS top area Mold top chip area 10

11 Heat flux of case 1: no air void Without void, the heat flux path is directly down to chip, CDAF and leadframe. Time=1.0E-7s Time=1.78E-6s Time=5.6E-4s Time=0.01s Time=0.178s Time=100s 11

12 Heat flux of case 4: full void beneath DMOS With full void below DMOS area, the heat flux needs to by pass the void area. Time=1.0E-7s Time=1.78E-6s Time=5.6E-4s Time=0.01s Time=0.178s Time=100s 12

13 Conclusion Only if full delam.(void) at DMOS area, the temp. difference could be possibly differentiated by 10%. However, in reality, such case seldom happens, which explains why the IR camera cannot capture the difference. Case Description Illustration 1 No air void 2 Center 1/4 area 3 Center 1/2 area Monitor temp, [deg] Case1 Case2 Case3 Case4 Case5 Case6 DMOS top average temp Mold top chip area average temp value ratio 100% 102.8% 107.9% 123.7% 103.4% 107.5% value ratio 100% 101.8% 104.8% 111.5% 104.3% 104.6% 4 Full power area Chip max. temp value ratio 100% 102.9% 108.2% 127.8% 102.2% 107.8% 5 Full non-power area Zth-JC (deg/w) Center 1/2 area,top half DA 13

14 Computation summary Model Transient thermal study: about 140K nodes, 130K elements Workstation HPZ820, HPC 6 cores of Intel Xeon@2.9GHz, 128GB memory, no GPU ANSYS HPC benefit: With 6 core HPC licenses, 13minutes With 2 core licenses, 30minutes 14

23 rd ASEMEP National Technical Symposium

23 rd ASEMEP National Technical Symposium THE EFFECT OF GLUE BOND LINE THICKNESS (BLT) AND FILLET HEIGHT ON INTERFACE DELAMINATION Raymund Y. Agustin Janet M. Jucar Jefferson S. Talledo Corporate Packaging & Automation/ Q&R STMicroelectronics,