KGC SCIENTIFIC Making of a Chip
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1 KGC SCIENTIFIC Making of a Chip
2 FROM THE SAND TO THE PACKAGE, A DIAGRAM TO UNDERSTAND HOW CPU IS MADE? Sand CPU
3 CHAIN ANALYSIS OF SEMICONDUCTOR Material for manufacturing process of integrated circuit Detergent High purity gas Photo resist Developer Glue dispenser High purity gas Etching gas High purity reagent High purity gas BF3/AsH3/PH3 Detergent High purity gas High purity metal source High purity gas Wafer/Chips Clean Oxidation Graphical Etch Clean Doping CVD Chips Packaging Test Metallization PVD Electroplating Graphical CMP Packaging material Sedimentary gas High purity metal Target materials Electroplating solution Additives Photo resist Developer Glue dispenser High purity gas Polishing solution Polishing pad Detergent
4 Material for packaging process CHAIN ANALYSIS OF SEMICONDUCTOR Wafer Original film polishing with rubber film Wafer polishing Dicing film Wafer slicing Surface mount Mounting Mounting film Mounting glue Metal lead frame -Flip chip -Wire bonding Wire bonding High temperature adhesive tape Gold/Coppe r/ Aluminum wire Printing ink Soldering flux Solder ball Molding Printing Soldering Package bases are cut into separate pieces Carrier reel Carrier tape Functionality test Packaging and transportation Solder paste Soldering flux Solder paste Soldering flux Epoxy molding compound Epoxy resin for washing film Cutting film Carrier Carton packaging
5 Step 1-Sand -With about 25% (mass) Silicon isafter Oxygen-the second most frequent chemical element in the earth s crust. -Sand especially Quartz- has high percentages of Silicon in the form of Silicon dioxide (SiO2) and is the base ingredient for semiconductor manufacturing. Step 2- Melted Silicon -Scale: wafer level (12 inch/300mm) -Silicon is purified in multiple steps to finally reach semiconductor manufacturing quality which is called Electronic Grade Silicon (EGS). -Electronic Grade Silicon may only have one alien atom every one billion Silicon atoms. In this picture shows that how one big crystal is grown from the purified silicon melt. The resulting mono crystal is called Ingot.
6 Step 3-Mono-crystal Silicon Ingot -Scale: wafer level (12inch/300mm) -An ingot has been produced from Electronic Grade Silicon. -One ingot diameter is 300mm cylindrical and weights about 100 kg (=220 pounds) and has a Silicon purity of % Step 4-Ingot Slicing -The ingot is cut into individual silicon discs called wafers.
7 Step 5-Wafer -The wafers are polished until they have flawless, mirror-smooth surfaces. -Intel buys those manufacturing ready wafers from third party companies. -Intel s highly advanced 45nm High-K/Metal Gate process uses wafers with a diameter of 300 mm (12 inch). -When Intel first began making chips, the company printed circuits on 2 inch (50mm) wafers. Step 6- Applying photo resist -The liquid (blue here) that s poured onto the wafer while it spins is a photo resist finish similar as the one known from film photography. -The wafer spins during this step to allow very thin and even application of this photo resist layer.
8 Step 7-Photo Lithography (Exposure) -The photo resist finish is exposed to UV light. -The chemical reaction triggered by that process step is similar to what happens to film material in a film camera the moment you press the shutter button. -The photo resist finish that s exposed to UV light will become soluble. -The exposure is done using masks that act like stencils in this process step. -When used with UV light, masks create the various circuit patterns on each layer of the microprocessor. -A lens(middle) reduces the mask s image. -So what gets printed on the wafer is typically four ties smaller linearly than the mask s pattern.
9 Step 8 Dissolved photo resist - The gooey photo resist is completely dissolved by a solvent (photo lithography exposed to UV light). -This reveals a pattern of photo resist made by the mask. Step 9- Removing photo resist -After the ion implantation the photo resist will be removed and the material that should have been doped to form a transistor.
10 Step 10-Transistor formation -Figure is a point to enlarge the wafer, where there is a transistor. -Green areas represent doped silicon. -Now the wafer will have hundreds of billions of such regions to accommodate transistor. Step 11- Etching -In order to create a fin for the three gate transistor, the image is in the process of the lithography which using a image material called dural sheet(blue). -Then etched away the unwanted silicon with chemical, leaving the fin covered with the dural sheet.
11 7 Step 12- Removing photo resist -The chemical method of hard mask is removed, leaving a large thin silicon wafer, which will contain a transistor channel. Step 13- Silicon dioxide gate dielectric -Scale: transistor level (around nm) -In the lithography stage, a portion of the transistor is covered with a photo resist layer, and a wafer is inserted into the tubular furnace filled with oxygen to produce a thin layer of silicon dioxide (red), which created a temporary gate dielectric.
12 Step 14-Polysilicon gate electrode -Scale: transistor level (around nm) -In the lithography stage, to create a layer of polysilicon (yellow), which created a temporary gate electrode. Step 15- Insulation -Scale: transistor level (around nm) -During the oxidation stage, the silicon dioxide layer (red transparent) of the entire wafer is used to be insulated from other parts. -Intel uses the last gate (also known as instead of the metal gate ) to make the transistor metal gate. -The purpose of this approach is to ensure that the transistor does not appear stability problems, otherwise the high temperature process will lead to instability of the transistor.
13 Step 16-Removing temporary gate -Scale: transistor level (around nm) - The practice of using the diaphragm process, the temporary gate electrode and the gate dielectric are etched. - Real gates will now form because the first gate is removed and the process is called the last gate. Step 17-Use of High-K dielectric -Scale: transistor level (around nm) - During the deposition of the atomic layer, the surface of the wafer is coated with a layer of molecules. - The yellow layer represents the two layer in the layers. -Using lithography, in the unwanted areas (such as the top of the transparent silicon dioxide), the High-K material was etched off.
14 Step 18-Metal Gate -Scale: transistor level (around nm) -Metal electrode is formed on the wafer, and the unwanted area is etched by a method of lithography. -Match up with High-K materials (thin yellow layer), can improve the performance of the body tube, reduce the leakage current, which is the use of traditional silica/ polysilicon gate cannot match. Step 19- Ready Transistor Scale: transistor level (around nm) -This transistor is close to being finished. -Three holes have been etched into the insulation layer above the transistor. -These three holes will be filled with copper which will make up the connections to other transistors.
15 Step 20-Electroplating -The wafers are put into a copper sulphate solution as this stage. -The copper ions are deposited onto the transistor thru a process called electroplating. -The copper ions travel from the positive terminal (anode) to the negative terminal (cathode) which is represented by the wafer. Step 21- Sequential after platingcopper layer -After Electroplating, on the wafer surface the copper ions settle as a thin layer of copper.
16 Step 22-Polishing -Scale transistor level (around 50-20nm) -The excess material is polished off until the copper reveal bright copper. Step 23- Metal layers -Scale: transistor level (six transistors combined around 500nm) -Multiple metal layers are created to interconnect (thick: wires) in between the various transistors. -The specific layout depends on the various functions of the respective processor.
17 Step 24- Metal layers -While computer chips look extremely flat, they may actually have over 20 layers to form complex circuitry. -If look at a magnified view of a chip, will see an intricate network of circuit lines and transistors that look like a futuristic, multilayered highway system. Step 25- Wafer Sort Test -Scale: die level (around 10mm/ around 0.5 inch) -This fraction of a ready wafer is being put to a first functionality test. -In this stage test patterns are fed into every single chip and response from the chip monitored and compared to the right answer.
18 Step 26- Wafer Slicing Step 27- Discarding faulty Dies -Scale: wafer level ( around 300mm/12 inch). -The wafer is cut into pieces (called dies). -The dies that responded with the right answer to the test pattern will be put forward for the next step.
19 Step 28-Individual Die -This is an individual die which has been cut out in the previous step (slicing). -The die shown here is a die of an Intel Core i7 Processor Step 29-Packaging -Scale: package level (around 20mm/ around 1 inch) -The substrate, the die and the heat spreader are put together to form a completed processor. -The substrate (green) builds the electrical and mechanical interface for the processor to interact with the rest of the PC system. -The heat spreader (silver) is a thermal interface where a cooling solution will be put on to. -This will keep the processor cool during operation.
20 Step 30-Processor -Completed processor (Intel Core i7 Processor in this case). -A microprocessor is the most complex manufactured product on earth. -In fact, it takes hundreds of steps-only the most important ones have been visualized in this picture story- in the world s cleanest environment ( a microprocessor fab) to make microprocessors. Step 31-Class Testing -During this final test the processors will be tested for their key characteristics (among the tested characteristics are power dissipation and maximum frequency) -And determines the class of the processor. ( for example, suitable for making the most high-end (Core i7-975 Extreme), or low-end models Core i7-920.)
21 Step 32-Binning Step 33-Retail Package -Based on the test result of class testing processors with the same capabilities are put into the same transporting trays. -The readily manufactures and tested processors ( again Intel Core i7 Processors is shown here) either go to system manufacturers in trays or into retail stores in a box such as that shown here.
22 It can be said, the CPU is the power source of the rapid operation in the modern society, in any electronic devices can be found on the figure of the micro chip. In short, the processors in the manufacturing process can be roughly divided into sand material (quartz), silicon ingots, wafer, photo lithography, etching, ion implantation, deposition of metal, metal layer, interconnection, wafer testing and slicing, core package, class test, listed on packaging and many other steps and each step also contains more detailed process.
23 Thank you This slide presentation is prepared by Research & Development Team, KGC Resources Sdn Bhd Any inquiries, feel free to us at
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