14. Area Optimization

Transcription

1 14. Area Optimization May 2013 QII QII Tis capter describes tecniques to reduce resource usage wen designing or Altera devices. Tis capter includes te ollowing topics: Resource Utilization on page 14 1 on page 14 2 Optimizing Resource Utilization (Macrocell-Based CPLDs) on page Scripting Support on page Resource Utilization Determining device utilization is important regardless o weter your design acieved a successul it. I your compilation results in a no-it error, resource utilization inormation is important or analyzing te itting problems in your design. I your itting is successul, review te resource utilization inormation to determine weter te uture addition o extra logic or oter design canges migt introduce itting diiculties. Also, review te resource utilization inormation to determine i it is impacting timing perormance. To determine resource usage, reer to te Flow Summary section o te Compilation Report. Tis section reports resource utilization, including pins, memory bits, digital signal processing (DSP) blocks, and pase-locked loops (PLLs). Flow Summary indicates weter your design exceeds te available device resources. More detailed inormation is available by viewing te reports under Resource Section in te Fitter section o te Compilation Report. Flow Summary sows te overall logic utilization. Te Fitter can spread logic trougout te device, wic may lead to iger overall utilization. As te device ills up, te Fitter automatically searces or logic unctions wit common inputs to place in one ALM. Te number o packed registers also increases. Tereore, a design tat as ig overall utilization migt still ave space or extra logic i te logic and registers can be packed togeter more tigtly. Te reports under te Resource Section in te Fitter section o te Compilation Report provide more detailed resource inormation. Te Fitter Resource Usage Summary report breaks down te logic utilization inormation and provides oter resource inormation, including te number o bits in eac type o memory block. Tis panel also contains a summary o te usage o global clocks, PLLs, DSP blocks, and oter device-speciic resources Altera Corporation. All rigts reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks o Altera Corporation and registered in te U.S. Patent and Trademark Oice and in oter countries. All oter words and logos identiied as trademarks or service marks are te property o teir respective olders as described at Altera warrants perormance o its semiconductor products to current speciications in accordance wit Altera's standard warranty, but reserves te rigt to make canges to any products and services at any time witout notice. Altera assumes no responsibility or liability arising out o te application or use o any inormation, product, or service described erein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain te latest version o device speciications beore relying on any publised inormation and beore placing orders or products or services. ISO 9001:2008 Registered Quartus II Handbook Version 13.1 May 2013 Twitter Feedback Subscribe

2 14 2 Capter 14: Area Optimization You can also view reports describing some o te optimizations tat occurred during compilation. For example, i you use Quartus II integrated syntesis, te reports in te Optimization Results older in te Analysis & Syntesis section include inormation about registers tat integrated syntesis removed during syntesis. Use tis report to estimate device resource utilization or a partial design to ensure tat registers were not removed due to missing connections wit oter parts o te design. I a speciic resource usage is reported as less tan 100% and a successul it cannot be acieved, eiter tere are not enoug routing resources or some assignments are illegal. In eiter case, a message appears in te Processing tab o te Messages window describing te problem. I te Fitter inises unsuccessully and runs muc aster tan on similar designs, a resource migt be over-utilized or tere migt be an illegal assignment. I te Quartus II sotware seems to run or an excessively long time compared to runs on similar designs, a legal placement or route probably cannot be ound. In te Compilation Report, look or errors and warnings tat indicate tese types o problems. You can use te Cip Planner to ind areas o te device tat ave routing congestion on speciic types o routing resources. I you ind areas wit very ig congestion, analyze te cause o te congestion. Issues suc as ig an-out nets not using global resources, an improperly cosen optimization goal (speed versus area), very restrictive loorplan assignments, or te coding style can cause routing congestion. Ater you identiy te cause, modiy te source or settings to reduce routing congestion. For more inormation about Fitter Resources Report, reer to Fitter Resources Report in Quartus II Help. For inormation about ow to view routing congestion, reer to Displaying Resources and Inormation in Quartus II Help. For inormation about using te Cip Planner tool, reer to About te Cip Planner in Quartus II Help. For details about using te Cip Planner tool, reer to te Analyzing and Optimizing te Design Floorplan wit te Cip Planner capter o te Quartus II Handbook. Ater design analysis, te next stage o design optimization is to improve resource utilization. Complete tis stage beore proceeding to I/O timing optimization or register-to-register timing optimization. Ensure tat you ave already set te basic constraints Initial Compilation: Required Settings section in te Design Optimization Overview capter o te Quartus II Handbook beore proceeding wit te resource utilization optimizations described in tis section. I a design does not it into a speciied device, use te tecniques in tis section to acieve a successul it. Ater you optimize resource utilization and your design its in te desired target device, optimize I/O timing as described in te I/O Timing Optimization Tecniques (LUT-Based Devices) section in te Timing Closure and Optimization capter o te Quartus II Handbook. Tese tips are valid or all FPGA amilies and te MAX II amily o CPLDs. Quartus II Handbook Version 13.1 May 2013 Altera Corporation

3 Capter 14: Area Optimization 14 3 Using te Resource Optimization Advisor Te Resource Optimization Advisor provides guidance in determining settings tat optimize resource usage. To run te Resource Optimization Advisor, on te Tools menu, point to Advisors, and click Resource Optimization Advisor. Te Resource Optimization Advisor provides step-by-step advice about ow to optimize resource usage (logic element, memory block, DSP block, I/O, and routing) o your design. Some o te recommendations in tese categories migt conlict wit eac oter. Altera recommends evaluating te options and coosing te settings tat best suit your requirements. For more inormation about te Resource Optimization Advisor, reer to Resource Optimization Advisor Command (Tools Menu) in Quartus II Help. Resolving Resource Utilization Issues Summary Resource utilization issues can be divided into te ollowing tree categories: Issues relating to I/O pin utilization or placement, including dedicated I/O blocks suc as PLLs or LVDS transceivers (reer to I/O Pin Utilization or Placement ). Issues relating to logic utilization or placement, including logic cells containing registers and LUTs as well as dedicated logic, suc as memory blocks and DSP blocks (reer to Logic Utilization or Placement on page 14 4). Issues relating to routing (reer to Routing on page 14 9). I/O Pin Utilization or Placement Use te suggestions in te ollowing sections to elp you resolve I/O resource problems. Use I/O Assignment Analysis To elp wit pin placement, on te Processing menu, point to Start and click Start I/O Assignment Analysis. Te Start I/O Assignment Analysis command allows you to ceck your I/O assignments early in te design process. You can use tis command to ceck te legality o pin assignments beore, during, or ater compilation o your design. I design iles are available, you can use tis command to accomplis more toroug legality cecks on your design s I/O pins and surrounding logic. Tese cecks include proper reerence voltage pin usage, valid pin location assignments, and acceptable mixed I/O standards. Common issues wit I/O placement relate to te act tat dierential standards ave speciic pin pairings and certain I/O standards migt be supported only on certain I/O banks. I your compilation or I/O assignment analysis results in speciic errors relating to I/O pins, ollow te recommendations in te error message. Rigt-click te message in te Messages window and click Help to open te Quartus II Help topic or tis message. May 2013 Altera Corporation Quartus II Handbook Version 13.1

4 14 4 Capter 14: Area Optimization Modiy Pin Assignments or Coose a Larger Package I a design tat as pin assignments ails to it, compile te design witout te pin assignments to determine weter a it is possible or te design in te speciied device and package. You can use tis approac i a Quartus II error message indicates itting problems due to pin assignments. I te design its wen all pin assignments are ignored or wen several pin assignments are ignored or moved, you migt ave to modiy te pin assignments or te design or select a larger package. I te design ails to it because insuicient I/Os pins are available, a successul it can oten be obtained by using a larger device package (wic can be te same device density) tat as more available user I/O pins. For more inormation about I/O assignment analysis, reer to te I/O Management capter in volume 2 o te Quartus II Handbook. Logic Utilization or Placement Use te suggestions in te ollowing sections to elp you resolve logic resource problems, including logic cells containing registers and LUTs, as well as dedicated logic suc as memory blocks and DSP blocks. Optimize Source Code I your design does not it because o logic utilization, evaluate and modiy te design at te source to acieve te desired results. You can oten improve logic signiicantly by making design-speciic canges to your source code. Tis is typically te most eective tecnique or improving te quality o your results. I your design does not it into available logic elements (LEs) or ALMs, but you ave unused memory or DSP blocks, ceck i you ave code blocks in your design tat describe memory or DSP unctions tat are not being inerred and placed in dedicated logic. You migt be able to modiy your source code to allow tese unctions to be placed into dedicated memory or DSP resources in te target device. Ensure tat your state macines are recognized as state macine logic and optimized appropriately in your syntesis tool. State macines tat are recognized are generally optimized better tan i te syntesis tool treats tem as generic logic. In te Quartus II sotware, you can ceck or te State Macine report under Analysis & Syntesis in te Compilation Report. Tis report provides details, including te state encoding or eac state macine tat was recognized during compilation. I your state macine is not being recognized, you migt ave to cange your source code to enable it to be recognized. For coding style guidelines, including examples o HDL code or inerring memory and DSP unctions, reer to te Instantiating Altera Megaunctions and te Inerring Multiplier and DSP Functions rom HDL Code sections o te Recommended HDL Coding Styles capter in volume 1 o te Quartus II Handbook. For guidelines and sample HDL code or state macines, reer to te General Coding Guidelines section o te Recommended HDL Coding Styles capter in volume 1 o te Quartus II Handbook. Quartus II Handbook Version 13.1 May 2013 Altera Corporation

5 Capter 14: Area Optimization 14 5 For additional HDL coding examples, reer to AN 584: Timing Closure Metodology or Advanced FPGA Designs. Optimize Syntesis or Area, Not Speed I your design ails to it because it uses too muc logic, resyntesize te design to improve te area utilization. First, ensure tat you ave set your device and timing constraints correctly in your syntesis tool. Particularly wen area utilization o te design is a concern, ensure tat you do not over-constrain te timing requirements or te design. Syntesis tools generally try to meet te speciied requirements, wic can result in iger device resource usage i te constraints are too aggressive. I resource utilization is an important concern, some syntesis tools oer an easy way to optimize or area instead o speed. I you are using Quartus II integrated syntesis, select Balanced or Area or te Optimization Tecnique. You can also speciy an Optimization Tecnique logic option or speciic modules in your design wit te Assignment Editor in cases were you want to reduce area using te Area setting (potentially at te expense o register-to-register timing perormance) wile leaving te deault Optimization Tecnique setting at Balanced (or te best trade-o between area and speed or certain device amilies) or Speed. You can also use te Speed Optimization Tecnique or Clock Domains logic option to speciy tat all combinational logic in or between te speciied clock domain(s) is optimized or speed. In some syntesis tools, not speciying an MAX requirement can result in less resource utilization. 1 In te Quartus II sotware, te Balanced setting typically produces utilization results tat are very similar to tose produced by te Area setting, wit better perormance results. Te Area setting can give better results in some cases. For inormation about setting te timing requirements and syntesis options in Quartus II integrated syntesis and oter syntesis tools, reer to te appropriate capter in Syntesis in volume 1 o te Quartus II Handbook, or your syntesis sotware s documentation. Te Quartus II sotware provides additional attributes and options tat can elp improve te quality o your syntesis results. Restructure Multiplexers Multiplexers orm a large portion o te logic utilization in many FPGA designs. By optimizing your multiplexed logic, you can acieve a more eicient implementation in your Altera device. For more inormation about tis option, reer to Restructure Multiplexers logic option in Quartus II Help. For design guidelines to acieve optimal resource utilization or multiplexer designs, reer to te Recommended HDL Coding Styles capter in volume 1 o te Quartus II Handbook. May 2013 Altera Corporation Quartus II Handbook Version 13.1

6 14 6 Capter 14: Area Optimization Perorm WYSIWYG Primitive Resyntesis wit Balanced or Area Setting Te Perorm WYSIWYG Primitive Resyntesis logic option speciies weter to perorm WYSIWYG primitive resyntesis during syntesis. Tis option uses te setting speciied in te Optimization Tecnique logic option. Te Perorm WYSIWYG Primitive Resyntesis logic option is useul or resyntesizing some or all o te WYSIWYG primitives in your design or better area or perormance. However, WYSIWYG primitive resyntesis can be done only wen you use tird-party syntesis tools. 1 Te Balanced setting typically produces utilization results tat are very similar to te Area setting wit better perormance results. Te Area setting can give better results in some cases. Perorming WYSIWYG resyntesis or area in tis way typically reduces register-to-register timing perormance. For inormation about tis logic option, reer to Perorm WYSIWYG Primitive Resyntesis logic option in Quartus II Help. Use Register Packing Te Auto Packed Registers option implements te unctions o two cells into one logic cell by combining te register o one cell in wic only te register is used wit te LUT o anoter cell in wic only te LUT is used. For more inormation, reer to Auto Packed Registers logic option in Quartus Help. Remove Fitter Constraints A design wit conlicting constraints or constraints tat are diicult to meet may not it in te targeted device. For example, a design migt ail to it i te location or LogicLock assignments are too strict and not enoug routing resources are available on te device. To resolve routing congestion caused by restrictive location constraints or LogicLock region assignments, use te Routing Congestion task in te Cip Planner to locate routing problems in te loorplan, ten remove any internal location or LogicLock region assignments in tat area. I your design still does not it, te design is over-constrained. To correct te problem, remove all location and LogicLock assignments and run successive compilations, incrementally constraining te design beore eac compilation. You can delete speciic location assignments in te Assignment Editor or te Cip Planner. To remove LogicLock assignments in te Cip Planner, in te LogicLock Regions Window, or on te Assignments menu, click Remove Assignments. Turn on te assignment categories you want to remove rom te design in te Available assignment categories list. For more inormation about te Routing Congestion task in te Cip Planner, reer to Analyzing and Optimizing te Design Floorplan wit te Cip Planner o te Quartus II Handbook. Quartus II Handbook Version 13.1 May 2013 Altera Corporation

7 Capter 14: Area Optimization 14 7 Flatten te Hierarcy During Syntesis Syntesis tools typically provide te option o preserving ierarcical boundaries, wic can be useul or veriication or oter purposes. However, te Quartus II sotware optimizes across ierarcical boundaries so as to perorm te most logic minimization, wic can reduce area in a design wit no design partitions. I you are using Quartus II incremental compilation, you cannot latten your design across design partitions. Incremental compilation always preserves te ierarcical boundaries between design partitions, and te syntesis does not latten it across partitions. Follow Altera s recommendations or design partitioning, suc as registering partition boundaries to reduce te eect o cross-boundary optimizations. For more inormation about using incremental compilation and recommendations or design partitioning, reer to te Quartus II Incremental Compilation or Hierarcical and Team-Based Design and Best Practices or Incremental Compilation Partitions and Floorplan Assignments capters in volume 1 o te Quartus II Handbook. Retarget Memory Blocks I your design ails to it because it runs out o device memory resources, your design may require a certain type o memory tat te device does not ave. For example, a design tat requires two M-RAM blocks cannot be targeted to a Stratix EP1S10 device, wic as only one M-RAM block. You migt be able to obtain a it by building one o te memories wit a dierent size memory block, suc as an M4K memory block. I te memory block was created wit te MegaWizard Plug-In Manager, open te MegaWizard Plug-In Manager and edit te RAM block type so it targets a new memory block size. ROM and RAM memory blocks can also be inerred rom your HDL code, and your syntesis sotware can place large sit registers into memory blocks by inerring te ALTSHIFT_TAPS megaunction. Tis inerence can be turned o in your syntesis tool to cause te memory or sit registers to be placed in logic instead o in memory blocks. Also, or improved timing perormance, you can turn tis inerence o to prevent registers rom being moved into RAM. For more inormation, reer to Auto RAM Replacement logic option, Auto ROM Replacement logic option, and Auto Sit Register Replacement logic option in Quartus II Help. Depending on your syntesis tool, you can also set te RAM block type or inerred memory blocks. In Quartus II integrated syntesis, set te ramstyle attribute to te desired memory type or te inerred RAM blocks, or set te option to logic, to implement te memory block in standard logic instead o a memory block. May 2013 Altera Corporation Quartus II Handbook Version 13.1

8 14 8 Capter 14: Area Optimization Consider te Resource Utilization by Entity report in te report ile and determine weter tere is an unusually ig register count in any o te modules. Some coding styles can prevent te Quartus II sotware rom inerring RAM blocks rom te source code because o te blocks arcitectural implementation, and orce te sotware to implement te logic in liplops. As an example, a unction suc as an asyncronous reset on a register bank migt make te resistor bank incompatible wit te RAM blocks in te device arcitecture, so tat te register bank is implemented in liplops. It is oten possible to move a large register bank into RAM by sligt modiication o associated logic. For more inormation about memory inerence control in oter syntesis tools, reer to te appropriate capter in Syntesis in volume 1 o te Quartus II Handbook, or your syntesis sotware s documentation. For more inormation about coding styles and HDL examples tat ensure memory inerence, reer to te Recommended HDL Coding Styles capter in volume 1 o te Quartus II Handbook. Use Pysical Syntesis Options to Reduce Area Te pysical syntesis options or itting elp you decrease resource usage. Wen you enable tese options, te Quartus II sotware makes placement-speciic canges to te netlist tat reduce resource utilization or a speciic Altera device. 1 Te compilation time migt increase considerably wen you use pysical syntesis options. Wit te Quartus II sotware, you can apply pysical syntesis options to speciic instances, wic can reduce te impact on compilation time. Pysical syntesis instance assignments allow you to enable pysical syntesis algoritms or speciic portions o your design. Te ollowing pysical syntesis optimizations or itting are available: Pysical syntesis or combinational logic Map logic into memory For more inormation, reer to Pysical Syntesis Optimizations Page (Settings Dialog Box) in Quartus II Help. Retarget or Balance DSP Blocks A design migt not it because it requires too many DSP blocks. You can implement all DSP block unctions wit logic cells, so you can retarget some o te DSP blocks to logic to obtain a it. I te DSP unction was created wit te MegaWizard Plug-In Manager, open te MegaWizard Plug-In Manager and edit te unction so it targets logic cells instead o DSP blocks. Te Quartus II sotware uses te DEDICATED_MULTIPLIER_CIRCUITRY megaunction parameter to control te implementation. Quartus II Handbook Version 13.1 May 2013 Altera Corporation

9 Capter 14: Area Optimization 14 9 DSP blocks also can be inerred rom your HDL code or multipliers, multiply-adders, and multiply-accumulators. You can turn o tis inerence in your syntesis tool. Wen you are using Quartus II integrated syntesis, you can disable inerence by turning o te Auto DSP Block Replacement logic option or your entire project. On te Assignments menu, click Settings. In te Category list, select Analysis & Syntesis Settings, click More Settings, and turn o Auto DSP Block Replacement. Alternatively, you can disable te option or a speciic block wit te Assignment Editor. For more inormation about disabling DSP block inerence in oter syntesis tools, reer to te appropriate capter in Syntesis in volume 1 o te Quartus II Handbook, or your syntesis sotware s documentation. Te Quartus II sotware also oers te DSP Block Balancing logic option, wic implements DSP block elements in logic cells or in dierent DSP block modes. Te deault Auto setting allows DSP block balancing to convert te DSP block slices automatically as appropriate to minimize te area and maximize te speed o te design. You can use oter settings or a speciic node or entity, or on a project-wide basis, to control ow te Quartus II sotware converts DSP unctions into logic cells and DSP blocks. Using any value oter tan Auto or O overrides te DEDICATED_MULTIPLIER_CIRCUITRY parameter used in megaunction variations. For more details about te Quartus II logic options described in tis section, reer to Auto DSP Block Replacement logic option and DSP Block Balancing logic option in Quartus II Help. Use a Larger Device I a successul it cannot be acieved because o a sortage o LEs, ALMs, memory, or DSP blocks, you migt require a larger device. Routing Use te suggestions in te ollowing sections to elp you resolve routing resource problems. Set Auto Packed Registers to Sparse or Sparse Auto Te Auto Packed Registers option reduces LE or ALM count in a design.you can set tis option in te Assignment Editor or by clicking More Settings on te Fitter Settings page in te Settings dialog box. For more inormation, reer to Auto Packed Registers logic option in Quartus II Help. May 2013 Altera Corporation Quartus II Handbook Version 13.1

10 14 10 Capter 14: Area Optimization Set Fitter Aggressive Routability Optimizations to Always Te Fitter Aggressive Routability Optimization option is useul i your design does not it due to excessive routing wire utilization. I tere is a signiicant imbalance between placement and routing time (during te irst itting attempt), it migt be because o ig wire utilization. Turning on te Fitter Aggressive Routability Optimizations option can reduce your compilation time. On average, tis option can save up to 6% wire utilization, but can also reduce perormance by up to 4%, depending on te device. For more inormation, reer to Fitter Aggressive Routability Optimizations logic option in Quartus II Help. Increase Router Eort Multiplier Te Router Eort Multiplier controls ow quickly te router tries to ind a valid solution. Te deault value is 1.0 and legal values must be greater tan 0. Numbers iger tan 1 elp designs tat are diicult to route by increasing te routing eort. Numbers closer to 0 (or example, 0.1) can reduce router runtime, but usually reduce routing quality sligtly. Experimental evidence sows tat a multiplier o 3.0 reduces overall wire usage by approximately 2%. Using a Router Eort Multiplier iger tan te deault value could be beneicial or designs wit complex datapats wit more tan ive levels o logic. However, congestion in a design is primarily due to placement, and increasing te Router Eort Multiplier does not necessarily reduce congestion. 1 Any Router Eort Multiplier value greater tan 4 only increases by 10% or every additional 1. For example, a value o 10 is actually 4.6. For more inormation, reer to Router Eort Multiplier logic option in Quartus II Help. Remove Fitter Constraints A design wit conlicting constraints or constraints tat are diicult to acieve may not it te targeted device. Conlicting or diicult-to-acieve constraints can occur wen location or LogicLock assignments are too strict and tere are not enoug routing resources. In tis case, use te Routing Congestion task in te Cip Planner to locate routing problems in te loorplan, ten remove all location and LogicLock region assignments rom tat area. I te local constraints are removed, and te design still does not it, te design is over-constrained. To correct te problem, remove all location and LogicLock assignments and run successive compilations, incrementally constraining te design beore eac compilation. You can delete speciic location assignments in te Assignment Editor or te Cip Planner. To remove LogicLock assignments in te Cip Planner, in te LogicLock Regions Window, or on te Assignments menu, click Remove Assignments. Turn on te assignment categories you want to remove rom te design in te Available assignment categories list. Quartus II Handbook Version 13.1 May 2013 Altera Corporation

11 Capter 14: Area Optimization For more inormation about te Routing Congestion task in te Cip Planner, reer to te Analyzing and Optimizing te Design Floorplan wit te Cip Planner capter in volume 2 o te Quartus II Handbook. You can also reer to About te Cip Planner in Quartus II Help. Optimize Syntesis or Area, Not Speed In some cases, resyntesizing te design to improve te area utilization can also improve te routability o te design. First, ensure tat you ave set your device and timing constraints correctly in your syntesis tool. Ensure tat you do not overconstrain te timing requirements or te design, particularly wen te area utilization o te design is a concern. Syntesis tools generally try to meet te speciied requirements, wic can result in iger device resource usage i te constraints are too aggressive. I resource utilization is important to improve te routing results in your design, some syntesis tools oer an easy way to optimize or area instead o speed. I you are using Quartus II integrated syntesis, on te Assignments menu, click Settings. In te Category list, select Analysis & Syntesis Settings and select Balanced or Area under Optimization Tecnique. You can also speciy tis logic option or speciic modules in your design wit te Assignment Editor in cases were you want to reduce area using te Area setting (potentially at te expense o register-to-register timing perormance). You can apply te setting to speciic modules wile leaving te deault Optimization Tecnique setting at Balanced (or te best trade-o between area and speed or certain device amilies) or Speed. You can also use te Speed Optimization Tecnique or Clock Domains logic option to speciy tat all combinational logic in or between te speciied clock domain(s) is optimized or speed. 1 In te Quartus II sotware, te Balanced setting typically produces utilization results tat are very similar to tose obtained wit te Area setting, wit better perormance results. Te Area setting can yield better results in some unusual cases. In some syntesis tools, not speciying an MAX requirement can result in less resource utilization, wic can improve routability. For inormation about setting te timing requirements and syntesis options in Quartus II integrated syntesis and oter syntesis tools, reer to te appropriate capter in Syntesis in volume 1 o te Quartus II Handbook, or your syntesis sotware s documentation. May 2013 Altera Corporation Quartus II Handbook Version 13.1

12 14 12 Capter 14: Area Optimization Optimizing Resource Utilization (Macrocell-Based CPLDs) Optimize Source Code I your design does not it because o routing problems and te metods described in te preceding sections do not suiciently improve te routability o te design, modiy te design at te source to acieve te desired results. You can oten improve results signiicantly by making design-speciic canges to your source code, suc as duplicating logic or canging te connections between blocks tat require signiicant routing resources. Use a Larger Device I a successul it cannot be acieved because o a sortage o routing resources, you migt require a larger device. Optimizing Resource Utilization (Macrocell-Based CPLDs) Te ollowing recommendations elp you take advantage o te macrocell-based arcitecture in te MAX 7000 and MAX 3000 devices to yield maximum speed, reliability, and device resource utilization wile minimizing itting diiculties. Ater design analysis, te irst stage o design optimization is to improve resource utilization. Complete tis stage beore proceeding to timing optimization. First, ensure tat you ave set te basic constraints described in Initial Compilation: Required Settings section in te Design Optimization Overview capter o te Quartus II Handbook. I your design is not itting into a speciied device, use te tecniques in tis section to acieve a successul it. Use Dedicated Inputs or Global Control Signals MAX 7000 and MAX 3000 devices ave our dedicated inputs tat you can use or global register control. Because te global register control signals can bypass te logic cell array and directly eed registers, product terms can be preserved or primary logic. Also, because eac signal as a dedicated pat into te LAB, global signals also can bypass logic and data pat interconnect resources. Because te dedicated input pins are designed or ig an-out control signals and provide low skew, always assign global signals (suc as clock, clear, and output enable) to te dedicated input pins. You can use logic-generated control signals or global control signals instead o dedicated inputs. However, te ollowing list sows te disadvantages o using logic-generated control signals: More resources are required (logic cells, interconnect). More data skew is introduced. I te logic-generated control signals ave ig an-out, te design can be more diicult to it. By deault, te Quartus II sotware uses dedicated inputs or global control signals automatically. You can assign control signals to dedicated input pins in one o te ollowing ways: Quartus II Handbook Version 13.1 May 2013 Altera Corporation

13 Capter 14: Area Optimization Optimizing Resource Utilization (Macrocell-Based CPLDs) In te Assignment Editor, select one o te two ollowing metods: Assign pins to dedicated pin locations. Assign a Global Signal setting to te pins. On te Assignments menu, click Settings. On te Analysis & Syntesis Settings page, click More Settings, and in te Existing Option settings section, select Auto Global Register Control Signals. Insert a GLOBAL primitive ater te pins. Reserve Device Resources Because pin and logic option assignments can be necessary or board layout and perormance requirements, and because ull utilization o te device resources can increase te diiculty o itting te design, Altera recommends leaving 10% o te logic cells and 5% o te I/O pins unused to accommodate uture design modiications. Following te Altera-recommended device resource reservation guidelines or macrocell-based CPLDs increases te cance tat te Quartus II sotware can it te design during recompilation ater canges or assignments ave been made. Pin Assignment Guidelines and Procedures Sometimes user-speciied pin assignments are necessary or board layout. Tis section describes pin assignment guidelines and procedures. To minimize itting issues wit pin assignments, ollow tese guidelines: Assign speed-critical control signals to dedicated inputs. Assign output enables (OE) pin to appropriate locations. Estimate an-in to assign output pins to te appropriate LAB. Assign output pins tat require parallel expanders to macrocells numbered 4 to Altera recommends allowing te Quartus II sotware to select pin assignments automatically wen possible. You can use te Quartus II Pin Advisor eature (accessible rom te Tools menu) or pin connection guidelines. For more inormation about te Pin Advisor, reer to Pin Advisor Command (Tools Menu) in Quartus II Help. Control Signal Pin Assignments Assign speed-critical control signals to dedicated input pins. Every MAX 7000 and MAX 3000 device as our dedicated input pins (GCLK1, OE2/GCLK2, OE1, and GCLRn). You can assign clocks to global clock dedicated inputs (GCLK1 and OE2/GCLK2), assign clear signals to te global clear dedicated input (GCLRn), and speed-critical OE signals to global OE dedicated inputs (OE1 and OE2/GCLK2). Output Enable Pin Assignments Occasionally, because te total number o required output enable pins is more tan te dedicated input pins, output enable signals must be assigned to I/O pins. May 2013 Altera Corporation Quartus II Handbook Version 13.1

14 14 14 Capter 14: Area Optimization Optimizing Resource Utilization (Macrocell-Based CPLDs) To minimize possible itting errors wen assigning te output enable pins or MAX 7000 and MAX 3000 devices, reer to Pin-Out Files or Altera Devices on te Altera website ( Estimate Fan-In Wen Assigning Output Pins Macrocells wit ig an-in can cause more placement problems or te Quartus II Fitter tan tose wit low an-in. Te maximum an-in per LAB sould not exceed 36 in MAX 7000 and MAX 3000 devices. Tereore, estimate te an-in o logic (suc as an x-input AND gate) tat eeds eac output pin. I te total an-in o logic tat eeds eac output pin in te same LAB exceeds 36, compilation can ail. To save resources and prevent compilation errors, avoid assigning pins tat ave ig an-in. Outputs Using Parallel Expander Pin Assignments Figure 14 1 sows ow parallel expanders are used witin a LAB. MAX 7000 and MAX 3000 devices contain cains tat can lend or borrow parallel expanders. Te Quartus II Fitter places macrocells in a location tat allows tem to lend and borrow parallel expanders appropriately. As sown in Figure 14 1, only macrocells 2 troug 16 can borrow parallel expanders. Tereore, assign output pins tat migt require parallel expanders to pins adjacent to macrocells 4 troug 16. Altera recommends using macrocells 4 troug 16 because tey can borrow te largest number o parallel expanders. Figure LAB Macrocells and Parallel Expander Associations Macrocell 1 cannot borrow any parallel expanders. Macrocell 3 borrows up to ten parallel expanders rom Macrocells 1 and 2. LAB A Macrocell 1 Macrocell 2 Macrocell 3 Macrocell 4 Macrocell 5 Macrocell 6 Macrocell 7 Macrocell 8 Macrocell 9 Macrocell 10 Macrocell 11 Macrocell 12 Macrocell 13 Macrocell 14 Macrocell 15 Macrocell 16 Macrocell 2 borrows up to ive parallel expanders rom Macrocell 1. Macrocells 4 troug 16 borrow up to 15 parallel expanders rom te tree immediately preceding macrocells. Quartus II Handbook Version 13.1 May 2013 Altera Corporation

15 Capter 14: Area Optimization Optimizing Resource Utilization (Macrocell-Based CPLDs) Resolving Resource Utilization Problems Excessive macrocell usage and lack o routing resources can cause resource utilization problems. Macrocell usage errors occur wen te total number o macrocells in te design exceed te available macrocells in te device. Routing errors occur wen te available routing resources are insuicient to implement te design. Ceck te Message window or te compilation results. 1 Messages in te Messages window are also copied in te Report Files. For more inormation about te message, rigt-click a message and click Help. Resolving Macrocell Usage Issues Occasionally, a design requires more macrocell resources tan are available in te selected device, wic results in te design not itting. Te ollowing list provides tips or resolving macrocell usage issues as well as tips to minimize te number o macrocells used: On te Assignments menu, click Settings. In te Category list, select Analysis & Syntesis Settings, click More Settings, and turn o Auto Parallel Expanders. I te design s clock requency ( MAX ) is not an important design requirement, turn o parallel expanders or all or part o te project. Te design usually requires more macrocells i parallel expanders are turned on. Cange Optimization Tecnique rom Speed to Area. Selecting Area instructs te compiler to give preerence to area utilization rater tan speed ( MAX ). On te Assignments menu, click Settings. In te Category list, cange te Optimization Tecnique option in te Analysis & Syntesis Settings page. Use D-type liplops instead o latces. Altera recommends always using D-type liplops instead o latces in your design because D-type liplops can reduce te macrocell an-in, and tus reduce macrocell usage. Te Quartus II sotware uses extra logic to implement latces in MAX 7000 and MAX 3000 designs because MAX 7000 and MAX 3000 macrocells contain D-type liplops instead o latces. Use asyncronous clear and preset instead o syncronous clear and preset. To reduce product term usage, use asyncronous clear and preset in your design wenever possible. Using oter control signals suc as syncronous clear produces macrocells and pins wit iger an-out. 1 Ater ollowing te suggestions in tis section, i your project still does not it te targeted device, consider using a larger device. Wen upgrading to a dierent density, te vertical package-migration eature o te MAX 7000 and MAX 3000 device amilies allows pin assignments to be maintained. May 2013 Altera Corporation Quartus II Handbook Version 13.1

16 14 16 Capter 14: Area Optimization Optimizing Resource Utilization (Macrocell-Based CPLDs) Resolving Routing Issues Routing is anoter resource tat can cause design itting issues. For example, i te total an-in into a LAB exceeds te maximum allowed, a no-it error can occur during compilation. I your design does not it te targeted device because o routing issues, consider te ollowing suggestions: Use dedicated inputs/global signals or ig an-out signals. Te dedicated inputs in MAX 7000 and MAX 3000 devices are designed or speed-critical and ig an-out signals. Always assign ig an-out signals to dedicated inputs/global signals. Cange te Optimization Tecnique option rom Speed to Area. Tis option can resolve routing resource and macrocell usage issues. Reer to Resolving Macrocell Usage Issues on page Reduce te an-in per cell. I you are not limited by te number o macrocells used in te design, you can use te Fan-in per cell (%) option to reduce te an-in per cell. Te allowable values are %; te deault value is 100%. Reducing an-in can reduce localized routing congestion but increase te macrocell count. You can set tis logic option in te Assignment Editor or under More Settings in te Analysis & Syntesis Settings page o te Settings dialog box. On te Assignments menu, click Settings. In te Category list, select Analysis & Syntesis Settings, click More Options, and turn o Auto Parallel Expanders. By turning o te parallel expanders, you give te Quartus II sotware more itting lexibility or eac macrocell, allowing macrocells to be relocated. For example, you can move eac macrocell (previously grouped togeter in te same LAB) to a dierent LAB to reduce routing constraints. Insert logic cells. Inserting logic cells reduces an-in and sared expanders used per macrocell, increasing routability. By deault, te Quartus II sotware automatically inserts logic cells wen necessary. Oterwise, you can disable Auto Logic Cell as ollows: 1. On te Assignments menu, click Settings. 2. In te Category list, select Analysis & Syntesis Settings. 3. Under More Settings, turn o Auto Logic Cell Insertion. For more inormation, reer to Using LCELL Buers to Reduce Required Resources. Cange pin assignments. I you want to discard your pin assignments, you can let te Quartus II Fitter ignore some or all o te assignments. 1 I you preer reassigning pins to increase routing eiciency, reer to Pin Assignment Guidelines and Procedures on page Using LCELL Buers to Reduce Required Resources Complex logic, suc as multilevel XOR gates, are oten implemented wit more tan one macrocell. Wen tis occurs, te Quartus II sotware automatically allocates sareable expanders or additional macrocells (called syntesized logic cells) to supplement te logic resources tat are available in a single macrocell. You can also break down complex logic by inserting logic cells in te project to reduce te average an-in and te total number o sareable expanders required. Manually inserting logic cells can provide greater control over speed-critical pats. Quartus II Handbook Version 13.1 May 2013 Altera Corporation

17 Capter 14: Area Optimization Scripting Support Instead o using te Auto Logic Cell Insertion option, you can manually insert logic cells. However, Altera recommends using te Auto Logic Cell Insertion option unless you know wic part o te design is causing te congestion. A good location to manually insert LCELL buers is were a single complex logic expression eeds multiple destinations in your design. You can insert an LCELL buer just ater te complex expression; te Fitter extracts tis complex expression and places it in a separate logic cell. Rater tan duplicate all te logic or eac destination, te Quartus II sotware eeds te single output rom te logic cell to all destinations. To reduce an-in and prevent no-it compilations caused by routing resource issues, insert an LCELL buer ater a NOR gate (Figure 14 2). Te design in Figure 14 2 was compiled or a MAX 7000AE device. Witout te LCELL buer, te design requires two macrocells and eigt sareable expanders, and te average an-in is 14.5 macrocells. However, wit te LCELL buer, te design requires tree macrocells and eigt sareable expanders, and te average an-in is just 6.33 macrocells. Figure Reducing te Average Fan-In by Inserting LCELL Buers Scripting Support You can run procedures and make settings described in tis capter in a Tcl script. You can also run some procedures at a command prompt. For detailed inormation about scripting command options, reer to te Quartus II command-line and Tcl API Help browser. To run te Help browser, type te ollowing command at te command prompt: quartus_s --qelp r May 2013 Altera Corporation Quartus II Handbook Version 13.1

18 14 18 Capter 14: Area Optimization Scripting Support For more inormation about Tcl scripting, reer to te Tcl Scripting capter in volume 2 o te Quartus II Handbook. For more inormation about all settings and constraints in te Quartus II sotware, reer to te Quartus II Settings File Manual. For more inormation about command-line scripting, reer to te Command-Line Scripting capter in volume 2 o te Quartus II Handbook. You can speciy many o te options described in tis section eiter in an instance, or at a global level, or bot. Use te ollowing Tcl command to make a global assignment: set_global_assignment -name <.qs variable name> <value> r Use te ollowing Tcl command to make an instance assignment: set_instance_assignment -name <.qs variable name> <value> \ -to <instance name> r 1 I te <value> ield includes spaces (or example, Standard Fit ), you must enclose te value in straigt double quotation marks. Initial Compilation Settings Table Advanced Compilation Settings Use te Quartus II Settings File (.qs) variable name in te Tcl assignment to make te setting along wit te appropriate value. Te Type column indicates weter te setting is supported as a global setting, an instance setting, or bot. Table 14 1 lists te advanced compilation settings. Setting Name.qs File Variable Name Values Type Placement Eort Multiplier PLACEMENT_EFFORT_MULTIPLIER Any positive, non-zero value Global Router Eort Multiplier ROUTER_EFFORT_MULTIPLIER Any positive, non-zero value Global Router Timing Optimization level ROUTER_TIMING_OPTIMIZATION_LEVEL NORMAL, MINIMUM, MAXIMUM Global Final Placement Optimization FINAL_PLACEMENT_OPTIMIZATION ALWAYS, AUTOMATICALLY, NEVER Global Resource Utilization Optimization Tecniques (LUT-Based Devices) Table 14 2 lists te.qs ile variable name and applicable values or te settings described in on page Table Resource Utilization Optimization Settings (Part 1 o 2) Setting Name.qs File Variable Name Values Type Auto Packed Registers (1) Perorm WYSIWYG Primitive Resyntesis AUTO_PACKED_REGISTERS_<device amily name> ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP OFF, NORMAL, MINIMIZE AREA, MINIMIZE AREA WITH CHAINS, AUTO ON, OFF Global, Instance Global, Instance Quartus II Handbook Version 13.1 May 2013 Altera Corporation

19 Capter 14: Area Optimization Document Revision History Table Resource Utilization Optimization Settings (Part 2 o 2) Setting Name.qs File Variable Name Values Type Pysical Syntesis or Combinational Logic or Reducing Area Pysical Syntesis or Mapping Logic to Memory Optimization Tecnique Speed Optimization Tecnique or Clock Domains State Macine Encoding Auto RAM Replacement Auto ROM Replacement Auto Sit Register Replacement Auto Block Replacement Number o Processors or Parallel Compilation Note to Table 14 2: Document Revision History PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR AREA <device amily name>_optimization_technique Table 14 3 lists te revision istory or tis document. ON, OFF ON, OFF AREA, SPEED, BALANCED Global, Instance Global, Instance Global, Instance SYNTH_CRITICAL_CLOCK ON, OFF Instance STATE_MACHINE_PROCESSING AUTO_RAM_RECOGNITION AUTO_ROM_RECOGNITION AUTO_SHIFT_REGISTER_RECOGNITION AUTO_DSP_RECOGNITION NUM_PARALLEL_PROCESSORS (1) Allowed values or tis setting depend on te device amily tat you select. Table Document Revision History Date Version Canges May Initial release. AUTO, ONE-HOT, GRAY, JOHNSON, MINIMAL BITS, ONE-HOT, SEQUENTIAL, USER-ENCODE ON, OFF ON, OFF ON, OFF ON, OFF Integer between 1 and 16 inclusive, or ALL Global, Instance Global, Instance Global, Instance Global, Instance Global, Instance Global May 2013 Altera Corporation Quartus II Handbook Version 13.1

20 14 20 Capter 14: Area Optimization Document Revision History Quartus II Handbook Version 13.1 May 2013 Altera Corporation