1024K X 16 BIT LOW POWER CMOS SRAM

Size: px

Start display at page:

Download "1024K X 16 BIT LOW POWER CMOS SRAM"

Oliver Randall
6 years ago
Views:

1 FEATURES Process Technology : 0.15μm Full CMOS Organization : 1M x 16 bit Power Supply Voltage : 2.7V ~ 3.6V Low Data Retention Voltage : 1.5V(Min.) Three state output and TTL Compatible Package Type : 48-FPBGA GENERAL DESCRIPTION The - 55 is fabricated by Alliance's advanced full CMOS process technology. The device supports industrial temperature range and Chip Scale Package for user flexibility of system design. The device also supports low data retention voltage for battery backup operation with low data retention current. PRODUCT FAMILY Product Family Operating Temperature Vcc Range Speed Power Dissipation Standby (I SB1, Typ.) Operating (I CC1.Max.) PKG Type - 55 BIN Industrial (-40 ~ 85 o C) 2.7 ~ 3.6 V 55ns 4 μa 1) 8 ma 48-FPBGA 1. Typical values are measured at Vcc=3.3V, T A =25 o C and not 100% tested. FUNCTIONAL BLOCK DIAGRAM Pre-charge Circuit A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 Row Select Memory Array 1M x 16 V CC V SS DQ8 ~ DQ15 DQ0 ~ DQ7 Data Cont Data Cont I/O Circuit Column Select A11 A12 A13 A14 A15 A16 A17 A18 A19 WE OE UB LB CS1 Control Logic 1

2 PIN CONFIGURATIONS FPBGA-48 : Top view(ball down) A LB OE A0 A1 A2 B DQ8 UB A3 A4 CS1 DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 D V SS DQ11 A17 A7 DQ3 V CC E V CC DQ12 NC A16 DQ4 V SS F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 A19 A12 A13 WE DQ7 H A18 A8 A9 A10 A11 NC PIN DESCRIPTION Name Function Name Function CS1, Chip Select inputs V CC Power Supply OE Output Enable input V SS Ground WE Write Enable input UB Upper Byte (DQ8~DQ15) A0~A19 Address inputs LB Lower Byte (DQ0~DQ7) DQ0~DQ15 Data inputs/outputs NC No Connection 2

3 ABSOLUTE MAXIMUM RATINGS 1) Parameter Symbol Ratings Unit Voltage on Any Pin Relative to Vss V IN, V OUT -0.2 to 4.0 V Voltage on Vcc supply relative to Vss V CC -0.2 to 4.0 V Power Dissipation P D 1.0 W Operating Temperature T A -40 to 85 o C 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. FUNCTIONAL DESCRIPTION CS1 OE WE LB UB DQ0~7 DQ8~15 Mode Power H X X X X X Deselected Stand by X L X X X X Deselected Stand by X X X X H H Deselected Stand by L H H H L X Output Disabled Active L H H H X L Output Disabled Active L H L H L H Data Out Lower Byte Read Active L H L H H L Data Out Upper Byte Read Active L H L H L L Data Out Data Out Word Read Active L H X L L H Data In Lower Byte Write Active L H X L H L Data In Upper Byte Write Active L H X L L L Data In Data In Word Write Active NOTE : X means don t care. (Must be low or high state) 3

4 RECOMMENDED DC OPERATING CONDITIONS 1) Parameter Symbol Min Typ Max Unit Supply voltage V CC V Ground V SS V Input high voltage V IH V CC ) V Input low voltage V IL ) V 1. TA= -40 to 85 o C, otherwise specified 2. Overshoot: VCC +2.0 V in case of pulse width < 20ns 3. Undershoot: -2.0 V in case of pulse width < 20ns 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE 1) (f =1MHz, T A =25 o C) Item Symbol Test Condition Min Max Unit Input capacitance C IN V IN =0V - 8 pf Input/Ouput capacitance C IO V IO =0V - 10 pf 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Parameter Symbol Test Conditions Min Typ Max Unit Input leakage current I LI V IN =V SS to V CC -1-1 μa Output leakage current I LO CS1=V IH or =V IL or OE=V IH or WE=V IL or LB=UB=V IH V IO =V SS to V CC -1-1 μa Operating power supply I CC I IO =0mA, CS1=V IL, =WE=V IH, V IN =V IH or V IL ma Average operating current I CC1 I CC2 Cycle time=1μs, 100% duty, I IO =0mA, CS1<0.2V, >V CC -0.2V, LB<0.2V or/and UB<0.2V, V IN <0.2V or V IN >V CC -0.2V Cycle time = Min, I IO =0mA, 100% duty, CS1=V IL, =V IH, LB=V IL or/and UB=V IL, V IN =V IL or V IH 55ns ma 70 ma Output low voltage V OL I OL = 2.1mA V Output high voltage V OH I OH = -1.0mA V Standby Current (TTL) I SB CS1=V IH, =V IL, Other inputs=v IH or V IL ma Standby Current (CMOS) I SB1 CS1>V CC -0.2V, >V CC -0.2V (CS1 controlled) or 0V<<0.2V ( controlled), Other inputs = 0~V CC (Typ. condition : V CC 25 o C) LF - 4 1) 30 μa (Max. condition : V CC 85 o C) 1. Typical values are measured at Vcc=3.3V, T A =25 o C and not 100% tested. 4

5 AC OPERATING CONDITIONS Test Conditions (Test Load and Test Input/Output Reference) Input Pulse Level : 0.4 to 2.4V Input Rise and Fall Time : 5ns Input and Output reference Voltage : 1.5V Output Load (See right) : CL 1) = 100pF+ 1 TTL(70nsec) CL 1) = 30pF + 1 TTL(45ns/55ns) 1. Including scope and Jig capacitance 2. R 1 =3070Ω, R 2 =3150Ω 3. V TM =2.8V 4. CL = 5pF + 1 TTL (measurement with t LZ, t HZ, t OLZ, t OHZ, t WHZ ) CL 1) V TM 3) R 1 2) R 2 2) READ CYCLE (V cc =2.7 to 3.6V, Gnd = 0V, T A = -40 o C to +85 o C) Parameter Symbol 55ns Min Max Unit Read cycle time t RC 55 - ns Address access time t AA - 55 ns Chip select to output t CO1, t CO2-55 ns Output enable to valid output t OE - 35 ns UB, LB access time t BA 55 ns Chip select to low-z output t LZ1, t LZ2 5 - ns UB, LB enable to low-z output t BLZ 5 - ns Output enable to low-z output t OLZ 5 - ns Chip disable to high-z output t HZ1, t HZ ns UB, LB disable to how-z output t BHZ 0 20 ns Output disable to high-z output t OHZ 0 20 ns Output hold from address change t OH 10 - ns WRITE CYCLE (V cc =2.7 to 3.6V, Gnd = 0V, T A = -40 o C to +85 o C) Parameter Symbol Min 55ns Max Unit Write cycle time t WC 55 - ns Chip select to end of write t CW1, t CW ns Address setup time t AS 0 - ns Address valid to end of write t AW 45 - ns UB, LB valid to end of write t BW 45 - ns Write pulse width t WP 45 - ns Write recovery time t WR 0 - ns Write to ouput high-z t WHZ 0 20 ns Data to write time overlap t DW 25 ns Data hold from write time t DH 0 - ns End write to output low-z t OW 5 - ns 5

6 TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=V IL,=WE=V IH, UB or/and LB=V IL ) Address t RC t OH t AA Data Out Previous Data Valid Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE = V IH ) Address t RC t AA t OH CS1 t CO1,2 UB,LB t BA t HZ1,2 OE t OE t BHZ Data Out t OLZ Data Valid t OHZ t BLZ t LZ1,2 NOTES (READ CYCLE) 1. t HZ1,2 and t OHZ are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, t HZ1,2 (Max.) is less than t LZ1,2 (Min.) both for a given device and from device to device interconnection. 6

7 TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) Address t WC t CW1,2 (2) t WR (4) CS1 UB,LB t AW t BW t WP (1) WE t AS (3) t DW t DH Data in Data Valid t WHZ t OW Data out Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled) Address t WC t AS (3) t CW1 (2) t WR (4) CS1 UB,LB t AW t BW t WP (1) WE Data in t DW Data Valid t DH Data out 7

8 TIMING WAVEFORM OF WRITE CYCLE(3) ( Controlled) Address t WC CS1 t WR (4) t AS (3) t CW2 (2) t AW t WP (1) WE t DW t DH Data in Data Valid Data out 8

9 TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled) Address t WC CS1 t CW1,2 (2) t WR (4) UB,LB t AW t BW t AS (3) t WP (1) WE t DW t DH Data in Data Valid Data out NOTES (WRITE CYCLE) 1. A write occurs during the overlap(t WP ) of low CS1, a high and low WE. A write begins at the latest transition among CS1 goes low, goes high and WE goes low. A write ends at the earliest transition among CS1 goes high, goes low and WE goes high. The t WP is measured from the beginning of write to the end of write. 2. t CW is measured from the CS1 going low or going high to end of write. 3. t AS is measured from the address valid to the beginning of write. 4. t WR is measured from the end or write to the address change. t WR applied in case a write ends as CS1 or WE going high or going low. 9

10 EM681FV16B Family Low Power, 512Kx16 SRAM AUGUST 2010 DATA RETENTION CHARACTERISTICS Parameter Symbol Test Condition Min Typ Max Unit V CC for Data Retention V DR I SB1 Test Condition (Chip Disabled) 1) V Data Retention Current I DR V CC =1.5V, I SB1 Test Condition (Chip Disabled) 1) μa Chip Deselect to Data Retention Time t SDR See data retention wave form Operation Recovery Time t RDR t RC - - NOTES 1. See the I SB1 measurement condition of datasheet page 4. ns DATA RETENTION WAVE FORM t SDR Data Retention Mode t RDR V cc 2.7V 2.2V V DR CS1, LB / UB GND CS1 > Vcc-0.2V V cc 2.7V t SDR Data Retention Mode t RDR V DR 0.4V < 0.2V GND 10

11 PACKAGE DIMENSION 48 Ball Fine Pitch BGA (0.75mm ball pitch) Unit: millimeters Top View B Bottom View B B1 0.5 A1 index Mark A #A1 C B C D E C1 C C1/2 F G H B/2 Side View 0.26 E2 D Detail A E E1 C Min Typ Max 0.79Typ Typ. A Y A B B C C D E E NOTES. 1. Bump counts : 48(8row x 6column) 2. Bump pitch : (x,y)=(0.75x0.75) (typ.) 3. All tolerence are +/ unless otherwise specified. 4. Typ : Typical 5. Y is coplanarity : 0.08(Max) E Y

12 ORDERING INFORMATION VCC Speed Alliance Organization Package Operating Temp Range ns AS6C8016A -55ZIN 512K x V 44pin TSOP II Industrial ~ -40 C - 85 C 55 AS6C8016A -55BIN 512K x V 48ball FBGA Industrial ~ -40 C - 85 C 55 PART NUMBERING SYSTEM AS6C X X N Device Number Package Option Temperature Range N = Lead Free low power 80 = 8M Access Z - 44pin TSOP I = Industrial RoHS SRAM prefix 16 = x16 Time B = 48ball TFBGA (-40 to + 85 C) compliant part EM 1. Memory Component 8. Version Blank Mother die 2. Device Type A nd generation Low Power SRAM B rd generation STRAM C th generation C CellularRAM D th generation E th generation 3. Density F th generation M G th generation M M 9. Package M Blank KGD, FBGA M S stsop M T TSOP M U TSOP M V SOP 4. Option 10. Speed ns 5. Technology ns F Full CMOS ns ns 6. Operating Voltage ns T V ns V V U V 11. Power S V LL Low Low Power R V LF Low Low Power(Pb-free & Green) P V L Low Power S Standard Power 7. Organization X8 bit X16 bit X32 bit MEMORY FUNCTION GUIDE X XX XXX XX XX -XXXX AUGUST 2010 ORDERING INFORMATION Alliance Organization VCC Range Package Operating Temp Speed ns -55 BIN 1024K x V 48 FPBGA Industrial ~ -40 C - 85 C 55 PART NUMBERING SYSTEM AS6C X X N Low power SRAM prefix Device Number Package Option Temperature Range 16 = 16M Access I = Industrial 16 = x16 Time B = 48ball FPBGA (-40 to + 85 C) N = Lead Free RoHS compliant part Alliance Memory, Inc 5 1 Taylor Way, San Carlos, CA 94070, USA Phone: Fax: Copyright Alliance Memory All Rights Reserved Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks ofalliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to thisdocument and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The datacontained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at anytime, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information inthis product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide,any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of anyproduct described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability orwarranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to inalliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance'sTerms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights,trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components inlife-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion ofalliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against allclaims arising from such use Dual CS ns Single CS ns 12

512K X 16 BIT LOW POWER CMOS SRAM

512K X 16 BIT LOW POWER CMOS SRAM FEATURES Process Technology : 0.15μm Full CMOS Organization : 512K x 16 bit Power Supply Voltage : 2.7V ~ 3.6V Low Data Retention Voltage : 1.5V(Min.) Three state output and TTL Compatible Package Type