ECE 2300 Digital Logic & Computer Organization. Pipelined Microprocessor

Transcription

1 ECE 2300 Digital ogic & Computer Organization Spring 2018 Pipelined Microprocessor ecture 17: 1

2 nnouncements Prelab 5(b) deadline is on Friday Prelim 2: Tues pril 17, 7:30-9:00pm, PH 101 Coverage: ectures 8~16 FSMs, timing analysis, binary arithmetic, memories, singlecycle microprocessor Supplementary notes on timing analysis posted on course web Closed book, closed notes, closed internet sample exam is posted on CMS Instructor OH moved from Thursday 4/12 to Monday 4/16, 4:00-5:30pm (one-time change) ecture 17: 2

3 Programmable Single-Cycle Processor PC Inst. RM DR S SB M MB FS MD D MW BS Decoder SE(OFF,0) RF D S SB DR D_in Data DataB SE M +2 dder 0 1 MB 0 1 MP F m F 0 V C Z N M_address Data_in 0 1 Z Z N N C V Data RM MW MP BS 0 1 MD Instruction RM holds the program to be run Decoder derives control word from the instruction ecture 17: 3

4 ECE-2300 Instruction Set D ecture 17: 4

5 Instruction Set rchitecture (IS) The IS describes a set of instructions supported by a family of machines The IS specification tells hardware and software (compiler and operating system) developers Instruction formats Operation of each instruction Ways to form memory addresses Data formats ots of other Examples: x86, RM, MIPS, POWER, SPRC, RISC-V ecture 17: 5

6 Steps in Instruction Execution Instruction Fetch (IF) Fetch instruction; pdate PC Instruction Decode (ID) Decode instruction; Read register file Execute (EX) Perform operation Memory (MEM) Perform memory operation Write Back (WB) Put result into register file Clock period is limited by the longest path Suppose each step takes 1ns, clock period is 5ns ecture 17: 6

7 Pipelining: Basic Idea IF ID EX MEM WB IF/ID ID/EX EX/MEM MEM/WB Overlap instruction execution by performing each step in successive clock cycles ecture 17: 7

8 Pipelining: Overlapped Instructions Single-cycle execution CC1 IF-ID-EX-MEM-WB CC2 IF-ID-EX-MEM-WB Pipelined execution Instruction 1 Instruction 2 Instruction 3 Instruction 4 Instruction 5 CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 IF ID MEM WB IF ID MEM WB IF ID MEM WB IF ID MEM WB IF ID MEM WB ecture 17: 8

9 Pipelining: Performance Faster clock frequency than single cycle processor Each instruction takes 5 cycles verage number of cycles per instruction (CPI) ~1 instruction completed every cycle (ideally) CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 Instruction 1 Instruction 2 Instruction 3 Instruction 4 Instruction 5 IF ID MEM WB IF ID MEM WB IF ID MEM WB IF ID MEM WB IF ID MEM WB ecture 17: 9

10 Instruction Fetch Stage M X PCJ P C PC +2 Inst RM IF/ID Fetch the instruction into IF/ID (based on current PC) oad PC+2 into PC Place PC+2 into IF/ID ecture 17: 10

11 Instruction Decode Stage C Control Signals M X PCJ P C +2 Inst RM Decoder dder D S SB DR RF V C Z N PC D_in SE IF/ID ID/EX Read source operands from RF into ID/EX Place SE(M) into ID/EX Place SE(M)+(PC+2) into ID/EX Place DR into ID/EX ecture 17: 11

12 Execute Stage C Control Signals M X PCJ P C PC +2 Inst RM Decoder dder D S SB DR RF D_in V C Z N F m F 0 M X V C Z N SE IF/ID ID/EX MB EX/MEM Perform operation and place result into EX/MEM Pass DataB from the RF to EX/MEM Pass DR to EX/MEM If taken branch, update PC (Is it too late?) ecture 17: 12

13 Memory Stage C Control Signals M X PCJ P C PC +2 Inst RM Decoder dder D S SB DR RF D_in V C Z N F m F 0 M X V C Z N Data RM D_IN MW M X MD SE IF/ID ID/EX MB EX/MEM MEM/WB Store: Write DataB into RM oad: Read data from RM into MEM/WB operation: pass result from EX/MEM to MEM/WB Pass DR to MEM/WB ecture 17: 13

14 Writeback Stage C Control Signals M X PCJ P C PC +2 Inst RM Decoder dder D S SB DR RF D_in V C Z N F m F 0 M X V C Z N Data RM D_IN MW M X MD SE IF/ID ID/EX MB EX/MEM MEM/WB oad or operation: Write register file ecture 17: 14

15 Pipelined Microprocessor C Control Signals M X PCJ P C PC +2 Inst RM Decoder dder D S SB DR RF D_in V C Z N F m F 0 M X V C Z N Data RM D_IN MW M X MD SE IF/ID ID/EX MB EX/MEM MEM/WB ecture 17: 15

16 bstract Representation IF/ID ID/EX EX/MEM MEM/WB ecture 17: 16

17 Example Instruction Sequence DD R1,R2,R3 OR R4,R4,R3 SB R5,R2,R3 ND R6,R6,R2 DDI R7,R7,3 ecture 17: 17

18 Example Instruction Sequence DD R1,R2,R3 OR R4,R4,R3 SB R5,R2,R3 ND R6,R6,R2 DDI R7,R7,3 DD R1,R2,R3 ecture 17: 18

19 Example Instruction Sequence DD R1,R2,R3 OR R4,R4,R3 SB R5,R2,R3 ND R6,R6,R2 DDI R7,R7,3 OR R4,R4,R3 DD R1,R2,R3 ecture 17: 19

20 Example Instruction Sequence DD R1,R2,R3 OR R4,R4,R3 SB R5,R2,R3 ND R6,R6,R2 DDI R7,R7,3 SB R5,R2,R3 OR R4,R4,R3 DD R1,R2,R3 ecture 17: 20

21 Example Instruction Sequence DD R1,R2,R3 OR R4,R4,R3 SB R5,R2,R3 ND R6,R6,R2 DDI R7,R7,3 ND R6,R6,R2 SB R5,R2,R3 OR R4,R4,R3 DD R1,R2,R3 ecture 17: 21

22 Example Instruction Sequence DD R1,R2,R3 OR R4,R4,R3 SB R5,R2,R3 ND R6,R6,R2 DDI R7,R7,3 DDI R7,R7,3 ND R6,R6,R2 SB R5,R2,R3 OR R4,R4,R3 DD R1,R2,R3 ecture 17: 22

23 Example Instruction Sequence DD R1,R2,R3 OR R4,R4,R3 SB R5,R2,R3 ND R6,R6,R2 DDI R7,R7,3 DDI R7,R7,3 ND R6,R6,R2 SB R5,R2,R3 OR R4,R4,R3 ecture 17: 23

24 Example Instruction Sequence DD R1,R2,R3 OR R4,R4,R3 SB R5,R2,R3 ND R6,R6,R2 DDI R7,R7,3 DDI R7,R7,3 ND R6,R6,R2 SB R5,R2,R3 ecture 17: 24

25 Example Instruction Sequence CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 DD R1,R2,R3 OR R4,R4,R3 SB R5,R2,R3 ND R6,R6,R2 DDI R7,R7,3 ecture 17: 25

26 What bout This Sequence? CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 DD R1,R2,R3 OR R4,R1,R3 SB R5,R2,R1 ND R6,R1,R2 DDI R7,R7,3 The OR, SB, and ND instructions are data dependent on the DD instruction ecture 17: 26

27 Data Hazard Occurs when a register is read before the write back of a value to that register DD R1,R2,R3 OR R4,R1,R3 SB R5,R2,R1 ND R6,R1,R2 IF ID MEM WB IF ID MEM WB IF ID MEM WB IF ID MEM WB What should happen The 1st instruction calculates a new value for R1 The 2nd, 3rd, and 4th instructions use this new value What actually happens The 2nd, 3rd, and 4th instructions read the old value of R1 The first instruction then writes the new value into R1 ecture 17: 27

28 Solution 1: SW (compiler) Inserts NOPs CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 DD R1,R2,R3 NOP NOP NOP OR R4,R1,R3 ecture 17: 28

29 Solution 2: HW Stalls the Pipeline CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 DD R1,R2,R3 OR R4,R1,R3 bubble bubble bubble SB R5,R2,R1 ND R6,R1,R2 DDI R7,R7,3 The pipeline is stalled for three cycles ecture 17: 29

30 Identify all data hazards in the following instruction sequences by circling each source register that is read before the updated value is written back DD R1, R2, R3 NOP DDI R2, R1, 1 SB R3, R1, R2 SB R4, R3, R1 Example: Data Hazards ecture 17: 30

31 H&H Before Next Class Next Time More Pipelined Microprocessor ecture 17: 31