Background Statement for SEMI Draft Document 5485 NEW STANDARD: GUIDE FOR INCOMING/OUTGOING QUALITY CONTROL AND TESTING FLOWFOR 3DS-IC PRODUCTS

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1 Background Statement for SEMI Draft Document 5485 NEW STANDARD: GUIDE FOR INCOMING/OUTGOING QUALITY CONTROL AND TESTING FLOWFOR 3DS-IC PRODUCTS tice: This background statement is not part of the balloted item. It is provided solely to assist the recipient in reaching an informed decision based on the rationale of the activity that preceded the creation of this Document. tice: Recipients of this Document are invited to submit, with their comments, notification of any relevant patented technology or copyrighted items of which they are aware and to provide supporting documentation. In this context, patented technology is defined as technology for which a patent has issued or has been applied for. In the latter case, only publicly available information on the contents of the patent application is to be provided. Background SEMI Draft Document 5485 was developed by the 3DS-IC Testing Task Force to define the common criteria for incoming quality control () and outgoing quality control () of OSATs (outsourced sub-assembly and test providers)and the generic testing flows for different 3DS-IC products to expedite the progress of 3DS-IC testing. Review and Adjudication Information Task Force Review Committee Adjudication Group: 3DS-IC Testing Task Force Taiwan 3DS-IC TC Chapter Date: TBD Jan 15, 2015 Time & Time zone: TBD / Taiwan (GMT+8) 13:30 15:30 / Taiwan (GMT+8) Location: TBD SEMI Taiwan Office City, State/Country: Hsinchu, Taiwan Hsinchu, Taiwan Leader(s): M.C. Tsai (KYEC) W.S. Chu(ASE) Li-Heng Lee(ITRI) Tzu-Kun Ku (ITRI) Wendy Chen (King Yuan Electronics) Roger Hwang(ASE) Standards Staff: Andy Tuan (SEMI Taiwan) /atuan@semi.org Andy Tuan (SEMI Taiwan) /atuan@semi.org This meeting s details are subject to change, and additional review sessions may be scheduled if necessary. Contact Standards staff for confirmation. Telephone and web information will be distributed to interested parties as the meeting date approaches. If you will not be able to attend these meetings in person but would like to participate by telephone/web, please contact Standards staff. Check on calendar of event for the latest meeting schedule. If you need further assistance, or have questions, please do not hesitate to contact the 3DS-IC Testing Task Force: Li-Heng Lee, lihenglee@itri.org.tw

2 SEMI Draft Document 5485 NEW STANDARD: GUIDE FOR INCOMING/OUTGOING QUALITY CONTROL AND TESTING FLOW FOR 3DS-IC PRODUCTS 1 Purpose 1.1 To ensure consistent yield control of 3DS-IC products, common criteria for and of OSATs are needed. The generic testing flows for different 3DS-IC products also be defined in this document will expedite the progress of 3DS-IC testing. 2 Scope 2.1 This guide will define the criteria of and of OSATs, such as appearance, discolor, missing ball or crack etc. after stacking and thinning, etc., to clarify the manufacturer s responsibilities and to improve product yield. This guide will also define the generic testing flows for different 3DS-IC products, such as chip on chip (CoC), chip on substrate (CoS), chip on wafer(cow), stacked chip on substrate (SCoS), wafer on wafer (WoW), etc., to help accelerate the progress of 3DS-IC testing. 3 Limitations 3.1 This document does not specify details of the testing procedures. 4 Referenced Standards and Documents 4.1 SEMI Standards and Safety Guidelines SEMI M59 Terminology for Silicon Technology NOTICE: Unless otherwise indicated, all documents cited shall be the latest published versions. 5 Terminology 5.1 Abbreviations and Acronyms AOI Automatic Optical Inspection CoC Chip on Chip CoS Chip on Substrate CoW Chip on Wafer Incoming Quality Control OM Optical Microscopy Outgoing Quality Control OSAT Outsourced Sub-Assembly and Test SCoS Stacked Chip on Substrate WoW Wafer on Wafer 6 3DS-IC and 6.1 The guide is applied for the and of OSAT 3DS-IC manufacturing chains where the products, especially semi-finished goods, could be moved around among different sites. Some examples are named below. 6.2 After stacking, the stacked chips, i.e. CoC chips, could be sent out to an assembly house for packaging. 6.3 The wafers or substrates with chips stacked on top of them could be sent out to an assembly house for die saw and packaging The stacked wafers, i.e. WoW, could be sent out to an assembly house for die saw and packaging. Page 1

3 Chips or Wafers/Substrates Stacked Chips or Stacked Wafers/Substrates Site 1: wafer fabrication Site 2: 3D Stacking Site 3: Figure 1 The and Are Required In The 3DS-IC Manufacturing Flow Where The Product Is In The Form Of Semi-Finished Good And A Site To Site Transfer Occurs 7 Incoming Quality Control 7.1 This section defines the criteria of 3DS-IC products. The 3DS-IC product, no matter stacked chips or wafers, and the documents attached to describe this product are examined separately in the process. 7.2 Review of attached documents. The items listed below would be checked from the box label, flow card, and map information which attached with the product to ensure the right product is received Device number Lot number Wafer pieces Chip quantity Wafer size Mask code Wafer thickness Wafer identification Flat direction Wafer type: unbound or bounded, single or double side patterned wafer, e.g. interposer Chip type: single chip or stacked chip Pad material: Al, Au etc Pad structure: bump, pillar etc Summary report including AOI data 7.3 Review of product. The following inspections would be performed sequentially to ensure the good product is received Eye inspection. Use eyes to check if any scratch, chipping, broken, etc., in the product Optical microscopy (OM) inspection. Use OM to check if any discoloration of pad, probing mark abnormal, scratch, etc., in the product. Page 2

4 8 Outgoing Quality Control 8.1 This section defines the criteria of 3DS-ICsemi-finished goods, such as stacked chips for further stacking or final molding. The 3DS-IC product, no matter stacked chips or wafers, and the documents attached to describe this product are examined separately in the process. 8.2 Review of product and summary report. The review of the out-going goods should include the inspections of the following defects listed below and summarized in the report Check mechanical and structural defects, such as scratch, chipping, broken etc. in the product Check process defects such as missing ball, bridging, abnormal probing mark etc. in the product Check pad contamination, silicon residue in the product Ink inspection. Check if any ink mark in the product is existing and intact. 8.3 Review of attached documents. The items listed below would be checked sequentially to ensure the right product is shipped Box label. Check the product related information such as device number, lot number, and wafer pieces etc., are consistent with that in the flow card Flow card. Confirm the product has finished all the testing steps and the product related information such as device number, lot number, and wafer pieces etc., are consistent with that in the box label Testing report(s). Check the testing report(s) surely accompanying the shipped product Product inspection summary reports. 8.4 Shipping product quantities. Confirm the shipping quantity of product is correct. 8.5 inspection. 9 Testing Flow 9.1 This section shows the brief testing flows for different 3DS-IC products. 9.2 CoC testing flow CoC stacking packaging Figure 2 The Testing Flow of CoC(Chip on Chip) Stacking Page 3

5 9.3 CoS testing flow CoS stacking package Figure 3 The Testing of CoS(Chip on Substrate) Stacking 9.4 CoW testing flow CoW stacking Wafer probing packaging Figure 4 The Testing Flow of CoW(Chip on Wafer) Stacking Page 4

6 9.5 SCoS testing flow Dicing and pick up known good chips CoC/CoW CoW stacking Wafer probing CoC stacking SCoS stacking packaging Dicing and pick up known good chips Figure 5 The Testing Flow of SCoS(Stacked Chip on Substrate) Stacking. 9.6 WoW testing flow WoW stacking WoW probing Dicing and pick up known good stacked chips packaging Figure 6 The Testing Flow of WoW (Wafer on Wafer) Stacking Page 5

NOTICE: (SEMI) makes no warranties or representations as to the suitability of the Standards and Safety Guidelines set forth herein for any particular application.

7 NOTICE: (SEMI) makes no warranties or representations as to the suitability of the Standards and Safety Guidelines set forth herein for any particular application. The determination of the suitability of the Standard or Safety Guideline is solely the responsibility of the user. Users are cautioned to refer to manufacturer s instructions, product labels, product data sheets, and other relevant literature, respecting any materials or equipment mentioned herein. Standards and Safety Guidelines are subject to change without notice. By publication of this Standard or Safety Guideline, SEMI takes no position respecting the validity of any patent rights or copyrights asserted in connection with any items mentioned in this Standard or Safety Guideline. Users of this Standard or Safety Guideline are expressly advised that determination of any such patent rights or copyrights, and the risk of infringement of such rights are entirely their own responsibility. Page 6

Background Statement for SEMI Draft Document 4806 New Standard: GUIDE TO DEFECTS FOUND ON MONOCRYSTALLINE SILICON CARBIDE SUBSTRATES

Background Statement for SEMI Draft Document 4806 New Standard: GUIDE TO DEFECTS FOUND ON MONOCRYSTALLINE SILICON CARBIDE SUBSTRATES NOTICE: This background statement is not part of the balloted item.