This document should be superseded by dimensional specification and technology-specific guidelines for circuit-quality wafers.

Transcription

1 Background Statement for SEMI Document 4624B (rev. 16) NEW STANDARD: SPECIFICATION FOR DEVELOPMENTAL 450 mm DIAMETER POLISHED SINGLE CRYSTAL SILICON WAFERS Note: This background statement is not part of the balloted item. It is provided solely to assist the recipient in reaching an informed decision based on the rationale of the activity that preceded the creation of this document. Note: Recipients of this document are invited to submit, with their comments, notification of any relevant patented technology or copyrighted items of which they are aware and to provide supporting documentation. In this context, patented technology is defined as technology for which a patent has issued or has been applied for. In the latter case, only publicly available information on the contents of the patent application is to be provided. Attached document specifies 450 mm diameter polished single crystal wafers intended for use in research and development of process and metrology equipment and fabrication processes required to manufacture high-density integrated circuits on 450 mm diameter single crystal silicon wafers. It can also be used to establish the techniques and metrology necessary to support a dimensional specification for 450 mm diameter circuit-quality (prime) wafers. This document should be superseded by dimensional specification and technology-specific guidelines for circuit-quality wafers. The detailed specifications for 450 mm wafers are organized in three categories to assist manufacturers in choosing the most cost effective wafers for a given application: Particle monitors, intended for use in evaluating the particle contamination added by a process tool. Lithography monitors, for development of lithographic and patterning equipment and processes. Other monitors, suitable for use in process and inspection equipment development (other than particle counting or lithography development). The developmental wafers dimensional requirement are identical to the 450 mm mechanical handling wafers, published in SEMI M74, except wafer diameter tolerance, that was tightened to ±0.1 mm, to better reflect wafer handling and some process equipment needs. When specifying the wafer edge profile the customers must select one of two options, a parameter based profile or a template based edge profile. The previous draft of this document, 4624A, was reviewed at SEMICON Japan A number of editorial clarifications were made, which are reflected in the present draft. In addition to these changes, some additional clarifying notes are added to Table 1 and a Related Information section is added to clarify the related equipment requirements for use with the edge profiles specified in this document. The results of this document will be reviewed at the Int l 450 mm Wafer TF and will be adjudicated by the NA Silicon Wafer committee during their meetings at NA Spring Meetings in March 29-30, 2010 in Santa Clara, CA. Please check for the latest meeting schedule.

2 SEMI Document 4624B NEW STANDARD: SPECIFICATION FOR DEVELOPMENTAL 450 mm DIAMETER POLISHED SINGLE CRYSTAL SILICON WAFERS 1 Purpose 1.1 The developmental wafers covered by this specification are intended for use in research and development of process and metrology equipment and fabrication processes required for manufacturing high-density integrated circuits on 450 mm diameter single crystal silicon wafers. They can also be used to establish the techniques and metrology necessary to support a dimensional specification for 450 mm diameter circuit-quality (prime) wafers. 2 Scope 2.1 This specification covers dimensional and crystallographic orientation requirements for 450 mm diameter, polished single crystal silicon wafers needed in development. This document should be superseded by dimensional specification and technology-specific guidelines for circuit-quality wafers. 2.2 A complete purchase specification requires that additional physical properties be specified along with test methods for determining their magnitude. If a test instrument is not available, the acceptance criteria should be agreed upon between supplier and customer. 2.3 This specification also contains guidance to assist equipment manufacturers and others to specify wafers for use in developing selected process equipment and unit processes. 2.4 The specification for 450 mm diameter mechanical handling wafers used in development of 450 mm semiconductor equipment such as 450 mm wafers carriers, load ports, Automated Materials Handling System (AMHS), and robotics has already been published as SEMI M This specification is not intended to be a product wafer specification. 2.6 For referee purposes, SI (System International, commonly called metric) units shall be used. NOTICE: This standard does not purport to address safety issues, if any, associated with its use. It is the responsibility of the users of this standard to establish appropriate safety and health practices and determine the applicability of regulatory or other limitations prior to use. 3 Referenced Standards and Documents 3.1 SEMI Standards SEMI E45 Test Method for the Determination of Inorganic Contamination from Mini Environments Using Vapor Phase Decomposition-Total Reflection X-ray Spectroscopy (VPD/TXRF), VPD-Atomic Absorption Spectroscopy (VPD/AAS), or Inductively Couples Plasma-Mass Spectroscopy (VPD/ICP-MS) SEMI M1 Specifications for Polished Single Crystal Silicon Wafers SEMI M12 Specification for Serial Alphanumeric Marking of the Front Surface of Wafers SEMI M13 Specification for Alphanumeric Marking of Silicon Wafers SEMI M20 Practice for Establishing a Wafer Coordinate System SEMI M33 Test Method for the Determination of Residual Surface Contamination on Silicon Wafers by Means of Total Reflection X-Ray Fluorescence Spectroscopy (TXRF) SEMI M43 Guide for Reporting Wafer Nanotopography. SEMI M49 Guide for Specifying Geometry Systems Equipment forsilicon Wafers for the 130 nm to 22 nm Technology Generations. SEMI M52 Guide for Specifying Scanning Surface Inspection Systems for Silicon Wafers for the 130 nm, 90 nm, 65 nm, and 45 nm Technology Generations Page 1 Doc. 4624B SEMI

3 SEMI M53 Practice for Calibrating Scanning Surface Inspection Systems Using Certified Depositions of Monodisperse Reference Spheres on Unpatterned Semiconductor Wafer Surfaces SEMI M58 Test Method for Evaluating DMA-Based Particle Deposition Systems and Processes SEMI M59 Terminology for Silicon Technology. SEMI M67 Practice for Determining Wafer Near-Edge Geometry from a Measured Thickness Data Array Using the ESFQR, ESFQD and ESBIR Metrics SEMI M68 Practice for Determining Wafer Near-Edge Geometry from a Measured Height Data Array Using a Curvature Metric, ZDD SEMI M70 Practice for Determining Wafer-Near-Edge Geometry Using Partial Wafer Site Flatness SEMI M73 Test method for Extracting Relevant Characteristics from Measured Wafers Edge Profiles SEMI M74 Specifications for 450 mm Diameter Mechanical Handling Polished Wafers SEMI MF26 Test Methods for Determining the Orientation of a Semiconductive Single Crystal SEMI MF42 Test Methods for Conductivity Type of Extrinsic Semiconducting Materials SEMI MF81 Test Method for Measuring Radial Resistivity Variation on Silicon Wafers SEMI MF523 Practice for Unaided Visual Inspection of Polished Silicon Wafer Surfaces SEMI MF533 Test Method for Thickness and Thickness Variation of Silicon Wafers SEMI MF534 Test Method for Bow of Silicon Wafers SEMI MF657 Test Method for Measuring Warp and Total Thickness Variation on Silicon Wafers by Noncontact Scanning SEMI MF673 Test Methods for Measuring Resistivity of Semiconductor Wafers or Sheet Resistance of Semiconductor Films with a Noncontact Eddy-Current Gage SEMI MF951 Test Method for Determination of Radial Interstitial Oxygen Variation in Silicon Wafers SEMI MF1049 Practice for Shallow Pit Detection on Silicon Wafers SEMI MF1152 Test Method for Dimensions of Notches on Silicon Wafers SEMI MF1188 Test Method for Interstitial Atomic Oxygen Content of Silicon by Infrared AbsorptionWith Short Baseline. SEMI MF1366 Test Method for Measuring Oxygen Concentration in Heavily Doped Silicon Substrates by Secondary Ion Mass Spectrometry SEMI MF1389 Test Method for Photoluminescence Analysis of Single Crystal Silicon for III-V Impurities. SEMI MF1390 Test Method for Measuring Warp on Silicon Wafers by Automated Noncontact Scanning SEMI MF1451 Test Method for Measuring Sori on Silicon Wafers by Automated Noncontact Scanning SEMI MF1530 Test Method for Measuring Flatness, Thickness, and Thickness Variation on Silicon Wafers by Automated Noncontact Scanning SEMI MF1617 Test Method for Measuring Surface Sodium, Aluminum, and Potassium on Silicon and Epi Substrates by Secondary Ion Mass Spectrometry SEMI MF1619 Test Method for Measurement of Interstitial Oxygen Content of Silicon Wafers by Infrared Absorption Spectroscopy with p-polarized Radiation Incident at the Brewster Angle SEMI MF1727 Practice for Detection of Oxidation Induced Defects in Polished Silicon Wafers SEMI MF1809 Guide for Selection and Use for Etching Solutions to Delineate Structural Defects in Silicon SEMI MF1810 Test Method for Counting Preferentially Etched or Decorated Surface Defects in Silicon Wafers. Page 2 Doc. 4624B SEMI

4 SEMI MF2074 Guide for Measuring Diameter of Silicon and Other Semiconductor Wafers SEMI T3 Specifications for Wafer Box Labels SEMI T7 Specification for Back Surface Marking of Double-Side Polished Wafers with a Two-Dimensional Matrix Code Symbol 3.2 ANSI Standard 1 ANSI/ASQC Z1.4 Sampling Procedures and Tables for Inspection by Attributes 3.3 ASTM Standard 2 ASTM E122 Standard Practice for Choice of Sample Size to Estimate the Average Quality of a Lot or Process 3.4 ISO Standard 3 ISO Surface Chemical Analysis Chemical methods for collection of elements from the surface of silicon-wafer working reference materials and their determination by total-reflection X-ray fluorescence (TXRF) spectroscopy 4 Terminology 4.1 Terms and acronyms associated with silicon wafers and silicon technology are listed and defined in SEMI M59. 5 Wafer Ordering Information 5.1 Purchase orders for silicon wafers furnished to this specification shall include the following items. Values for these items are given in Tables 1 and Developmental wafer monitor category Crystal Growth Method (see 6.4) Conductivity Type and Dopant Resistivity or Resistivity Range Wafer edge profile type requested (see 6.5.7) Lot Acceptance Procedures (see 7) Test methods for specified attributes (see 8) Certification (if required) (see 9) Packing and Package Labeling (see 10). 5.2 Optional Criteria The following items may also be specified in addition to those listed above if they are considered to be necessary for the application for which the wafers are to be employed (see Table 1) Wafer identification mark symbol or symbols Wafer dimensional characteristics requirements As specified in Appendix 1 of SEMI M Particulate contamination (localized light scatterer) requirements (see 6.6.2) Surface defect requirements, including surface metal contamination (see 6.6.3). 1 American National Standards Institute, Headquarters: 1819 L Street, NW, Washington, DC 20036, USA. Telephone: ; Fax: New York Office: 11 West 42nd Street, New York, NY 10036, USA. Telephone: ; Fax: ; 2 American Society for Testing and Materials, 100 Barr Harbor Drive, West Conshohocken, Pennsylvania , USA. Telephone: ; Fax: ; 3 International Organization for Standardization, ISO Central Secretariat, 1 rue de Varembé, Case postale 56, CH-1211 Geneva 20, Switzerland. Telephone: ; Fax: ; Page 3 Doc. 4624B SEMI

5 5.3 Additional Criteria Any additional criteria considered to be necessary for the application for which the wafers are to be employed may also be specified, as agreed between supplier and customer (see Table 1). 6 Requirements 6.1 Table 1 and Table 2 contain detailed specifications for 450 mm diameter wafers intended for use in development. The requirements are organized by wafer categories and edge profile specification method. Table 1 details wafer required properties by category to assist manufacturers in choosing the most cost effective wafers for a given application. Table 2 details the different methods for specifying the edge profile requirements. 6.2 Wafer Categories Particle monitors Wafers intended for use in evaluating the particulate contamination added by a process tool must have controlled front and back surface defect properties. Consequently, specifications are provided for front surface localized light scatterers (LLSs), edge chips, and scratches on both surfaces. If desired, a specification for back surface LLSs can be negotiated between supplier and purchaser Lithography monitors For development of lithographic and patterning equipment and processes, both surface flatness and surface defects must be carefully controlled Other monitors This column repeats the basic requirements for developmental wafers. Wafers in this category are not intended for use in particle counting or litography and patterning. These wafers are suitable for use in process and inspection equipment development. When used for furnace and thermal processes development wafer back side, edge surface finish and oxygen content are critical issues in connection with the introduction of slip during high temperature processing. Bulk iron, oxidation induced stacking faults, and bulk microdefects all can influence wafer performance in thermal processing and should be controlled for critical tests; appropriate specification levels should be negotiated between supplier and purchaser. Table 1 General Specification for Developmental 450 mm Diameter Polished Single Crystal Silicon Wafers Item #1 2-1 General Characteristics Particle Wafer Category Lithography Growth Method Cz or MCz Other Measurement Method Crystal Orientation (100) MF26 (x-ray) Conductivity Type p p or n M1, MF Dopant B B or P M1, MF FQA radius #2 223 mm Wafer surface On-orientation ± MF26 (x-ray) declination in respect to crystal orientation 2-2 Electrical Characteristics Resistivity #2 M1, MF673 p type wafers Ω cm Ω cm n type wafers Not specified 1-20 Ω cm M1, MF Radial Resistivity Variation (RRG) #4 <10% M1, MF Chemical Characteristics Oxygen Concentration Not specified Customer Specified M1, MF1188, MF Radial Oxygen Not specified 10% MF951 Page 4 Doc. 4624B SEMI

6 Item #1 Variation #5 2-4 Structural Characteristics Dislocation Etch Pit Density Particle Wafer Category Lithography 10/cm 2 Other Measurement Method M1, MF Slip None MF Twin Boundary None MF Swirl None MF Wafer Preparation Characteristics Wafer ID Marking #6 SEMI T7 T Edge surface conditions Polished # Back surface condition Polished #7 2-6 Dimensional Characteristics Diameter 450 ± 0.1 mm M1, MF Notch dimensions #8 Depth Angle mm Orientation of Notch axis <110> ± 1 0 MF Edge profile Customer Specified #9 M1, M Thickness #3 925 ± 25 μm MF GBIR, less than 10 μm 3 μm 10 μm MF Bow, max Customer Specified MF Warp, max 100 μm 50 μm 100 μm MF Flatness/SFQR (26x8mm 2 site size) Nanotopography Not specified Customer specified Near Edge Geometry Not specified Customer specified 2-7 Front Surface Chemistry Surface Metal Contamination Not specified 42 nm Not specified MF1530 Not specified Not specified M43 M67, M68, M Sodium per cm 2 MF1617, E45 ISO Aluminum per cm 2 MF1617, E45 ISO Potassium per cm 2 M33, MF Chromium per cm 2 M33, MF Iron per cm 2 M33, MF Nickel per cm 2 M33, MF Copper per cm 2 M33, MF1617 Page 5 Doc. 4624B SEMI

7 Item #1 Particle Wafer Category Lithography Other Measurement Method Zinc per cm 2 M33, MF Calcium per cm 2 M33, MF Front Surface Inspection Characteristics Scratches None M1, MF Pits (COP) Customer Specified Haze Customer Specified Not specified Not specified M1, MF523 M1, MF Localized Light 0.16 per cm per cm 2 M1 Scatterers μm 250 per wafer 500 per wafer (SSIS) Edge Chips None M1, MF Back Surface Inspection Characteristics # Edge Chips None M1, MF Scratches - Macro None M1, MF Scratches - Micro Customer Specified M1, MF Localized Light Customer Specified M1, MF523 Scatterers #1 Numbers in the left hand column are not necessarily continuous because they follow the numbers in the polished wafer specification order form, Table 1 of SEMI M1. #2 This FQA radius results in a nominal edge exclusion of 2 mm; the radius of the wafer is to be center referenced. #3 Measured at Center Point. #4 Measured between Center Point and a point on a radius 219 mm from the Center Point. #5 Measured between Center Point and a point on a radius 215 mm from the Center Point. #6 See Related Information 1 for optional alphanumeric marking. #7 Implies a surface condition and not a particular processing technique. #8 See Related Information 2 for discussion of inscribed fiducial mark wafer ( notch-free ). #9 Edge profile target is defined in Table 2, choose specification method A or B(see 6.4.7). #10 Back surface inspection characteristics are impacted by the type of wafer handling. So far no decision about back surface or edge handling in the bare wafer manufacturing has been made. 6.3 Material and Manufacture The material shall consist of wafers cut from ingots grown by either the normal Czochralski or the magnetic Czochralski method, at the supplier s option. 6.4 Dimensions and Permissible Variations Wafers shall conform to the dimensions and dimensional tolerances as specified for the attributes listed in Table Shape Although the warp value specified in Table 1 is expected to be adequate for many developmental purposes, it is now recognized that warp, even with correction for gravitational sag, is not a suitable metric for specifying wafer shape for all applications. Processing may induce additional warp Sori is an attribute that may be specified as agreed between the supplier and the purchaser in lieu of warp. (see SEMI MF1451) Bow values will be specified by the customer, depending on his application requirements Flatness GBIR and SFQR are specified in Table 1. NT and ERO values shall meet customer requirements as specified in the purchase order. NOTE 1: This is a wafer specification. Equipment specifications may have tighter requirements Fiducial Mark A notch in conformance with the dimensions and tolerances as described in SEMI M Page 6 Doc. 4624B SEMI

8 NOTE 2: Customer preferring wafers without a notch, will have the option to use a fiducial mark inscribed on the wafer backside as discussed in Related Information Back Surface Finish The back surface shall be polished Edge Profile The edge profile shall conform to one of two sets of requirements listed in Table 2 at all points on the wafer periphery except the notch region. Customers may choose one of two methods of wafer edge profile specifications: Method A the edge profile is specified by the set of target parameters and their tolerances given in Table 2 (see SEMI M73) Method B the edge profile is specified by the target template, drawn from similar profile parameters and the template width given in Table 2 (see SEMI M1 Appendix 3) Edge Surface Finish The edge surface finish is specified to be polished, which is meant to imply a surface condition and not a particular processing technique Fixed Quality Area The central region of the wafer with a radius of 223 mm is designated as the fixed quality area (FQA). NOTE 3: In SEMI M1, the FQA is referenced to the edge of a wafer of nominal diameter by the nominal edge exclusion (see M1, Fig.1c). For 450 mm wafers, the equivalent nominal edge exclusion for the specified FQA radius is 2 mm. Measurement results acquired with edge-referenced coordinates must be handled appropriately when traslating to SEMI M20 coordinate space used in this specification. NOTE 4: It should also be noted that a larger FQA radius (smaller value of nominal edge exclusion) may be required for circuitquality 450 mm diameter wafers. Table 2 Edge Profile Specification for Developmental 450 mm Diameter Polished Single Crystal Silicon Wafers Edge Wafer Edge Type Specification Item Method A Method B Front edge width 350 ± 50 μm 350 μm Front bevel angle ± Front shoulder radius ± 42.5 μm μm Back shoulder radius ± 42.5 μm μm Back bevel angle ± Back edge width 350 ± 50 μm 350 μm Template Width Thickness #1 925 ± 25 μm 30 μm Measurement Method SEMI M73 SEMI M1 Appendix 3 #1 Thickness is not an edge specification but it is listed here for convenience. 6.5 Other requirements The wafers shall conform to the surface orientation and fiducial axis orientation requirements as specified in Table 1. NOTE 5: The angular surface orientation tolerance specified in Table 1 is sufficient for wafers intended for general use where channeling is to be avoided in ion implantation. For applications where maximum channeling along the [100] direction perpendicular to the (100) wafer surface plane is desired, the surface orientation tolerance must be tightened as discussed in 7.1 of SEMI M All 450 mm wafers shall be marked with a two-dimensional matrix code symbol on the back surface outside the fixed quality area as soon after slicing as practical in the manner specified in SEMI T7 in order to provide both identification of these wafers and traceability of each wafer, going back to the ingot from which it was cut. The back surface is identified as the wafer surface with the two-dimensional matrix code symbol. Page 7 Doc. 4624B SEMI

9 Optionally the user may specify an additional alpha-numeric back-surface mark as described in Related Information Particulate Contamination (Localized Light Scatterer or LLS) Requirements Particulate contamination requirements are specified in Table 1. Particle monitor wafers have tighter requirements than other monitor wafers Surface Defect Requirements including surface metal contamination levels, are specified in Table The wafers shall conform to such other physical characteristics listed in SEMI M1 as may be specified in the purchase order or contract. 7 Sampling 7.1 Unless other wise specified, ASTM Practice E 122 shall be used to define the sampling plan. When so specified, appropriate sample sizes shall be selected from each lot in accordance with ANSI/ASQC Z1.4. Each quality characteristic shall be assigned an acceptable quality level (AQL) or lot tolerance percent defective (LTPD) value in accordance with ANSI/ASQC Z1.4 definitions for critical, major, and minor classifications. If desired and so specified in the contract or order, each of these classifications may alternatively be assigned cumulative AQL or LTPD values. Inspection levels shall be agreed upon between the supplier and the purchaser. 8 Test Methods 8.1 Table 1 of SEMI M1 contains a listing of SEMI, ASTM, DIN, and JEIDA/JIS and ISO test methods that may apply to the testing of specified attributes of developmental 450 mm diameter silicon wafers. 9 Certification 9.1 Upon request of the purchaser in the contract or order, manufacturer s or supplier s certification that the material was manufactured and tested in accordance with this specification, together with a report of the test results, shall be furnished at the time of shipment. 9.2 In the interest of controlling inspection costs, the supplier and the purchaser may agree that the material shall be certified as capable of meeting certain requirements. In this context, capable of meeting shall signify that the supplier is not required to perform the appropriate tests as included in the purchase order or contract (see 8). However, if the purchaser performs the test and the material fails to meet the requirement, the material may be subject to rejection. 10 Packing and Package Labeling 10.1 Special packing requirements shall be subject to agreement between the supplier and the purchaser. Otherwise all wafers shall be handled, inspected, and packed in such a manner as to avoid chipping, scratches, and contamination and in accordance with the best industry practices to provide ample protection against damage during shipment Wafers supplied under this specification shall be identified by appropriately labeling the outside of each box or other container and each subdivision thereof in which it may be reasonably expected that the wafers will be stored prior to further processing. Wafer box labels shall include as a minimum the following information in accordance with SEMI T3: Customer Assigned Product Identification Number, Lot Number, Vendor Identification Code, Labeling Date, and Quantity The lot number shall provide access to information concerning the nominal diameter, conductivity type, dopant, orientation, resistivity range, and fabrication history of the particular wafers in that lot. Such information shall be retained on file at the manufacturer s facility for at least one month after that particular lot has been accepted by the purchaser, or for a longer time if so specified in the purchase order or contract. Page 8 Doc. 4624B SEMI

10 RELATED INFORMATION 1 ALPHANUMERIC IDENTIFICATION MARK FOR 450 mm DEVELOPMENTAL WAFER NOTICE: This related information is not an official part of SEMI Mxx and was derived from the International 450 mm Wafer Task Force. This related information was approved for publication by ballot on [tbd]. R1-1.1 As specified in Table 1 all 450 mm wafers have to be marked with a two-dimensional matrix code symbol on the back surface as defined by SEMI T7. R However, some customer may require an additional mark, especially during the process development stages. R This mark contains alphanumeric characters with: The same message characters as the SEMI T7 mark and appropriate checksum characters as defined by SEMI M12 and M13 and Character string as specified in SEMI M12 and M13. R The wafer identification marking positions and dimensions are described in Fig. R1-1 Wafer Back Surface A/N MARK T7 MARK Fiducial Axis 5.0 ± 0.1 from Fiducial Axis Outer Periphery of FQA All dimensions in millimeters unless otherwise indicated R ± ± 0.15 from data matrix code system reference point to wafer center A/N read direction A/N read direction Edge Exclusion Area Edge Profile Region R 225 Notch 8.22 ± ± ± 0.03 Wafer Periphery Reference point of SEMI T7 Mark Figure R1-1 T7 and Alphanumeric Identification Marking Positions and Dimensions Page 9 Doc. 4624B SEMI

11 RELATED INFORMATION 2 DISCUSSION ON INSCRIBED FIDUCIAL MARK FOR 450 mm DEVELOPMENTAL WAFER NOTICE: This related information is not an official part of SEMI Mxx and was derived from the International 450 mm Wafer Task Force. This related information was approved for publication by ballot on [tbd]. NOTICE: This fiducial mark specification option is intended for the customers who choose to use a notch free wafer. R2-1.1 The wafer notch is used for wafer alignment however it impacts the wafer symmetry and creates a stress area. Eliminating the notch will improve the wafer symmetry and eliminate the notch related stress but will require a different alignment method. R2-1.2 A fiducial mark, inscribed on the back of the wafer has been proposed as an alternative alignment method. A good mark needs to provide a clear signature, with good angular resolution, provide a robust signature for wafer theta alignment and be readable through all the process steps. R2-1.3 The exact dimensions, position and pattern of the fiducial mark have not been defined yet and will have to be addressed in future working group meetings. Page 10 Doc. 4624B SEMI

12 RELATED INFORMATION 3 EDGE PROFILE FOR 450 mm DEVELOPMENTAL WAFERS NOTICE: This related information is not an official part of SEMI Mxx and was derived from the International 450 mm Wafer Task Force. This related information was approved for publication by ballot on [tbd]. R3-1 The purpose of this drawing is to assist the equipment manufacturer with their mechanical design mm 0.1 mm 0.1 mm NOTE: The dimensions and tolerances are detailed in Table 2. Figure R3-1 Scale Drawing of the 450 mm Target Edge Profile Illustrating the Terms and Dimensions Used to Describe the Profile R3-2 It should be noted that the edge profile drawings will be addressed in future meetings in the appropriate committees in an effort to define a better drawing solution. NOTICE: SEMI makes no warranties or representations as to the suitability of the standard(s) set forth herein for any particular application. The determination of the suitability of the standard(s) is solely the responsibility of the user. Users are cautioned to refer to manufacturer s instructions, product labels, product data sheets, and other relevant literature respecting any materials or equipment mentioned herein. These standards are subject to change without notice. By publication of this standard, Semiconductor Equipment and Materials International (SEMI) takes no position respecting the validity of any patent rights or copyrights asserted in connection with any item mentioned in this standard. Users of this standard are expressly advised that determination of any such patent rights or copyrights, and the risk of infringement of such rights are entirely their own responsibility. Page 11 Doc. 4624B SEMI