High Performance High-K + Metal Gate Strain Enhanced Transistors on (110) Silicon Paul Packan, S. Cea*, H. Deshpande, T. Ghani, M. Giles*, O. Golonzka, M. Hattendorf, R. Kotlyar*, K. Kuhn, A. Murthy, P. Ranade, L. Shifren*, C. Weber* and K. Zawadzki Logic Technology Development, *Process Technology Modeling Intel Corporation IEDM 2008
Outline Transistor Scaling Stress Effects on Mobility Comparison of (100) and (110) Silicon Substrates Device Performance Summary IEDM 2008 2
Key Messages Record PMOS drive current of 1.2mA/um is presented for devices on (110) silicon substrates For short gate lengths, NMOS drive currents on (110) substrates are not degraded as much as believed by many in literature The fundamental physics behind these behaviors is understood IEDM 2008 3
Outline Transistor Scaling Stress Effects on Mobility Comparison of (100) and (110) Silicon Substrates Device Performance Summary IEDM 2008 4
Traditional Scaling Id= Cox/Le(Vg-Vt) Source Source Gate Gate Drain Drain Lmet @ 1 na/um Ioff 0.25 0.20 0.15 0.10 0.05 Gate Length 140 130 120 110 100 REXT Voltage Potential Contours 0.0 R EXT 90 0 50 100 150 200 250 Junction Depth (nm) Traditional device scaling requires all dimensions to scale to maintain performance and leakage Scaling junction depths and S/D areas is causing Rext increase IEDM 2008 5
Constant Leakage Scaling Id= Cox/Le(Vg-Vt) Doping Concentration 2.5E+20 2.0E+20 1.5E+20 1.0E+20 5.0E+19 0.0E+00 Solid Solubility Depth Doping 1992 1994 1996 1998 2000 2002 2004 Year 1400 1200 1000 800 600 400 200 0 Junction Depth Normalized Value 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 VT IDLIN 0.015 0.025 0.035 0.045 0.055 Gate Length IDSAT Junction scaling is slowing due to unacceptable resistance increases Scaling gate lengths at constant leakage requires increasing Vt which results in drive current reduction Traditional device scaling is losing steam IEDM 2008 6
Mobility Scaling Id= Cox/Le(Vg-Vt) Increasing mobility increases device performance without increasing leakage Reducing scattering mechanisms, applying stress and surface orientation all affect mobility Ge Conc. (%) 35 25 15 90nm 65nm 45nm Technology node 40 30 20 10 0 Gate-to-SiGe S/D (nm) 65 nm 45 nm IEDM 2008 7
Outline Transistor Scaling Stress Effects on Mobility Comparison of (100) and (110) Silicon Substrates Device Performance Summary IEDM 2008 8
Silicon Band Structure gap conduction band for electrons valence band for holes Electron hh Hole IEDM 2008 9
Stress and Band Structure k y (2 /a) 0.2 0.1 0-0.1 D B -0.2-0.2 Unstressed -0.1 0 0.1 k x (2 /a) A C 0.2 k y (2 /a) 0.2 0.1 0-0.1 D B -0.2-0.2 M.Giles, AVS 2006 Stressed A C -0.1 0 0.1 0.2 k x (2 /a) (001) surface 1GPa uniaxial stress [110] 1 MV/cm vertical field 30meV energy contours Compression lowers the energy of (C,D) Holes redistribute from (A,B) to (C,D) The effective mass is reduced IEDM 2008 10
Conduction Band Stress Response z Repopulation y y Scattering x [110] x Energy No stress XY Plane [110] uniaxial tensile [001] uniaxial compressive E Mobility gain comes from valley repopulation, valley warping, and scattering suppression M.Giles, AVS 2006 IEDM 2008 11
Stress Effects on Mobility 2.5 2.0 longitudinal stress transverse stress vertical stress 6.0 5.0 longitudinal stress transverse stress vertical stress Mobility Ratio 1.5 1.0 4.0 3.0 2.0 1 MV/cm 0.5 0.0 1 MV/cm Electrons -3000-1000 1000 3000 Stress MPa 1.0 0.0 Holes -3000-1000 1000 3000 Stress MPa Longitudinal tension and vertical compression increases electron mobility Longitudinal compression and vertical tension increases hole mobility Transverse tension increases both electron and hole mobility Hole mobility shows a greater sensitivity to stress for (100) IEDM 2008 12
Stress Methods Capping Layers Gate Induced Epitaxial Layers Contacts C. Auth, VLSI 2008 IEDM 2008 13
1000 VDD = 1.0V NMOS Stress Contact Stress Ioff(nA/ m) 100 +10% 10 Tensile Fill Control 1 0.70 0.90 1.10 1.30 Idsat(mA/ m) 1000 VDD = 1.0V Gate Stress Ioff (na/ m) 100 10 +5% Compressive Gate Control 1 0.9 1.1 1.3 1.5 Idsat (ma/ m) C. Auth, VLSI 2008 IEDM 2008 14
PMOS Stress SiGe Stress K.Mistry, 2004 VLSI IEDM 2008 15
Outline Transistor Scaling Stress Effects on Mobility Comparison of (100) and (110) Silicon Substrates Device Performance Summary IEDM 2008 16
Substrate Orientation (100) (110) [010] [001] [100] [100] [010] [001] calculated using MASTAR (http://www.itrs.net/models.html) IEDM 2008 17
PMOS Hole Occupation and Band Structure (100) (110) stressed unstressed ky <-110> ky <001> constant energy contours kx <110> kx <110> More dense contour lines show lower effective mass for (110) PMOS hole occupation of band structure shows a larger difference between unstressed and stressed devices for (100) IEDM 2008 18
Stress Response of Electron Mobility Mobility Ratio 2.5 2.0 1.5 1.0 0.5 0.0 longitudinal stress stress transverse stress transverse stress vertical stress vertical stress (100) Electrons -3000-1000 1000 3000 Stress MPa 4.0 6.0 3.5 5.0 3.0 4.0 2.5 2.0 3.0 1.5 2.0 1.0 0.5 1.0 longitudinal stress transverse longitudinal stress stress vertical transverse stress stress vertical stress (100) (110) Electrons Holes Mobility Ratio 0.0 0.0-3000 -3000-1000 -1000 1000 1000 3000 3000 Stress MPa Stress MPa Stress MPa Longitudinal tension improves (100) and (110) mobility Vertical and transverse stress show opposite dependencies Stress sensitivity is larger for (110) substrate orientation IEDM 2008 19
Stress Response of Hole Mobility Mobility Ratio 6.0 4.0 3.5 5.0 3.0 4.0 2.5 3.0 2.0 1.5 2.0 longitudinal stress longitudinal stress transverse stress vertical transverse stress stress vertical stress vertical stress Mobility Ratio 2.5 2.0 1.5 1.0 longitudinal stress transverse stress vertical stress (100) (110) 1.0 0.5 1.0 0.5 Electrons Holes Holes 0.0 0.0-3000 -1000 1000 3000-3000 -1000 1000 3000 Stress MPa Stress MPa Stress MPa MPa Longitudinal compression improves (100) and (110) mobility Vertical and transverse tension improves (100) and (110) mobility Stress sensitivity is larger for (100) substrate orientation IEDM 2008 20
Simulated Hole and Electron Mobility Hole Mobility (cm 2 /Vs) 340 290 240 190 140 90 40 (100) Mobility (110) Mobility 1.6x Hole 3.5x -3000-2000 -1000 0 <110> Stress (MPa) 3000 1.5x (100) Mobility (110) Mobility 2000 Electron 1000 <110> Stress (MPa) 2.5x 0 600 500 400 300 200 100 0 Electron Mobility (cm 2 /Vs) Hole mobility increases and electron mobility decreases for (110) substrates The difference in mobility depends on device stress IEDM 2008 21
Outline Transistor Scaling Stress Effects on Mobility Comparison of (100) and (110) Silicon Substrates Device Performance Summary IEDM 2008 22
45 nm Hi-K+Metal Gate Technology Based on Intel s 45 nm process technology High-k first, metal gate last process architecture 35nm gate length 160 nm contacted gate pitch 1.0 nm EOT High-k Dual workfunction metal gate electrodes 3 RD generation strained silicon K.Mistry IEDM 2007 IEDM 2008 23
(110) and (100) PMOS Idsat Ioff IOFF (A/um) (A/um) 1E-5 1E-6 1E-7 1E-8 1E-9 0.7 0.9 1.1 1.3 Idsat (ma/um) IDSAT (ma/um) 1.2 15% (110) (100) Record PMOS drive currents of 1.2 ma/um at 1.0V and 100nA/um Ioff are reported for (110) substrates The performance improvement is 15% for (110) substrates compared to (100) substrates IEDM 2008 24
PMOS (110)/(100) Idsat Improvement versus Stress PMOS % IDSAT improvement 50% experimental (110)/(100) data 40% (110)/(100) 30% 20% 10% 0% 0% 10% 20% 30% 40% Ge Fraction Under stress, the relative hole mobility between (110) and (100) substrates decreases due to the larger stress sensitivity of mobility on the (100) substrate Even under high stress, substantial performance improvement is seen IEDM 2008 25
(110) and (100) NMOS Idsat 1E-7 160nm Lgate 1E-5 35nm Lgate Ioff (A/um) 1E-8 1E-9 1E-10 40% 1E-11 0.2 0.4 0.6 Idsat IDSAT (ma/um) (110) (100) Ioff IOFF (A/um) 1E-6 1E-7 1E-8 1E-9 13% (110) (100) 0.8 1 1.2 1.4 1.6 Idsat IDSAT (ma/um) As channel lengths are decreased, NMOS performance loss on (110) substrates is reduced Why is the degradation reduced? IEDM 2008 26
Surface Confinement Effect [110] Bulk conduction m [110] =0.43m e (100) surface confinement (110) surface confinement Ground state [110] m [110] =0.19m e [110] m [110] =0.55m e Surface confinement changes ground state transport mass Separation depends on confinement field IEDM 2008 27
Local Electron Mobility Electron Density (/cm 3 ) 1e20 1e18 1e16 1e14 1e12 (100) inversion layer at center of channel Device Length 30nm 60nm 0.03 um 0.06 um 1e10 0 20 40 60 80 100 Distance from Surface (A) (110)/(100) mobility ratio 1 0.9 0.8 0.7 0.6 0.5 (a) source mid- Source Channel drain Drain tip/channel channel tip/channel Lgate 0.036 35nm 0.04 40nm 0.05 50nm 0.06 60nm LC LC Slice Location Location along along Device the Lgate k. p calculations for an unstressed device show the maximum degradation occurs near the middle of the channel As the channel lengths is decreases, the carrier confinement is reduced due to 2D short channel effects IEDM 2008 28
2D Effects on Valley Splitting Valley Splitting splitting due to Confinement Field field for Long in Long Channel Device Valley Splitting splitting Reduction reduced in due Short to 2D SCE for Short Channel Channel Device E o E 1 E 1 -E 2 =large E o E 1 E 1 -E 2 =reduced due E 2 to 2D short-channel effects E 2 Reduced carrier confinement in short channel devices due to 2D effects reduce the valley splitting This reduction results in reduced NMOS performance loss for (110) substrates IEDM 2008 29
Simulated 2D Effects Simulated NMOS and PMOS performance both with and without 2D effects The NMOS devices shows a large reduction in short channel degradation when 2D effects are included Due to high stress effects in the PMOS device, little change is seen by including the 2D effects. IEDM 2008 30
Narrow Width Stress Effects STI Expand Compress Gate Channel % IDSAT Loss 0% -2% -4% -6% -8% -10% NMOS (110)/(100) -12% -14% 0 0.25 0.5 0.75 1 Device Width (um) STI causes compressive transverse stress in the channel which increases at narrower device widths Transverse compression improves (110) and degrades (100) electron mobility NMOS performance for typical devices is only degraded by 5-8% IEDM 2008 31
Reliability Data Relative BTI 3 2 1 (100) (110) (100) (110) NMOS PMOS BTI reliability data for 45nm high-k+metal gate devices show no intrinsic difference between (100) and (110) substrate orientations IEDM 2008 32
Outline Transistor Scaling Stress Effects on Mobility Comparison of (100) and (110) Silicon Substrates Device Performance Summary IEDM 2008 33
Summary Record PMOS drive current of 1.2mA/um are shown PMOS drive currents on (110) substrates show a 15% performance improvement NMOS drive currents on (110) substrates for typical device widths are only degraded 5-8% The fundamental physical reason behind these behaviors is understood The use of (110) silicon substrates is a promising technology option IEDM 2008 34
For further information on Intel's silicon technology, please visit our Technology & Research page at www.intel.com/technology IEDM 2008 35