Charge-trap memories with high-k control dielectrics
|
|
- Tobias Fleming
- 6 years ago
- Views:
Transcription
1 Charge-trap memories with high-k control dielectrics Gabriel Molas CEA-LETI MINATEC Advanced Memory Technology G. Molas Workshop on Innovative Memory Technologies June 24 th
2 Outline Context Charge trap memories with high-k control dielectrics Modelling and simulation Conclusions G. Molas Workshop on Innovative Memory Technologies June 24 th
3 Year of production NAND Flash Technology [nm] Cell type Floating gate NAND Interpoly Interpoly thickness [nm] Context TANOS NAND FG ONO FG ONO FG ONO FG/CT ONO CT ONO CT High-k CT-3D High-k CT-3D High-k 9-10 ITRS 2007 envisages High-k interpoly combined with charge trapping (CT) layers for sub-30nm nodes to maintain high coupling ratio and good reliability Samsung TANOS (TaN / Al 2 O 3 / Si 3 N 4 / SiO 2 / Si) memory envisaged for sub-30 nm (resistance to SILC, low cell to cell X coupling ) CT-3D High-k 9-10 TANOS 63nm SAMSUNG IEDM 05 TANOS 40nm SAMSUNG IEDM 06, VLSI 06 G. Molas Workshop on Innovative Memory Technologies June 24 th
4 Context - Embedded charge traps 1T SONOS + high-k dielectrics Nitride charge trap memory Reduction of the programming voltages (high-k tunox and topox) Split gate SONOS Reduction of the programming consumption (SSI instead of CHE) MG AG R. v. Schaijk, NVSMW 2006, NXP LETI program in progress Patent US 2008/ , K. YASUI et al., Nov. 2008, RENESAS LETI program in progress G. Molas Workshop on Innovative Memory Technologies June 24 th
5 Outline Context Charge trap memories with high-k control dielectrics High-k Control dielectric optimization Nitride thickness Metal gate Modelling and simulation Conclusions G. Molas Workshop on Innovative Memory Technologies June 24 th
6 Optimization of charge trap memories SANOS-like memories High-k Control dielectric - Study of various high-k materials - Introduction of a SiO 2 interlayer Nitride thickness Impact of the nitride thickness on the memory retention 16nm Al 2 O 3 50nm 5.5nm 3.5nm Si 3 N 4 SiO 2 Control gate Comparison of various gate types on the erasing characteristics G. Molas Workshop on Innovative Memory Technologies June 24 th
7 High-k control dielectrics - HfAlO HfO 2, Al 2 O 3, and HfAlO deposited by ALCVD (H 2 O, TMA and HfCl 4 precursors) in ASM PULSAR 2000 tool used as control dielectrics Optical Bandgap [ev] Eg = [Hf] Al 2 O 3 HfO 2 Hf fraction Bandgap: HfO 2 < HfAlO < Al 2 O Stress Time [s] G. Molas Workshop on Innovative Memory Technologies June 24 th V T [V] V G : 10V 14V Programming speed: HfO 2 > HfAlO > Al 2 O 3 Tuning the memory characteristics with the Hf:Al ratio HfO 2 HfAlO Al 2 O 3
8 High-k control dielectrics - HTO / Al 2 O 3 bilayer SANOS 100% HTO/Al2O3 EOT 4/8 nm => 7.3nm Al 2 O 3 V T / V T,t=0s [-] 90% Al2O3 EOT 16 nm => 6.6nm 20nm => 8.2nm Poly-Si Al 2 O 3 HTO SAONOS Al 2 O 3 HTO 80% Si 3 N 4 SiO Retention time [s] Same EOT HTO/Al 2 O 3 bilayers enable improved retention for the same EOT (so with no degradation of the programming voltages) M. Bocquet et al., SSE 2009 G. Molas Workshop on Innovative Memory Technologies June 24 th
9 Impact of the nitride thickness V T / V Tinit [% ] Si 3 N 4 : 3nm 6nm 10nm Nitride layer Retention Time [s] T=25 C 10 5 Si 3 N 4 3nm 6nm nm HT : no difference G. Molas Workshop on Innovative Memory Technologies June 24 th Life Time (@ V T / V Tprog =95%) Thick Si 3 N 4 Better retention 1/kT [1/eV] Nitride thickness mostly impacts the retention at RT: Same retention behavior at high temperature RT : difference data retention Si 3 N 4 3nm 6nm 10nm M. Bocquet et al., IMW 2009
10 Impact of the control gate on erasing V T - V To [V] Poly N+ Poly P+ V G =-18V Blocking Oxide: HTO / Al2O3 V G =-12V Stress time [s] M. Bocquet et al., ESSDERC 2008 Same speed between P+/N+ poly-si gate Poly - Si N+ / P+ Al 2 O 3 HTO Si 3 N 4 V T saturation appears for N+ type gate at high voltages P+ poly-si gate: limited erase saturation G. Molas Workshop on Innovative Memory Technologies June 24 th h+ e- Control Gate SiO 2 8nm 5nm 6nm 2.5nm
11 Collaboration with Aixtron Metal gate Deposition of TaN and TaAlN gates (AVD ) on ANOS stacks Midgap metal gates reduce erase saturation with respect to N+ gates G. Molas Workshop on Innovative Memory Technologies June 24 th
12 Outline Context Charge traps memories with high-k control dielectrics Modelling and simulation Nitride ab-initio Device physical modelling Device TCAD simulation Conclusions G. Molas Workshop on Innovative Memory Technologies June 24 th
13 Ab-initio: SiN Band-gap calculations Objectives: Study of the origin of charge trapping in SiN layers Consideration of defects: N and Si vacancies, saturated with H species (measured by MIR) Are the defects electrically active (e- energy states in the gap)? β phase E. Vianello, P. Blaise et al. G. Molas Workshop on Innovative Memory Technologies June 24 th
14 x V G Poly-Si Device physical modelling [E. Vianello, ESSDERC 2008] Al2O3 Si3N4 SiO2 (1) Tunnel-In (FN, DT, mfn, B-T) J in (1) program V G >>0 x (2) J out (3) (2) Electron transport + capture/emission Motion of electrons in SiN:Drift-Diffusion Interaction between the electrons in the CB and in the energy gap Emission rate (Poole-Frenkel) J out retention V G =0 J out (3) (2) (3) (3) Tunnel-Out G. Molas Workshop on Innovative Memory Technologies June 24 th
15 4x10 19 Retention at high temperature: Nitride charge distribution Trapped charge Trapped density charge [1/cm density 3 ] [1/cm 3 ] Immediately After programming 2x T=250 C x10 19 Nitride thickness [nm] Si Jout e- SiO 2 Si 3 N 4 Jout Al 2 O 3 Gate During retention 2x10 19 Jout e- Jout T=250 C T=250 C Si Nitride thickness [nm] SiO 2 Si 3 N 4 G. Molas Workshop on Innovative Memory Technologies June 24 th Al 2 O 3 Thermal emission in Si 3 N 4 Trapped charge redistribution Quick migration to SiO 2 and Al 2 O 3 interfaces Small retention difference between thin and thick SiN Gate M. Bocquet et al., IMW 2009
16 Drain Current Id [ua/um] TCAD: SONOS Split gate architectures Simulated structure defined using Synopsis tool E-3 Memory gate bias AG MG Vd=5V Vg2= 0V 2V 4V 6V 8V 10V Access Gate Voltage Vg1 [V] LETI program in collaboration with STM E. Nowak et al. In programming mode: Vg1=1V: Id limited by the conduction in the access transistor (weak inversion). Low consumption. Vmg=9V: generates the vertical electric field for SSI G. Molas Workshop on Innovative Memory Technologies June 24 th
17 Outline Context Charge traps memories with high-k control dielectrics Modelling and simulation Conclusions G. Molas Workshop on Innovative Memory Technologies June 24 th
18 Conclusions 1/2 Charge trap memories with high-k control dielectrics High-k control dielectrics engineering of SANOS HfAlO: by tuning the Hf/Al concentration of HfAlO alloys, a good compromise can be achieved in terms of: Coupling ratio (ε): good PE speed with Hf-rich samples Insulating capabilities: high bandgap, low E A with Al-rich samples Thermal stability (crystallization T ): increases w ith %Hf Improvement of SANOS memory retention by using a HTO/Al 2 O 3 control dielectrics double layer Impact of nitride thickness on retention Retention at room temperature increases with SiN thickness Thickness dependance disappears at high temperatures Impact of control gate on erasing Metal (TiN, TaN, TaAlN) an P+ control gates reduce erase saturation at high voltages G. Molas Workshop on Innovative Memory Technologies June 24 th
19 Modelling and simulations Conclusions 2/2 Ab-initio simulations of nitride layers (DFT, GW) Evaluation of the intrinsic properties of nitride (bandgap, impacts of defects on electrical traps ) Simulation hypotheses based on physical and morphological characterisation of nitride layers Physical modelling of nitride memories based on drift diffusion in nitride Quantitative description of the charge redistribution in nitride at high temperature during retention TCAD simulations allow to evaluate the potentiality of new architectures Reduced consumption in SONOS split gate memories in comparison with 1T architectures G. Molas Workshop on Innovative Memory Technologies June 24 th
20 Acknowledgments B. De Salvo (leader of the advanced memory activity), M. Bocquet, E. Vianello, J. P. Colonna, M. Gély, E. Nowak, L. Perniola, H. Grampeix, P. Blaise, P. Brianceau, F. Martin, C. Licitra, N. Rochat, E. Martinez, A. M. Papon, H. Dansas, P. Besson, P. Scheiblin, V. Vidal, A. Toffoli, R. Kies, G. Ghibaudo, G. Pananakakis, O. Boissière LETI cleanroom facilities CEA-LETI MINATEC Grenoble, France IU.NET, Udine, Italy CNRS IMEP Grenoble, France Aixtron, USA G. Molas Workshop on Innovative Memory Technologies June 24 th
Memory Devices. Ki-Nam Kim, President, Institut of Technology Samsung Electronics, 2010 IEDM, San Francisco.
Memory Devices In Korea now, Samsung : 2010, 30nm 2Gb DDRS DRAM/DDR3 SRAM 2011, Invest US $12 bil. for 20nm & SysLSI. Hynix : 2010, 26nm MLC- NAND Flash 2011, 30nm 4Gb DRAM At 2020, the demands of computing
More informationRedox-Active Molecular Flash Memory for On-Chip Memory
Redox-Active Molecular Flash Memory for On-Chip Memory By Hao Zhu Electrical and Computer Engineering George Mason University, Fairfax, VA 2013.10.24 Outline Introduction Molecule attachment method & characterizations
More informationMOS Gate Dielectrics. Outline
MOS Gate Dielectrics Outline Scaling issues Technology Reliability of SiO 2 Nitrided SiO 2 High k dielectrics 42 Incorporation of N or F at the Si/SiO 2 Interface Incorporating nitrogen or fluorine instead
More informationStudy of a Thermal Annealing Approach for Very High Total Dose Environments
Study of a Thermal Annealing Approach for Very High Total Dose Environments S. Dhombres 1-2, J. Boch 1, A. Michez 1, S. Beauvivre 2, D. Kraehenbuehl 2, F. Saigné 1 RADFAC 2015 26/03/2015 1 Université Montpellier,
More informationAnnual Meeting. North Carolina State University Dr. Veena Misra. January 17 19, 2017 December
Annual Meeting North Carolina State University Dr. Veena Misra January 17 19, 2017 December 8 2015 1 Misra Group at NCSU Over 9 years experience in wide band gap research on SiC, GaN and Ga2O3. World leaders
More informationFlash Memory with Nanoparticle Floating Gates
Flash Memory with Nanoparticle Floating Gates Sanjay Banerjee Director, Microelectronics Research Center Cockrell Chair Professor of Electrical & Computer Engineering University of Texas at Austin Why
More informationProject III. 4: THIN FILM DEVICES FOR LARGE AREA ELECTRONICS
Project III. 4: THIN FILM DEVICES FOR LARGE AREA ELECTRONICS Project leader: Dr D.N. Kouvatsos Collaborating researchers from other projects: Dr D. Davazoglou Ph.D. candidates: M. Exarchos, L. Michalas
More informationAl 2 O 3 SiO 2 stack with enhanced reliability
Al 2 O 3 SiO 2 stack with enhanced reliability M. Lisiansky, a A. Fenigstein, A. Heiman, Y. Raskin, and Y. Roizin Tower Semiconductor Ltd., P.O. Box 619, Migdal HaEmek 23105, Israel L. Bartholomew and
More informationNon-charge Storage Resistive Memory: How it works
Accelerating the next technology revolution Non-charge Storage Resistive Memory: How it works Gennadi Bersuker Copyright 2009 SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered servicemarks
More informationMARORA A Plasma Selective-oxidation Apparatus for Metal-gate Devices
Hitachi Review Vol. 57 (2008), No. 3 127 MARORA A Plasma Selective-oxidation Apparatus for Metal-gate Devices Tadashi Terasaki Masayuki Tomita Katsuhiko Yamamoto Unryu Ogawa, Dr. Eng. Yoshiki Yonamoto,
More informationLecture 4. Oxidation (applies to Si and SiC only) Reading: Chapter 4
Lecture 4 Oxidation (applies to Si and SiC only) Reading: Chapter 4 Introduction discussion: Oxidation: Si (and SiC) Only The ability to grow a high quality thermal oxide has propelled Si into the forefront
More informationAdvanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 6: New Materials, Processes, and Equipment
Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 6: New Materials, Processes, and Equipment Editors: E. P. Gusev Qualcomm MEMS Technologies San Jose, California, USA D-L. Kwong
More informationVLSI INTRODUCTION P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT
VLSI INTRODUCTION P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents UNIT I INTRODUCTION: Introduction to IC Technology MOS, PMOS, NMOS, CMOS & BiCMOS technologies. BASIC ELECTRICAL PROPERTIES : Basic Electrical
More informationState of the art quality of a GeOx interfacial passivation layer formed on Ge(001)
APPLICATION NOTE State of the art quality of a Ox interfacial passivation layer formed on (001) Summary A number of research efforts have been made to realize Metal-Oxide-Semiconductor Field Effect Transistors
More informationEE 434 Lecture 9. IC Fabrication Technology
EE 434 Lecture 9 IC Fabrication Technology Quiz 7 The layout of a film resistor with electrodes A and B is shown. If the sheet resistance of the film is 40 /, determine the resistance between nodes A and
More informationSiC MOSFET Gate Oxide Breakdown From Extrinsic to Intrinsic
SiC MOSFET Gate Oxide Breakdown From Extrinsic to Intrinsic J. Chbili,3, Z. Chbili,, A. Matsuda, J. P. Campbell, K. Matocha 4, K. P. Cheung * ) NIST, MD ) George Mason University, VA 3) Laboratoire SSC,
More informationCharacterization of the Vertical Position of the Trapped Charge in Charge-trap Flash Memory
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.2, APRIL, 2017 ISSN(Print) 1598-1657 https://doi.org/10.5573/jsts.2017.17.2.167 ISSN(Online) 2233-4866 Characterization of the Vertical Position
More informationRadiation Tolerant Isolation Technology
Radiation Tolerant Isolation Technology Background The following contains a brief description of isolation technologies used for radiation hardened integrated circuits. The technologies mentioned are junction
More informationArchitecting 3-D Integrated Circuit Fabric with Intrinsic Thermal Management Features
Architecting 3-D Integrated Circuit Fabric with Intrinsic Thermal Management Features Mostafizur Rahman, Santosh Khasanvis, Jiajun Shi, Mingyu Li, Csaba Andras Moritz* Electrical and Computer Engineering,
More informationCMOS FABRICATION. n WELL PROCESS
CMOS FABRICATION n WELL PROCESS Step 1: Si Substrate Start with p- type substrate p substrate Step 2: Oxidation Exposing to high-purity oxygen and hydrogen at approx. 1000 o C in oxidation furnace SiO
More informationNew Materials as an enabler for Advanced Chip Manufacturing
New Materials as an enabler for Advanced Chip Manufacturing Drive Innovation, Deliver Excellence ASM International Analyst and Investor Technology Seminar Semicon West July 10 2013 Outline New Materials:
More informationHigh Performance High-K + Metal Gate Strain Enhanced Transistors on (110) Silicon
High Performance High-K + Metal Gate Strain Enhanced Transistors on (110) Silicon Paul Packan, S. Cea*, H. Deshpande, T. Ghani, M. Giles*, O. Golonzka, M. Hattendorf, R. Kotlyar*, K. Kuhn, A. Murthy, P.
More informationElectrical Characteristics of Rare Earth (La, Ce, Pr and Tm) Oxides/Silicates Gate Dielectric
Electrical Characteristics of Rare Earth (La, Ce, Pr and Tm) Oxides/Silicates Gate Dielectric K. Matano 1, K. Funamizu 1, M. Kouda 1, K. Kakushima 2, P. Ahmet 1, K. Tsutsui 2, A. Nishiyama 2, N. Sugii
More informationMOS Front-End. Field effect transistor
MOS Front-End Back-end Transistor Contact Front-end p-well STI n-well Front-end-of-line includes substrate, isolation, wells, transistor, silicide Field effect transistor MOSFET: Metal-Oxide-Semiconductor
More informationSupplementary Figure S1 Crystal structure of the conducting filaments in sputtered SiO 2
Supplementary Figure S1 Crystal structure of the conducting filaments in sputtered SiO 2 based devices. (a) TEM image of the conducting filament in a SiO 2 based memory device used for SAED analysis. (b)
More informationMaterials Characterization
Materials Characterization C. R. Abernathy, B. Gila, K. Jones Cathodoluminescence (CL) system FEI Nova NanoSEM (FEG source) with: EDAX Apollo silicon drift detector (TE cooled) Gatan MonoCL3+ FEI SEM arrived
More informationInterface Structure and Charge Trapping in HfO 2 -based MOSFETS
Interface Structure and Charge Trapping in HfO 2 -based MOSFETS MURI - ANNUAL REVIEW, 13 and 14 th May 2008 S.K. Dixit 1, 2, T. Feng 6 X.J. Zhou 3, R.D. Schrimpf 3, D.M. Fleetwood 3,4, S.T. Pantelides
More informationLecture Day 2 Deposition
Deposition Lecture Day 2 Deposition PVD - Physical Vapor Deposition E-beam Evaporation Thermal Evaporation (wire feed vs boat) Sputtering CVD - Chemical Vapor Deposition PECVD LPCVD MVD ALD MBE Plating
More informationImpact of Filament Evolution on Reliability Issues of Oxide Electrolyte Based Conductive Bridge Random Access Memory
Impact of Filament Evolution on Reliability Issues of Oxide Electrolyte Based Conductive Bridge Random Access Memory Hangbing Lv, Xiaoxin Xu, Hongtao Liu, Qing Luo, Qi Liu, Shibing Long, Ming Liu* Institute
More informationFORMING-FREE NITROGEN-DOPED ALUMINUM OXIDE RESISTIVE RANDOM ACCESS MEMORY GROWN BY ATOMIC LAYER DEPOSITION TECHNIQUE A DISSERTATION
FORMING-FREE NITROGEN-DOPED ALUMINUM OXIDE RESISTIVE RANDOM ACCESS MEMORY GROWN BY ATOMIC LAYER DEPOSITION TECHNIQUE A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE
More informationEE 330 Lecture 9. IC Fabrication Technology Part II. -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects
EE 330 Lecture 9 IC Fabrication Technology Part II -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects Review from Last Time Etching Dry etch (anisotropic) SiO
More informationFOR SEMICONDUCTORS 2009 EDITION
INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2009 EDITION FRONT END PROCESSES THE ITRS IS DEVISED AND INTENDED FOR TECHNOLOGY ASSESSMENT ONLY AND IS WITHOUT REGARD TO ANY COMMERCIAL CONSIDERATIONS
More informationAtomic Layer Deposition of High-k k Dielectric and Metal Gate Stacks for MOS Devices
International Conference on Characterization and Metrology for ULSI Technology March 15-18, 2005 Atomic Layer Deposition of High-k k Dielectric and Metal Gate Stacks for MOS Devices Yoshi Senzaki, Kisik
More informationTechnology. Semiconductor Manufacturing. Hong Xiao INTRODUCTION TO SECOND EDITION SPIE PRESS
INTRODUCTION TO Semiconductor Manufacturing Technology SECOND EDITION Hong Xiao TECHNISCHE INFORMATIONSBiBUOTHEK UNIVERSITATSBIBLIOTHEK HANNOVER SPIE PRESS Bellingham,Washington USA Contents Preface to
More informationIEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 55, NO. 4, AUGUST
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 55, NO. 4, AUGUST 2008 1833 Radiation Effects in MOS Oxides James R. Schwank, Fellow, IEEE, Marty R. Shaneyfelt, Fellow, IEEE, Daniel M. Fleetwood, Fellow, IEEE,
More informationMOLYBDENUM AS A GATE ELECTRODE FOR DEEP SUB-MICRON CMOS TECHNOLOGY
Mat. Res. Soc. Symp. Vol. 611 2000 Materials Research Society MOLYBDENUM AS A GATE ELECTRODE FOR DEEP SUB-MICRON CMOS TECHNOLOGY Pushkar Ranade, Yee-Chia Yeo, Qiang Lu, Hideki Takeuchi, Tsu-Jae King, Chenming
More informationSilicon Oxides: SiO 2
Silicon Oxides: SiO 2 Uses: diffusion masks surface passivation gate insulator (MOSFET) isolation, insulation Formation: grown / native thermal: highest quality anodization deposited: C V D, evaporate,
More informationVLSI Systems and Computer Architecture Lab
ΚΥΚΛΩΜΑΤΑ VLSI Πανεπιστήμιο Ιωαννίνων CMOS Technology Τμήμα Μηχανικών Η/Υ και Πληροφορικής 1 From the book: An Introduction ti to VLSI Process By: W. Maly ΚΥΚΛΩΜΑΤΑ VLSI Διάρθρωση 1. N well CMOS 2. Active
More informationEECS130 Integrated Circuit Devices
EECS130 Integrated Circuit Devices Professor Ali Javey 9/13/2007 Fabrication Technology Lecture 1 Silicon Device Fabrication Technology Over 10 15 transistors (or 100,000 for every person in the world)
More information2006 UPDATE METROLOGY
INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS METROLOGY THE ITRS DEVED AND INTENDED FOR TECHNOLOGY ASSESSMENT ONLY AND WITHOUT REGARD TO ANY COMMERCIAL CONSIDERATIONS PERTAINING TO INDIVIDUAL PRODUCTS
More informationEE 560 FABRICATION OF MOS CIRCUITS. Kenneth R. Laker, University of Pennsylvania
1 EE 560 FABRICATION OF MOS CIRCUITS 2 CMOS CHIP MANUFACTRING STEPS Substrate Wafer Wafer Fabrication (diffusion, oxidation, photomasking, ion implantation, thin film deposition, etc.) Finished Wafer Wafer
More informationEEC 118 Lecture #5: MOS Fabrication. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #5: MOS Fabrication Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 3 this week, report due next week HW 3 due this Friday at 4
More informationOptical pumping and final metal investigation
Optical pumping and final metal investigation FLOORS Optical pumping of unstressed device Optical pumping of stressed device Stressing points Trap analysis t=0, As Built t>0, Degradation Final Metal Study
More informationSection 4: Thermal Oxidation. Jaeger Chapter 3. EE143 - Ali Javey
Section 4: Thermal Oxidation Jaeger Chapter 3 Properties of O Thermal O is amorphous. Weight Density =.0 gm/cm 3 Molecular Density =.3E molecules/cm 3 O Crystalline O [Quartz] =.65 gm/cm 3 (1) Excellent
More informationSchottky-Barrier-Height Modulation of Ni Silicide/Si Contacts by Insertion of Thin Er or Pt Layers
Schottky-Barrier-Height Modulation of Ni Silicide/Si Contacts by Insertion of Thin Er or Pt Layers Yoshihisa Ohishi 1, Kohei Noguchi 1, Kuniyuki Kakushima 2, Parhat Ahmet 1, Kazuo Tsutsui 2, Nobuyuki Sugii
More informationNagatsuta, Midori-ku, Yokohama , Japan. Technology, 4259-S2-20 Nagatsuta, Midori-ku, Yokohama , Japan
Improvement of Interface Properties of W/La O 3 /Si MOS Structure Using Al Capping Layer K. Tachi a, K. Kakushima b, P. Ahmet a, K. Tsutsui b, N. Sugii b, T. Hattori a, and H. Iwai a a Frontier Collaborative
More informationEffect of grain size on the mobility and transfer characteristics of polysilicon thin-film transistors
Indian Journal of Pure & Applied Physics Vol. 42, July 2004, pp 528-532 Effect of grain size on the mobility and transfer characteristics of polysilicon thin-film transistors Navneet Gupta* & B P Tyagi**
More informationModeling of Local Oxidation Processes
Introduction Isolation Processes in the VLSI Technology Main Aspects of LOCOS simulation Athena Oxidation Models Several Examples of LOCOS structures Calibration of LOCOS effects using VWF Field Oxide
More informationHei Wong.
Defects and Disorders in Hafnium Oxide and at Hafnium Oxide/Silicon Interface Hei Wong City University of Hong Kong Email: heiwong@ieee.org Tokyo MQ2012 1 Outline 1. Introduction, disorders and defects
More informationTri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering
Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering Jack Kavalieros, Brian Doyle, Suman Datta, Gilbert Dewey, Mark Doczy, Ben Jin, Dan Lionberger, Matthew
More informationNew Materials and Processes for Advanced Chip Manufacturing
New Materials and Processes for Advanced Chip Manufacturing Bob Hollands Director Technical Marketing EXANE BNP Paribas Tech Expert Access Event London June 27, 2013 Outline New Materials: Moore s Law
More informationRADIATION HARDNESS OF MEMRISTIVE SYSTEMS
RADIATION HARDNESS OF MEMRISTIVE SYSTEMS A. FANTINI ON BEHALF OF IMEC RRAM TEAM AND VU ISDE TEAM Workshop on Memristive systems for Space applications ESTEC - 30/04/2015 OUTLINE Introduction RRAM for space
More informationA New High-k Transistor Technology Implemented in Accordance with the 55nm Design Rule Process
A New High-k Transistor Technology Implemented in Accordance with the 55nm Design Rule Process FUKASE Tadashi, NAKAHARA Yasushi, TAKAHASHI Toshifumi, IMAI Kiyotaka Abstract NEC Electronics has developed
More informationSimulation of Inverse Piezoelectric effect in degradation AlGaN/GaN devices. David Horton, Dr M E Law
Simulation of Inverse Piezoelectric effect in degradation AlGaN/GaN devices David Horton, Dr M E Law Simulation Approach FLOORS Gate t > 0 AlGaN GaN Defect at gate edge t=0, As Built 1] Park S.Y, Kim,
More informationLow temperature deposition of thin passivation layers by plasma ALD
1 Low temperature deposition of thin passivation layers by plasma ALD Bernd Gruska, SENTECH Instruments GmbH, Germany 1. SENTECH in brief 2. Low temperature deposition processes 3. SENTECH SI ALD LL System
More informationOptimization of optical performances in submicron silicon-on-insulator rib and strip waveguides by H 2 thermal annealing
I N S T I T U T D E R E C H E R C H E T E C H N O L O G I Q U E Optimization of optical performances in submicron silicon-on-insulator rib and strip waveguides by H thermal annealing Erwine Pargon 1, Cyril
More informationFirst Commercial Demonstration of an Emerging Memory Technology for Embedded flash using CBRAM
adesto TECHNOLOGIES First Commercial Demonstration of an Emerging Memory Technology for Embedded flash using CBRAM P. Blanchard, C. Gopalan, J. Shields, W. Lee, Y. Ma, S. Park, B. Guichet, S. Hsu, T. Gallo,
More informationEtching Etching Definitions Isotropic Etching: same in all direction Anisotropic Etching: direction sensitive Selectivity: etch rate difference
Etching Etching Definitions Isotropic Etching: same in all direction Anisotropic Etching: direction sensitive Selectivity: etch rate difference between 2 materials Need strong selectivity from masking
More informationChallenges and Future Directions of Laser Fuse Processing in Memory Repair
Challenges and Future Directions of Laser Fuse Processing in Memory Repair Bo Gu, * T. Coughlin, B. Maxwell, J. Griffiths, J. Lee, J. Cordingley, S. Johnson, E. Karagiannis, J. Ehrmann GSI Lumonics, Inc.
More informationCMOS Manufacturing Process
CMOS Manufacturing Process CMOS Process A Modern CMOS Process gate-oxide TiSi 2 AlCu Tungsten SiO 2 n+ p-well p-epi poly n-well p+ SiO 2 p+ Dual-Well Trench-Isolated CMOS Process Circuit Under Design V
More informationThin Films: Sputtering Systems (Jaeger Ch 6 & Ruska Ch 7,) Sputtering: gas plasma transfers atoms from target to substrate Can deposit any material
Thin Films: Sputtering Systems (Jaeger Ch 6 & Ruska Ch 7,) Sputtering: gas plasma transfers atoms from target to substrate Can deposit any material on any substrate (in principal) Start with pumping down
More informationHybrid III-V/Si DFB laser integration on a 200 mm fully CMOS-compatible silicon photonics platform
Hybrid III-V/Si DFB laser integration on a 200 mm fully CMOS-compatible silicon photonics platform B. Szelag 1, K. Hassan 1, L. Adelmini 1, E. Ghegin 1,2, Ph. Rodriguez 1, S. Bensalem 1, F. Nemouchi 1,
More informationAdvanced CMOS Process Technology Part 3 Dr. Lynn Fuller
MICROELECTRONIC ENGINEERING ROCHESTER INSTITUTE OF TECHNOLOGY Part 3 Dr. Lynn Fuller Webpage: http://people.rit.edu/lffeee Electrical and Microelectronic Engineering Rochester Institute of Technology 82
More informationEffect of High Pressure Deuterium Annealing on Performance and Reliability of MOSFETs with High-k Gate Dielectrics and Metal Gate
Effect of High Pressure Deuterium Annealing on Performance and Reliability of MOSFETs with High-k Gate Dielectrics and Metal Gate H. Park, M. Chang, H. Yang, M. S. Rahman, M. Cho, B.H. Lee*, R. Choi*,
More informationHOMEWORK 4 and 5. March 15, Homework is due on Monday March 30, 2009 in Class. Answer the following questions from the Course Textbook:
HOMEWORK 4 and 5 March 15, 2009 Homework is due on Monday March 30, 2009 in Class. Chapter 7 Answer the following questions from the Course Textbook: 7.2, 7.3, 7.4, 7.5, 7.6*, 7.7, 7.9*, 7.10*, 7.16, 7.17*,
More informationOxide Growth. 1. Introduction
Oxide Growth 1. Introduction Development of high-quality silicon dioxide (SiO2) has helped to establish the dominance of silicon in the production of commercial integrated circuits. Among all the various
More informationThin Films: Sputtering Systems (Jaeger Ch 6 & Ruska Ch 7,) Can deposit any material on any substrate (in principal) Start with pumping down to high
Thin Films: Sputtering Systems (Jaeger Ch 6 & Ruska Ch 7,) Can deposit any material on any substrate (in principal) Start with pumping down to high vacuum ~10-7 torr Removes residual gases eg oxygen from
More informationFAST AND SLOW-STATE TRAPS AT THE MOSFET OXIDE INTERFACE WITH A TEMPERATURE DEPENDENT C-V METHOD.
Journal of Electron Devices, Vol. 1, 2003, pp. 1-6 JED [ISSN: 1682-3427] Journal of Electron Devices www.j-elec-dev.org FAST AND SLOW-STATE TRAPS AT THE MOSFET OXIDE INTERFACE WITH A TEMPERATURE DEPENDENT
More informationChallenges of Silicon Carbide MOS Devices
Indo German Winter Academy 2012 Challenges of Silicon Carbide MOS Devices Arjun Bhagoji IIT Madras Tutor: Prof. H. Ryssel 12/17/2012 1 Outline What is Silicon Carbide (SiC)? Why Silicon Carbide? Applications
More informationWorkfunction Tuning for Single-Metal Dual-Gate With Mo and NiSi Electrodes
tivation Workfunction Tuning for ngle-metal Dual-Gate With and i Electrodes poly- Gate Gate depletion effect -Effective oxide thickness increase Metal Gate o gate depletion effect K.Sano, M.Hino, and K.Shibahara
More information11:30 AM - C4.4 Chemical Vapor Deposition of Cobalt Nitride and Its Application as an Adhesion-enhancing Layer for Advanced Copper Interconnects
2012-04-11 SYMPOSIUM C 11:30 AM - C4.4 Chemical Vapor Deposition of Cobalt Nitride and Its Application as an Adhesion-enhancing Layer for Advanced Copper Interconnects Jing Yang 1, Harish B. Bhandari 1,
More informationIsolation Technology. Dr. Lynn Fuller
ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Isolation Technology Dr. Lynn Fuller Motorola Professor 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585) 475-2035 Fax (585) 475-5041
More informationDevice Simulation of Grain Boundaries in Lightly Doped Polysilicon Films and Analysis of Dependence on Defect Density
Jpn. J. Appl. Phys. Vol. 40 (2001) pp. 49 53 Part 1, No. 1, January 2001 c 2001 The Japan Society of Applied Physics Device Simulation of Grain Boundaries in Lightly Doped Polysilicon Films and Analysis
More informationPoint-contacting by Localised Dielectric Breakdown: A new approach for contacting solar cells
Point-contacting by Localised Dielectric Breakdown: A new approach for contacting solar cells SPREE Public Seminar 20 th February 2014 Ned Western Supervisor: Stephen Bremner Co-supervisor: Ivan Perez-Wurfl
More informationPortland Technology Development, * CR, # QRE, % PTM Intel Corporation
A 45nm Logic Technology with High-k + Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom,
More informationSilicon Wafer Processing PAKAGING AND TEST
Silicon Wafer Processing PAKAGING AND TEST Parametrical test using test structures regularly distributed in the wafer Wafer die test marking defective dies dies separation die fixing (not marked as defective)
More informationInterconnects. Outline. Interconnect scaling issues Aluminum technology Copper technology. Properties of Interconnect Materials
Interconnects Outline Interconnect scaling issues Aluminum technology Copper technology 1 Properties of Interconnect Materials Metals Silicides Barriers Material Thin film Melting resistivity point ( C)
More information"Plasma CVD passivation; Key to high efficiency silicon solar cells",
"Plasma CVD passivation; Key to high efficiency silicon solar cells", David Tanner Date: May 7, 2015 2012 GTAT Corporation. All rights reserved. Summary: Remarkable efficiency improvements of silicon solar
More informationCorrelation Between Energy Gap and Defect Formation of Al Doped Zinc Oxide on Carbon Doped Silicon Oxide
TRANSACTIONS ON ELECTRICAL AND ELECTRONIC MATERIALS Vol. 15, No. 4, pp. 207-212, August 25, 2014 Regular Paper pissn: 1229-7607 eissn: 2092-7592 DOI: http://dx.doi.org/10.4313/teem.2014.15.4.207 Correlation
More informationLaser Spike Annealing for sub-20nm Logic Devices
Laser Spike Annealing for sub-20nm Logic Devices Jeff Hebb, Ph.D. July 10, 2014 1 NCCAVS Junction Technology Group Semicon West Meeting July 10, 2014 Outline Introduction Pattern Loading Effects LSA Applications
More informationReactor wall plasma cleaning processes after InP etching in Cl 2 /CH 4 /Ar ICP discharge
Reactor wall plasma cleaning processes after InP etching in Cl 2 /CH 4 /Ar ICP discharge R. Chanson a, E. Pargon a, M. Darnon a, C. Petit Etienne a, S. David a, M. Fouchier a, B. Glueck b, P. Brianceau
More information3 Failure Mechanism of Semiconductor Devices
3 Failure Mechanism of Semiconductor Devices Contents 3.1 Reliability Factor and Failure Mechanism of Semiconductor Devices 3-1 3.1.1 Reliability factors 3-1 3.1.2 Failure factors and mechanisms of semiconductor
More informationSemiconductor Technology
Semiconductor Technology from A to Z Oxidation www.halbleiter.org Contents Contents List of Figures List of Tables II III 1 Oxidation 1 1.1 Overview..................................... 1 1.1.1 Application...............................
More informationSection 4: Thermal Oxidation. Jaeger Chapter 3
Section 4: Thermal Oxidation Jaeger Chapter 3 Properties of O Thermal O is amorphous. Weight Density =.0 gm/cm 3 Molecular Density =.3E molecules/cm 3 O Crystalline O [Quartz] =.65 gm/cm 3 (1) Excellent
More informationHigh Performance Organic Thin-Film Transistors and Nonvolatile Memory Devices Using High- Dielectric Layers
High Performance Organic Thin-Film Transistors and Nonvolatile Memory Devices Using High- Dielectric Layers 197 12 X High Performance Organic Thin-Film Transistors and Nonvolatile Memory Devices Using
More informationFrom microelectronics down to nanotechnology.
From microelectronics down to nanotechnology sami.franssila@tkk.fi Contents Lithography: scaling x- and y-dimensions MOS transistor physics Scaling oxide thickness (z-dimension) CNT transistors Conducting
More informationCapital / MRKT CAP \6.14B / \280.6B (as of May 12 th ) Chugeri, Yangji myun, Cheoin gu, Yongin, Kyunggi do, Korea
Company name Established 05 JAN, 2000 Eugene Technology Co., Ltd. CEO Pyung Yong Um Capital / MRKT CAP \6.14B / \280.6B (as of May 12 th ) Address Main Products Home Page 209-3 Chugeri, Yangji myun, Cheoin
More informationUltra High Barrier Coatings by PECVD
Society of Vacuum Coaters 2014 Technical Conference Presentation Ultra High Barrier Coatings by PECVD John Madocks & Phong Ngo, General Plasma Inc., 546 E. 25 th Street, Tucson, Arizona, USA Abstract Silicon
More informationBlisters formation mechanism during High Dose Implanted Resist Stripping
Blisters formation mechanism during High Dose Implanted Resist Stripping Marion Croisy a,b,c*, Cécile Jenny a, Claire Richard a, Denis Guiheux a, Sylvain Joblot a, Alain Campo b, Erwine Pargon c, Nicolas
More informationThe Role of Physical Defects in Electrical Degradation of GaN HEMTs
The Role of Physical Defects in Electrical Degradation of GaN HEMTs Carl V. Thompson Dept. of Materials Science and Engineering, MIT Faculty Collaborators: Chee Lip Gan 2,3, Tomas Palacios 1, Jesus Del
More informationModeling and Electrical Characterization of Ohmic Contacts on n-type GaN
Modeling and Electrical Characterization of Ohmic Contacts on n-type GaN Sai Rama Usha Ayyagari Thesis submitted to the faculty of the Virginia Polytechnic Institute and State University in partial fulfillment
More informationSUPPLEMENTARY INFORMATION
SUPPLEMENTARY INFORMATION doi: 1.138/nnano.21.279 Supplementary Material for Single-layer MoS 2 transistors B. Radisavljevic, A. Radenovic, J. Brivio, V. Giacometti, A. Kis Device fabrication Our device
More informationAmorphous Oxide Transistor Electrokinetic Reflective Display on Flexible Glass
Amorphous Oxide Transistor Electrokinetic Reflective Display on Flexible Glass Devin A. Mourey, Randy L. Hoffman, Sean M. Garner *, Arliena Holm, Brad Benson, Gregg Combs, James E. Abbott, Xinghua Li*,
More informationMaterials, Electronics and Renewable Energy
Materials, Electronics and Renewable Energy Neil Greenham ncg11@cam.ac.uk Inorganic semiconductor solar cells Current-Voltage characteristic for photovoltaic semiconductor electrodes light Must specify
More informationIs Now Part of To learn more about ON Semiconductor, please visit our website at
Is Now Part of To learn more about ON Semiconductor, please visit our website at www.onsemi.com ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC
More informationThe Progress and Challenges of Applying High-k/Metal-Gated Devices to Advanced CMOS Technologies
The Progress and Challenges of Applying High-k/Metal-Gated Devices to Advanced CMOS Technologies 8 Hsing-Huang Tseng, Ph.D. Professor of Electrical Engineering Ingram School of Engineering Texas State
More informationI. GaAs Material Properties
I. GaAs Material Properties S. Kayali GaAs is a III V compound semiconductor composed of the element gallium (Ga) from column III and the element arsenic (As) from column V of the periodic table of the
More informationManufacturing Process
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Manufacturing Process July 30, 2002 1 CMOS Process 2 A Modern CMOS Process gate-oxide TiSi 2 AlCu Tungsten
More informationDesign, Fabrication, and Characterization of Nano-scale Cross-Point Hafnium Oxide-Based Resistive Random Access Memory
Design, Fabrication, and Characterization of Nano-scale Cross-Point Hafnium Oxide-Based Resistive Random Access Memory A Thesis Presented to The Academic Faculty By Noah Ellis In Partial Fulfillment Of
More informationBasic Opamp Design and Compensation. Transistor Model Summary
Basic Opamp Design and Compensation David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide of 37 General Constants Transistor charge Boltzman constant Transistor Model Summary
More information