In the DSP camp the main

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1 Conclusion The proposed method gives an optimized and efficient VLSI implementation for calculating 16bit fix point log(1+exp(x)). Compared with fixed point software implementation, it has none approximation error and process is very efficient and simple. Integrated this design in ASIC for speech recognition can greatly reduce the software MIPS requirement and system power consumption, while chip size for this part is very small. References 1. C. Lai, S.-L. Lu, and Q. Zhao. Performance analysis of speech recognition software. Proceedings of the Fifth Workshop on Computer Architecture Evaluation using Commercial Workloads, Feb Israel Koren, Computer Arithmetic Algorithms, A K Peters, Ltd, 2002 Wang Weifeng is senior ASIC design engineer at Fortemedia Are DSP s still the right choice for carrier class VoP? Selecting the right silicon for a carrier class VoP processing platform today is no trivial task. There are a number of well established silicon manufacturers providing comprehensive solutions as well as newer, fabless companies with innovative products and good track records in other telecom related areas. The available choice though boils down to devices based on the traditional, general purpose DSP core (Figure 1a) or more highly optimised, so called, SoC devices (Figure 1b). In the DSP camp the main contenders for carrier class VoP are TI s TNETV3010 and Freescale s MSC8122 whilst in the SoC camp we find Centillium s Entropia 3 and Mindspeed s Miro and Comcerto. The difference between the VoP centric DSP s mentioned here and more general purpose DSP devices is that these VoP DSP s are integrated multi core parts with on chip memory sized to fit a flexible VoP application and industry standard network and bus interfaces for TDM and packet I/O as well as control plane processing. Though this level of integration somewhat blurs the line between VoP DSP devices and SoC devices, we will stick to this

2 terminology to differentiate between the two classes of device in this paper. In the sections below we will try to determine if the VoP DSP is still the best choice when it comes to building a high density, carrier class VoP media gateway. This will require looking at not just what goes on inside the VoP device itself, but how that determines what is required from the external circuitry such as network processors, FPGA s and switches. What can you do with just a DSP? General purpose DSP cores such as TI s C5000 and C6000 family and the StarCore are well established with strong support from their respective manufacturers as well as a wide range of industry partners providing algorithms, development tools, support and programming expertise and in some cases fully tested, production ready applications for specific VoP DSP devices. The SoC category, on the other hand, incorporates proprietary DSP cores, function accelerators and network processing (NP) engines. This provides dedicated, optimised resource pools for the DSP functions of VoP (e.g. vocoding, echo cancellation and tone processing) and the network interfacing functions (e.g. packetization, aggregation and routing). Whilst many system implementers see the DSP core as a number crunching resource for mathematical algorithms, highly optimised VoP applications like TI s Telogy Software are able to turn a VoP DSP into a true voice to packet processing solution by giving them the capability to fully terminate network compliant packets on their interfaces. SoC s certainly also provide this capability and their approach is optimised by the use of dedicated resources for voice processing and network functions. The SoC advantage here is that, for a specific device, a sweet spot can be selected at device design time where the network processing bandwidth capabilities match exactly the amount of voice data that the DSP part is able to process. For a G.711 channel optimised device this requires a

3 high ratio of NP to DSP power, whilst for a more DSP intensive function like the wireless SMV vocoder and echo cancellation more DSP power is required and so fewer network packets need to be processed (Figure 2). The VoP DSP advantage is that precise amounts of general purpose DSP resource can be allocated, at runtime, to voice processing, network packetization, routing and aggregation functions based on what combination of channel capabilities need to be supported at any one time. This allows developers and applications to make maximum use of all device resource for all possible combinations of vocoder and other VoP algorithms, as well as network processing functions. So, the main advantage, in terms of channel capacity, of a SoC is it s sweet spot where resource usage of all its internal components is maximised. This sweet spot however needs to be selected at device design time. Move away from that sweet spot and you either have to waste DSP resource (because the NP engines can t process that many packets) or you have to throttle back the NP engines to allow the DSP s to keep up. Tightly coupled processing, another SoC advantage? The packetization function performed by the network Vol 3 Issue 10 processor element of a SoC (for example there are four network processor engines in Entropia 3 and several ARM based packet engines on Miro and Comcerto) allows tight coupling of the DSP functions with the network interface. This is vitally important for VoP applications as any delay or latency incurred in the voice path can be detrimental to voice

4 quality, which is already impaired by vocoder delay and lossy compression algorithms. Internal to the device the NP function extends to aggregation and routing and again a tightly coupled NP allows efficient classification of incoming packets to determine which DSP core they need to be routed to. VoP DSP s that implement VoP algorithms and packetization processing on the same DSP core are inherently tightly coupled. Applications need not even incur any internal bus delay to transfer a vocoded frame to the packetization algorithm. A well designed, object oriented application will allow the vocoder, packetization engine and jitter removers to share the same on chip data buffers as well as the same processing core, and clever channel based scheduling algorithms are highly effective at eliminating memory access penalties when many different functions run concurrently on the same DSP core. The devices internal routing and aggregation functions are performed at wire speed by the network interface peripheral s intelligent DMA engines and packet classification is based on Ethernet or ATM headers. So who needs network processors? This leaves SoC and VoP DSP devices functionally equivalent in terms of their standalone I/O capabilities, whilst the amount of throughput (i.e. channel density per chip) varies between devices dependant on what algorithms are functional for each channel. In some cases the SoC may have a highly optimised sweet spot, but in all cases all the resources on the VoP DSP can be fully utilised. What s left in terms of system level functionality is the need to integrate a large number of devices together to provide a pool of VoP processing resource with a single (or more likely dual redundant), wide network interface (Figure 3). This is where the network processor, switch or FPGA comes in, and its job is to aggregate packets headed for the network and route packets from the network to the correct VoP device. As SoC and VoP DSP s can both deliver equivalently processed packets to their network interfaces, the external aggregation and routing resource required is determined purely by the systems channel density. Which type of solution has the advantage is only apparent when a board or system can be implemented with a single SoC or VoP DSP device, and then it s down to which one happens to match your density requirement. This however is not a high density carrier gateway. Conclusions The current industry trend in

5 carrier class gateway applications is to consolidate as many functions as possible into a single gateway platform. Sometimes this may mean different software loads for different deployment scenario s (e.g. wireline vs. wireless) and on other occasions this may require all singing all dancing gateways that can simultaneously handle all types of voice and data and transcode or transrate between them. The cost, power and space of any silicon solution can only be maximised across such a wide range of applications if the processing resources can always be fully utilised. Whilst the currently available SoC devices may excel in certain sweet spots, the VoP DSP still rules the roost for high end, flexible and efficient use of silicon in carrier class VoP applications. Phil Thompson is Infrastructure Systems Architect for the VoP business unit at Texas Instruments. DSP Technology: Develop Or License? Consumer expectations continue to rise as mobile electronics such as handsets and PDAs become less expensive, easier to use and provide higher quality features. However, meeting this high functionality, low price expectation can be challenging for device manufacturers as they strive to continually improve the performance of their products while keeping development costs low. For example, advanced handsets and other mobile communications equipment require tremendous processing capability to handle the high volume of information flow commanded by advanced features such as video capture and transfer, Internet browsing, gaming and other data-intensive applications. Efficient processing is especially critical in the wireless arena where battery life is limited and code density becomes a factor. As a result, competition among device manufacturers has become intense. As device manufacturers continuously search for costeffective ways to bring feature rich products to market, many device manufacturers have made the decision to license intellectual property (IP) building blocks for their products rather than developing the technology themselves.