POWER. OpenPOWER Foundation Overview. February Steve Fields IBM Distinguished Engineer Director of Power Systems Design

Transcription

1 Open Foundation Overview February 2014 Steve Fields IBM Distinguished Engineer Director of Power Systems Design 1

2 Goal and Intent of Open Opening the architecture, providing ability to innovate across full Hardware and Software stack Simplify system design with alternative architecture Includes SOC design, Bus Specifications, Reference Designs Open Source Firmware + Operating System + Hypervisor Driving an expansion of enterprise class Hardware and Software stack for the data center Building a complete ecosystem to provide customers with the flexibility to build servers best suited to the architecture 2

3 Why form Open? The number of companies designing & building servers is increasing Traditionally there have been few companies designing systems (HP, IBM, SUN, Dell etc ) Today there are many more: Google, Microsoft, Facebook, Rackspace etc A fairly mature ecosystem including the Taiwanese ODMs is a key enabler of this trend Two disruptive forces are impacting these custom system designs and driving designers to seek alternative architectures Technology integration is migrating what is board customization today to chip customization A need for choice and options in processor sourcing The architecture is a proven server-class technology with a growing server software ecosystem These trends creates an opportunity for a server targeted chip-system-software ecosystem Open expands the opportunity for members to grow this ecosystem There is an opportunity for to participate in Web2.0 and large-scale data centers 3

4 Giving ecosystem partners a license to innovate Open will enable datacenters to rethink their approach to technology Member companies may use for custom open servers and components for Linux based cloud data centers Open ecosystem partners can optimize the interactions of server building blocks microprocessors, networking, I/O & other components to tune performance Platinum Members How will Open Foundation benefit clients? Open technology creates greater choice for customers Open and collaborative model on the Power platform will create more opportunity for innovation New innovators will broaden the capability and value of the Power platform What does this mean to the industry? Game changer on the competitive landscape of the server industry Will enable and drive innovation in the industry Provide more choice to the industry 4

5 Open Foundation Structure Open is an industry foundation based on the architecture, enabling an Open community for development and opportunity for member differentiation and growth OPEN Ecosystem Community Development & Specification Value Add Complementary FOR PROFIT Ecosystem Store Channel Open Corp. Source Software Linkages to other groups Store Development workgroups Architecture & Specification Group System Design Group Specifications Reference Designs Chip Design Group Open IP Blocks Interface specifications Development groups Numerous Participants Fee based component examples Chip IP IBM SW stack Member SW stack on a card or board To Ensure Compliance: All offerings must be validated Consistent with Architecture & Interface Specifications Open Compliance 5

6 PCIe Proposed Ecosystem Enablement Power Open Source Software Stack Components Software Cloud Software Standard Operating Environment (System Mgmt) Operating System / KVM Firmware XCAT Open Firmware Existing Open Source Software Communitie s New OSS Community System Operating Environment Software Stack A modern development environment is emerging based on this type of tools and services Hardware Open Technology Multiple Options to Design with Technology Within Open 8 Framework to Integrate System IP on Chip Industry IP License Model Hardware CAPP CAPI over PCIe Customizable 6 Standard Products 2014 Custom SoC Future

7 Ecosystem Concept Technology FAB SYS ODM I/O I/O OEM Networking Chip Storage SoC Dev IP Dev FW Open Source SW Linux ISV ISV Open Source WEB 2.0 Data Center MSP Cloud Welcoming members at at all all levels 7

8 Membership Options Organized as a distinct 501c6 Not-for-profit entity with a Board of Directors and a Technical Steering Committee. Membership levels provide either a default Board of Director position (Platinum) or an opportunity to be elected to the Board (Gold, Silver, and Assoc/Academic members). The Bylaws detail additional governance by the Board including maximum seats, terms, etc. Technical Steering Committee. Formed from the Project Leads from the core projects and one representative designated by each Platinum member Includes tiered membership of Platinum, Gold, Silver, and individual memberships Annual fee and dedicated full-time equivalent (FTEs) - verification of committed number of FTEs on honor system Contributors, committers, and project leads influence Technical Steering Committee Membership Levels Membership Level Annual Fee FTEs IP contribution Technical Steering Committee Platinum $100k 10 Desired significant, in addition to FTEs One seat per member not otherwise represented Gold $60k 3 Not required May be on TSC if Project Lead Silver $20k 0 Not required May be on TSC if Project Lead Associate & Academic $0 0 Not required May be on TSC if Project Lead Board / Voting position Includes board position Includes TSC position Gold members may elect up to one BOD member per three gold members One Board seat elected by all Silver members May be elected to one community observer board seat Membership agreement, Bylaws, and IP Rights Policy available for review 8

9 Open Foundation Progress Completed legal formation activities Completed legal formation of entity as a standalone not-for-profit 501c6 entity, ratified Bylaws and IP Rights Policy Formalized Board of Directors and elected officers Chairman: Gordon MacKean, Engineering Director, Platforms, Google President: Brad McCredie, Vice President and IBM Fellow, IBM Vice President: Michael Diamond, Senior Director Marketing, Nvidia Chartered Technical Steering Committee and initiated Work Groups: System Software Application Software Open Server Development Platform Hardware Architecture 9

10 Work Groups and Projects Work Group Projects Participants System Software Linux - Little Endian Public (Open Source) KVM Public Application Software (Open Source) Open Server Development Platform Firmware OpenPower FW Interface LE ABI System Operating Environment Open Software ecosystem enablement Toolchain 8 Developer Board 8 Reference Design Public Public Public Public Restricted Restricted Hardware Architecture Compliance Member Open profile of architecture 8 ISA Book 1, 2, 3 Coherent Accelerator Interface Architecture (CAIA) Restricted Restricted 10

11 Open Foundation Next Steps Current initiatives to build industry momentum and strengthen organization Make progress on work groups and projects, formalize process for initiating new work groups or projects Welcome new members via individual conversations, initiate on-boarding process Develop identity / web site March 2014 Launch with software development environment and preliminary hardware design 11

12 SMP Links Accelerators SMP Links PCIe 8 Processor Cores 12 cores (SMT8) 8 dispatch, 10 issue, 16 exec pipe 2X internal data flows/queues Enhanced prefetching 64K data cache, 32K instruction cache Accelerators Crypto & memory expansion Transactional Memory VMM assist Data Move / VM Mobility 12 Mem. Ctrl. Technology 22nm SOI, edram, 15 ML 650mm2 8M L3 Region L3 Cache & Chip Interconnect Energy Management On-chip Power Management Micro-controller Integrated Per-core VRM Critical Path Monitors Mem. Ctrl. Caches 512 KB SRAM L2 / core 96 MB edram shared L3 Up to 128 MB edram L4 (off-chip) Memory Up to 230 GB/s sustained bandwidth Bus Interfaces Durable open memory attach interface Integrated PCIe Gen3 SMP Interconnect CAPI (Coherent Accelerator Processor Interface)

13 8 Building Blocks Core Flexible dynamic threading up to SMT8 64B L2 to L1 data bus 64KB Data Cache 32KB Instruction Cache L2 L3 512KB 8-way L2 cache per core 12-core chip provides 96MB L3 (12 x 8MB 8-way Banks) 12-core chip interconnect 150 GB/sec x 12 segments/direction = 3.6 TB/sec 13 System Infrastructure (SMP interconnect, memory, I/O, energy mgmt, etc)

14 8 Memory Buffer with 16MB of Cache DRAM Chips Memory Buffer DDR Interfaces Memory Buffer Functions Memory Scheduling logic for 4 DIMM channels L4 Cache for performance & energy efficiency Energy Mgmt, RAS decision point Processor Interface 9.6 Gbit/s interface Robust error detection & dynamic lane sparing Extensible protocol for innovation build-out Scheduler & Management 16MB Memory Cache 8 Link System Design Points Support buffer on motherboard or on DIMM Support 1, 2, 4 or 8 buffers per processor socket Up to 230 GB/sec per processor socket Up to 128 GB of L4 Cache per processor socket 14

15 8 CAPI Coherent Accelerator Processor Interface (CAPI) Virtual Addressing Accelerator can work with same memory addresses that the processors use Pointers de-referenced same as the host application Removes OS & device driver overhead Hardware Managed Cache Coherence Enables the accelerator to participate in Locks as a normal thread Lowers Latency over IO communication model 8 8 Coherence Bus CAPP Custom Hardware Application PSL FPGA or ASIC PCIe Gen 3 Transport for encapsulated messages Processor Service Layer (PSL) Present robust, durable interfaces to applications Offload complexity / content from CAPP 15

16 CAPI for Hardware Acceleration Custom Hardware Application PSL FPGA or ASIC Custom Hardware Acceleration Unit (FPGA or ASIC) Implement specific system, middleware or application function Written to durable interface provided by PSL Accelerator function operates as part of application Behaves as another hardware thread running the application Eliminates overhead associated with traditional PCIe attach 16

17 CAPI for Attachment of I/O Devices Network or Storage Interface I/O Controller PSL FPGA or ASIC I/O Device can operate at user level Behaves as another hardware thread running the application Eliminates overhead associated with traditional I/O Device Driver model No pinned pages or memory copies required Ability to address all of system memory Advantages of CAPI protocol being transported over PCIe Gen3 interfaces Compatible with industry ASIC design capabilities Same device able to operate in PCIe and CAPI modes CAPI devices have access to system tailstock for external connectivity 17

18 Open Foundation Benefits System Design Open the Architecture to enable broader usage and collaboration Enable and drive innovation in the industry Data Center Enable innovation across the stack to optimize deployment Enable choice in architecture and processor sourcing Customer Greater choice New levels of capability through innovation and broad collaboration in the platform 18

19 Membership Application and Inquiries Membership Levels Membership Level Annual Fee FTEs IP contribution Technical Steering Committee Platinum $100k 10 Desired significant, in addition to FTEs One seat per member not otherwise represented Gold $60k 3 Not required May be on TSC if Project Lead Silver $20k 0 Not required May be on TSC if Project Lead Associate & Academic $0 0 Not required May be on TSC if Project Lead Board / Voting position Includes board position Includes TSC position Gold members may elect up to one BOD member per three gold members One Board seat elected by all Silver members May be elected to one community observer board seat Membership agreement, Bylaws, and IP Rights Policy available for review Very simple 2-page application: Contact information for Representative, Accounts Payable contact, Technical contact, Marketing/Communications contact Desired Level of Membership Signature For further information info@open-power.org 19

20 20 20 Confidential IBM Confidential 2013 Open