Sharif University of Technology Introduction to ASICs

Transcription

1 SoC Design Lecture 3: Introduction to ASICs Shaahin Hessabi Department of Computer Engineering Sharif University of Technology

2 IC Technology The term ASIC is often reserved for circuits that are fabricated in a silicon foundry, while circuits that can be programmed at the customer s s site are called Programmable Logic. The term full custom is reserved for circuits where all silicon layers can be optimized. This implies a long design process and thus full custom is mainly used for high-volume high- end circuits. Page 2

3 What is an ASIC? An ASIC (Application Specific Integrated Circuit) is an integrated circuit for a specific application and (generally) produced in relatively small volumes (batches of 10 to units). A typical ASIC is a circuit, where functions are designed by the customer, and layout and the fabrication is done by the silicon vendor. An ASIC technology helps to shorten the design time by providing a semi-fabricated integrated circuit. Not ASICs: General-purpose processors, memory chips and other standard components. Page 3

4 ASIC Vs. Standard IC Standard ICs: Typically low component cost Parts available off the shelf Proven component reliability Multiple sourcing System house not required to have in-house experts in chip design Examples: chipsets, telecom ICs, processors, interface ICs, logic ICs, memory circuits. ASICs: Good security of intellectual property Optimum system design Relatively efficient use of board space (smaller systems) Reliability enhanced at system level (fewer (ewe components) Performance may be better than comparable standard ICs (unique features and lower power consumption) Reduced cost for storage (less components to store) Design cost is high h and design cycle is long Page 4

5 ASICs Advantages and Disadvantages Advantages Efficient use of board space (lower final system cost) Product security Unique features and fine-tuning the product Optimized system performance Possible product differentiation Disadvantages Potential for design failure Not off-the the-shelf available (specification, design, testing ti and documentation phases are needed) High unit cost of IC (higher initial costs of development) Page 5 of 32

6 ASIC vs the Rest Energy Efficien ncy: MO OPS/mW Dedicated HW (ASICs) Reconfigurable Processor/Logic ASIPs DSPs Embedded Processors Flexibility Page 6

7 ASIC Tasks and Roles System Designer, Architect System Level Functional Specification, Architectural Specification Performance and Power Consumption Specification Partitioning across domains RF/Analog, Digital, Software Estimates Block Level Partitioning, Interfaces Memory and Interconnect Hierarchy Power Management Strategy Chip Level Planning Package, Pads, I/O Preliminary Floorplan Global Control and Timing Clock and Reset strategy DFT Strategy Startup and Boot Sequence Page 7

8 ASIC Tasks and Roles (cont d) Logic Designer Block Level Design Detailed Block Level Design Specification Synthesis and hand-off of a timing clean block Exhaustive block level verification with near perfect code coverage Verification Engineer Verification Plan Modeling of Environment Verification Environment, Scripts, Regression DFT Engineer DFT logic Boundary Scan ATPG Page 8

9 ASIC Tasks and Roles (cont d) Front end ASIC Engineer Chip Level Synthesis Strategy Synthesis Scripts Timing Analysis Interface to backend Back end ASIC Engineer Floorplanning Place and Route Clock Tree Synthesis Power routing Pads and Package Integration and Test Page 9

10 1. Requirements Capture ASIC Project Phases Market Survey, Business Opportunities, Customer Interaction Requirements Specification CRS (Customer Requirements Specification) 2. PreStudy Hierarchical list of requirements Peformance, Cost and Delivery Schedule Estimate Die Size, Package, Power Consumption, Performance, Development, Manufacturing, Integration and Test Times Buy or Develop Decisions Explore architectural and algorithmic alternatives Interact with Customer, Marketting and refine Requirements doc. Quit or go ahead decision Page 10

11 ASIC Project Phases (cont d) 3. System Design 4. Implementation ti Design and Verification 5. Integration & Test 6. Maintenance Page 11

12 Design Requirements Technology-driven: Greater Complexity Higher Density Increased Performance Lower Power Dissipation Market-driven: Shorter Time-to-Market (TTM) Average TTM constraint is about 8 months. Missing the market window is very costly. Lower cost Non-Recurring Engineering (NRE) cost,volume sensitive Manufacturing and test cost Page 12

13 Complexity Architecture Efficacy Gap Architecture Trends Design Productivity Gap Methodology Trends Power Capacity Gap Power Management Trends Page 13

14 Design criteria Three dimensions: area, delay, power size, speed, energy consumption Four dimensions: plus testability (reliability) Area: gates, wires, buses, etc Delay: inside a module, between modules, etc Power consumption: average, peak and total t Optimizations: transferring from one dimension to another design quality is measured by combined parameters, e.g., energy consumption per input sample Page 14

15 Full-Custom ASIC An engineer designs some or all of the logic cells, circuits, layout specifically for one ASIC. Excellent performance, small size, low power Demands long design cycle High NRE cost Mostly used: If no pre-designed cells are available (e.g., new or highly specialized circuit) When high performance is needed, and existing cell libraries are not suitable Are slow, or not small enough, or consume too much power Requirements for high-voltage (automobile), mixed analog/digital (communications), or sensors and actuators Page 15

16 Cell-based IC (CBIC) Standard-Cell ASICs Use predesigned d logic cells (known as standard d cells) and larger cells, called megacells or cores (e.g. microcontroller) The standard cell library defines logic elements of varying complexity: SSI, MSI logic, data path blocks, memories and system-level blocks. Standard cells are built by someone else using full-custom design techniques Designers save time, money, and reduce risk by using a predesigned, pretested cell library Each standard cell can be optimized individually All mask layers are customized (transistors and interconnect) Custom blocks can be embedded Manufacturing lead time is about 2 months Page 16

17 Standard-Cell ASICs (example) Cells are configured in rows and have constant height and variable width A cell library holds relevant information about cells Name, functionality, delays, resistance, capacitance, layout, area, pin topology, etc. All cells in a library have same standardized layouts, i.e., all cells have the same height. Page 17

18 Gate-Array ASICs A gate-array array chip contains prefabricated adjacent rows of PMOS and NMOS transistors. Interconnect is defined by designer and fabricated using a custom mask (masked gate array or MGA) Called personalization Designer chooses cells from a gate-array array library of predefined, pretested cells Chip is partially fabricated (cells, power, etc. added) and then stockpiled When design is received for fabrication, the remaining metal layers are added Cheaper everyone shares cost of producing high volume of initial chip Quick turn-around days, couple weeks Sharif University of Technology Introduction to ASICs Page 18

19 + Low manufacturing cost Gate Array Features Due to the high yield of MPGAs (only 4 masking steps are involved in personalization: one for each of the two metal layers and two for placing contacts on these layers). More metal layers to improve the routability results in lower yield, thus adversely affects the manufacturing cost Difficult layout Vertical and horizontal channels can accommodate only a fixed number of wires. Automatic layout generator can easily create congestion by trying to place strongly connected cells close, thus exceeding the wiring capacity of the channels. Floorplanning is also difficult because of the rigid array structure. All cells have to be designed to meet the size constraint imposed by the array structure. Sharif University of Technology Introduction to ASICs Page 19

20 Gate Array Features (cont d) Difficult to estimate performance Because of the limited it routing capacity, it is difficult to estimate t the wire delays of gate array designs before routing is done. Gate count and utilization Gate utilization is always less than the specified capacity. strongly dependent on the type of design (structured or random) and the gate array architecture. Gate array capacities come in discrete sizes, typically differing in 35% steps most gate array designs will not utilize the complete capacity. Page 20

21 Channeled Gate Array Only the interconnect is customized The interconnect uses predefined spaces between rows of base cells Manufacturing lead time is between two days and two weeks Page 21

22 Channel-less less Gate Array Also known as sea-of-gate (SOG) array Only some mask layers are customized: the interconnect Cells are connected via unused transistors no predefined channels (over the cell routing) utilizes the active silicon poorly, but allows higher density of gates. Manufacturing lead time is between 2 days and 2 weeks Page 22

23 Field Programmable Gate Arrays None of the mask layers are customized Basic logic cells and interconnect can be programmed Basic cells can be SRAM-based, flash-memory- based or fuse-based (one time programmable), and can implement combinational, as well as sequential logic Programmable I/O cells surround the core Page 23

24 Programmable Logic Devices Standard ICs, available in standard configurations, sold in high volume But can be configured / programmed to create a specialized device No customized cells or masks, just a single large block of programmable interconnect fast design turnaround a single large block of programmable interconnect a matrix of logic macrocells that usually consist of programmable array logic followed by a flip-flop flop or latch Page 24

25 Prototyping Possibility to check how a system works at conditions very close to the operating environment without the need to create expensive chips XESS Corp., $400 [ Xilinx Inc., FPGA XC2S100 ] ErST Electronics, $3380 [ Xilinx Inc., FPGA X2V ] Page 25

26 Comparison Page 26

27 Comparison (cont d) ASIC type Family member Custom mask layers Custom logic cells Analogue Full-custom Analog/digital All Some A pizza built from scratch Semicustom CBIC MGA All Some None None A pizza built from predefined selection A garden pizza with cheese option Programmable FPGA PLD None None None None A frozen pizza Adapted from professor Robert A. Walker s (Kent University) VLSI Design course web site Page 27

28 In terms of part cost: FPGA > MGA > CBIC In terms of product cost: fixed part cost + variable cost per part * sales volumes Economics of ASICs Example (using imaginary costs): FPGA: $21 21,800 (fixed) $39 (variable) MGA: $86 86,000 (fixed) $10 (variable) CBIC $ ,000 (fixed) $8 (variable) Then we can calculate the following break-even even volumes: FPGA/MGA» 2000 parts FPGA/CBIC» 4000 parts MGA/CBIC» 20, parts Sharif University of Technology Introduction to ASICs Page 28

29 ASIC fixed costs training i cost (EDA tools) hardware/software cost design for test nonrecurring- engineering i (NRE) cost masks simulation test program software tools design verification prototype samples Economics of ASICs Page 29

30 ASIC variable costs wafer size wafer cost gate density gate utilization die size =(#gates/util util)/density die per wafer defect density yield die cost profit margin price per gate part cost Economics of ASICs Page 30

31 Economics of ASICs For any new process technology, the price per gate decreases by 40% in the 1st year, 20% in the 2nd year, and then remains constant A new process technology is introduced every 2 years with feature size decreasing by a factor of 2 every 5 years. CBICs and MGAs are introduced at the same time and price The price of a new technology is initially 10% above the process that it replaces FPGAs are introduced one year after CBICs using the same process Initial FPGA price is 10% higher than the initial price for CBICs or MGAs using the same process Page 31