SEMI Test Methods under Development for Si Feedstock Materials, Bricks and Wafers Peter Wagner

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1 SEMI Test Methods under Development for Si Feedstock Materials, Bricks and Wafers Peter Wagner

2 Background SEMI Test Methods are an essential part of SEMI Standards. They are referenced in material specifications. They help to establish common understanding of metrics, of measurement procedures and of measurement results. So far, 7 out of 33 published SEMI PV Standards are Test Methods Several new test methods are currently developed Materials, Bricks and Wafers, Munich, June

3 Published SEMI Test Methods SEMI PV1-0211, Test Method for Measuring Trace Elements in PV-Grade Si by High-Mass Resolution Glow Discharge Mass Spectrometry SEMI PV9-0611, Test Method for Excess Charge Carrier Decay in PV Si Materials by Non-Contact Measurement of Microwave Reflectance after a Short Illumination Pulse SEMI PV , Test Method for Instrumental Neutron Activation Analysis SEMI PV , Test Method for Contactless Excess-Charge-Carrier recombination Lifetime Measurement in Si Wafers, Ingots, and Bricks Using an Eddy-Current Sensor SEMI PV , Test Method for Mechanical Vibration of Crystalline Si PV Modules in Shipping Environment SEMI PV , Test Method for Simultaneously Measuring Oxygen, Carbon, Boron and Phosphorous in Solar Si Wafers and Feedstock by Secondary Ion Mass Spectrometry SEMI PV , Test Method for Measuring Resistivity or Sheet Resistance with a Single-Sided Noncontact Eddy-Current Gauge Materials, Bricks and Wafers, Munich, June

4 Test Methods under Development(1) Doc 5330, NEW STANDARD: TEST METHOD FOR IN-LINE MEASUREMENT OF CRACKS IN PV SILICON WAFERS BY DARK FIELD INFRARED IMAGING (EU, passed technical review) Doc 5331A, NEW STANDARD: TEST METHOD FOR IN-LINE MEASUREMENT OF SAW MARKS ON PV SILICON WAFERS BY A LIGHT SECTIONING TECHNIQUE USING MULTIPLE LINE SEGMENTS (EU, passed technical review) Doc 5332A, NEW STANDARD: TEST METHOD FOR IN-LINE MEASUREMENT OF THICKNESS AND THICKNESS VARIATION OF SILICON WAFERS FOR PV APPLICATIONS USING CAPACITIVE PROBES (EU, passed technical review) Doc 5333, NEW STANDARD: TEST METHOD FOR IN-LINE MEASUREMENT OF WAVINESS OF PV SILICON WAFERS BY A LIGHT SECTIONING TECHNIQUE (EU, ballot planned for July 2012) Materials, Bricks and Wafers, Munich, June

5 Test Methods under Development(2) Doc 4675B, NEW STANDARD: TEST METHOD FOR THE MEASUREMENT OF ELEMENTAL IMPURITY CONCENTRATIONS IN SILICON FEEDSTOCK FOR SILICON SOLAR CELLS BY BULK DIGESTION, INDUCTIVELY COUPLED- PLASMA MASS SPECTROMETRY (NA, drafting) Doc 5394, NEW STANDARD: TEST METHOD FOR QSS MICROWAVE PCD MEASUREMENTS OF CARRIER DECAY AND LIFETIME (NA, drafting) Materials, Bricks and Wafers, Munich, June

6 Planned New Activities Doc xxxx, NEW STANDARD, TEST METHOD FOR IN-LINE CHARACTERIZATION OF PV SI WAFERS BY USING PHOTOLUMINESCNCE( EU, drafting) Doc xxxx, NEW STANDARD, TEST METHOD FOR IN-INE MEASUREMENT OF LATERAL DIMENSIONS OF SILICON WAFERS FOR PV APPLICATIONS (EU, drafting) Doc xxxx, NEW STANDARD; TEST METHOD FOR IN-LINE CHARACTERIZATION OF PV SILICON WAFERS REGARDING GRAIN SIZE (EU, drafting) Materials, Bricks and Wafers, Munich, June

7 Doc 5330, Purpose Silicon (Si) for PV applications contains a variety of micro- and macroscopic crystallographic defects and flaws that may impact the efficiency of a solar cells or the yield of a manufacturing line. Two categories of defects: Grown-in defects consisting of point defects (impurities, vacancies, selfinterstitials and their complexes), dislocations, grain boundaries, and precipitates/inclusions. Process induced defects consisting of chips/indents (surface and edge) and cracks (not to mention the surface itself). Inclusions, chips and cracks are detrimental for solar cell processing as they may enhance stress in the wafer bulk and the region surrounding them and trigger the breakage of a wafer. Defining a test method for reproducibly detecting and characterizing cracks and distinguishing them from other defects to avoid quality issues and improve claim handling. Materials, Bricks and Wafers, Munich, June

8 Doc 5330, Scope This test method characterizes cracks in single or multi-crystalline Si wafers. It covers an in-line, non-contacting and non-destructive method that determines the number of cracks per wafer and crack length of clean, dry as-cut Si wafers that are supported by two belts that move the test specimen through the measurement equipment. This test method covers square and pseudo-square PV Si wafers, with a nominal edge length 125 mm and a thickness 100 µm. Because this test method is intended for in-line high throughput measurements it is mandatory to operate the measurement system under a tight SPC (e.g. ISO 11462) for obtaining reliable, repeatable and reproducible measurement data. Materials, Bricks and Wafers, Munich, June

9 Doc 5330, Apparatus digital line cameras Schematic drawing of the Set-up for Measuring Cracks Showing Projector Positions for Method A wafer (Projector below Wafer) and Method B (Projectors besides Wafer) projector besides wafer a projected light strip projector besides wafer wafer transport direction projector below wafer surface normal and line of sight of camera Materials, Bricks and Wafers, Munich, June

10 Doc 5330, Image Processing Steps Step 1 Step 2 Step 3 Step 4 Step 5 Edge detection and filtering Detection of potential defects Segmentation Identification and classification of defects Comparison and final decision Outline of the Flow of the Image Processing Steps Materials, Bricks and Wafers, Munich, June

11 Doc 5331, Purpose Silicon (Si) wafers for PV applications cut from a Si ingot or Si brick by multiple-wire sawing contain artifacts characteristic for this cutting process, so called saw marks. Saw marks may significantly impact the quality of wafers. They interfere with printing the contact fingers on solar cells. Extreme saw mark dimensions may interrupt the contact fingers or create too wide fingers. Saw marks are frequently specified for Si wafers for solar cells with respect to their maximum peak-to-valley within a finite distance, or window. Standardized test methods providing reproducible values for saw marks are required to specify this aspect of wafer quality. Process and quality control during manufacturing of wafers requires continuous monitoring of saw marks with a non-contact method that supports high throughput. Materials, Bricks and Wafers, Munich, June

12 Doc 5331, Scope Determining maximum peak-to-valley of saw marks that typically run across the entire wafer surface and along the wire direction. Applying to square and pseudo-square PV Si wafers, single and multicrystalline, with a nominal edge length 125 mm and a nominal thickness 100 µm. Intended for in-line, non-conctact, non-destructive high throughput measurements. Therefore it is mandatory to operate the measurement system under statistical process control (SPC, e.g. ISO 11462) in order to obtain reliable, repeatable and reproducible measurement data. Based on a light sectioning technique where the saw marks are oriented perpendicular to the direction of wafer transport. Materials, Bricks and Wafers, Munich, June

13 Doc 5331, Apparatus digital cameras projector projector Schematic View of the Upper Part of the Measurement Set- Up projected light line segment pattern A with a single line segment scan line FR a saw marks scan line FL D projected light line segment pattern A with two parallel line segments wafer wafer transport direction transport belts Materials, Bricks and Wafers, Munich, June

14 y/a.u. Doc 5331, Data Processing Illustration of the Processing Steps for Evaluating the Peak-tovalley Value from the Digital Image of the Light Line Trace Image of light line segment COB line and spline fit (dashed) subtraction of spline fit from COB line moving average filter maximum peak-to-valley peak-to-valley evaluation -> t i,j,n (x) t th x/a.u. Materials, Bricks and Wafers, Munich, June

15 Doc 5332, Purpose Wafer thickness and its variation across a wafer are important parameters for solar cell manufacturing. Excessive thickness variations within a lot from wafer to wafer or within a wafer may negatively impact process yield and solar cell efficiency. Both parameters are part of the specification for solar cell wafers (SEMI PV22), which define a thickness range as well as an upper limit for the total thickness variation (TTV). In addition, careful process and quality control of the wafer thickness and its variation during wafer and solar cell manufacturing requires continuous monitoring of thickness by the supplier of wafers for PV applications as well as by the user of such wafers. Therefore a standardized test method providing reproducible data for thickness and its variation is required to establish agreement between business partners regarding the specification of wafers. Materials, Bricks and Wafers, Munich, June

16 Doc 5332, Scope In-line, non-contact, non-destructive measurement of the thickness and the TTV of clean, dry silicon (Si) wafers supported on two belts that move the test specimen through the measurement equipment. Applicable to square or pseudo-square multi- as well as single-crystalline Si wafers in the resistivity range 10-3 W cm to 10 5 W cm with edge length 125 mm and with thickness 100 µm. Based on simultaneously measuring the capacitance between an aligned pair of capacitive probes and the wafer surfaces when the wafer passes through the gap formed between the capacitive probe pair. The test method does not cover measurement of surface flatness, warp, bow or sori of wafers. The test method is intended for in-line high throughput measurements. Therefore it is mandatory to operate system under tight statistical process control (SPC), e.g. ISO 11462, in order to obtain reliable, repeatable and reproducible measurement data. Materials, Bricks and Wafers, Munich, June

17 Doc 5332, Apparatus(1) CL = SL b Schematic Drawing of l 2 l 1 l 1 l 2 the Set-Up of the Capacitive Probes, Top capacitive probe A capacitive probe B capacitive probe C View of the Bottom l 3 Probes. The Gray Areas Depict the Active Areas of the Capacitive Probes. light sensors or emitters, respectively wafer transport direction light sensors or emitters, respectively wafer l 3 light sensors or emitters, respectively SL a SL c Materials, Bricks and Wafers, Munich, June

18 Doc 5332, Apparatus(2) SL a SL c l 3 +e OD l 3 +e l 3 OD OD Measurement Positions for 5- Point (Triangles) and 9- Point (Circles) Measurements. The Crosses Depict the First and Last Measurement Points as well as the Center Points on the Scan Lines. CL l 2 OD OD l 3 +e OD l 3 +e l 2 l 3 CL = SL b wafer transport direction Materials, Bricks and Wafers, Munich, June

19 Doc 5332, Metrics 3 line scans Offset distance OD entire line Area selected points thickness Measure thickness variation thickness Measure thickness variation Thickness Metrics Decision Tree L3TA L3VA L3T5 5 Number 9 5 Number 9 of of points points 1 L3T9 L3V5 L3V9 L3TC Materials, Bricks and Wafers, Munich, June

20 THANK YOU FOR YOUR KIND ATTENTION Materials, Bricks and Wafers, Munich, June