MIPI Verification Made Easy

Transcription

1 MIPI Verification Made Easy Jitendra Puri (JP) nsys Design Systems Member-to-Member Presentations March 9,

2 Legal Disclaimer The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled by any of the authors or developers of this material or MIPI. The material contained herein is provided on an AS IS basis and to the maximum extent permitted by applicable law, this material is provided AS IS AND WITH ALL FAULTS, and the authors and developers of this material and MIPI hereby disclaim all other warranties and conditions, either express, implied or statutory, including, but not limited to, any (if any) implied warranties, duties or conditions of merchantability, of fitness for a particular purpose, of accuracy or completeness of responses, of results, of workmanlike effort, of lack of viruses, and of lack of negligence. ALSO, THERE IS NO WARRANTY OR CONDITION OF TITLE, QUIET ENJOYMENT, QUIET POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH REGARD TO THIS MATERIAL. All materials contained herein are protected by copyright laws, and may not be reproduced, republished, distributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express prior written permission of MIPI Alliance. MIPI, MIPI Alliance and the dotted rainbow arch and all related trademarks, tradenames, and other intellectual property are the exclusive property of MIPI Alliance and cannot be used without its express prior written permission. IN NO EVENT WILL ANY AUTHOR OR DEVELOPER OF THIS MATERIAL OR MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL, CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR ANY OTHER AGREEMENT RELATING TO THIS MATERIAL, WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. 2

3 nsys Your Verification Partner Largest company with sole focus on Verification IPs and Services leveraging them Products & Services based upon specialized knowledge of I/O standards & tools Observer of Standard Working Groups viz. PCIe, SAS, Accellera, SDIO, USB-IF etc. Standards knowledge Hi Lo Fabless Semiconductor Or System \ Houses nsys EDA Vendors Value Proposition Accelerating customers designs by delivering Zero-defect Verification IPs Lo Hi Tools & Methodologies 3

4 nsys Verification IPs: nvs PCIe nvs Gen 3/ 2/ 1 ATAPI nvs Ethernet nvs 100/40/10/1G Defined SR-IOV nvs SATA 3.0 nvs SPI 4.1 nvs nvs : nsys Verification Suite Largest product portfolio in industry PCI-X nvs SAS 3.0 nvs Interlaken nvs Highest quality Verification IPs Features PCI family Storage ARM AMBA Communicatio n AMBA AXI nvs AMBA AHB nvs AMBA APB nvs Extensive error injection capabilities Consistent usage experience across nvs family to lower training costs Mobile MIPI User Logic USB port Other interfaces USB 3.0 nvs USB 2.0 nvs SDIO nvs UART nvs I 2 C nvs SMBus nvs Deliverables Validated nvs consisting of BFM, Monitor & Checker Test Suites in source code Basic, Error, Random, Compliance, Functional Coverage 4

5 MIPI HSI nvs: Overview MIPI BFM Agent MIPI Bus-Monitor MIPI DUT Compliant to MIPI HSI Physical Layer Version / 1.0 Available in SystemVerilog (UVM /OVM/ VMM) and Verilog Consistency of interface, operation, and documentation across nvs family Supports extensive error-insertion and error-detection capabilities 5

6 Data Link Layer MIPI HSI nvs: Key Features Supports all control channel commands (32-bit) Supports programmable number of channels for data transfer Supports programmable PDU lengths from 0 to 256 KB User-configurable timeout for power-on procedure Support for QoS procedures as per the data transfer profiles Supports programmable CRC trailer frame Physical Layer Supports Frame & Stream Transmission Mode Supports up to 15 Run-Time Configurable Data-Channels Supports Synchronized, Pipelined and Receiver Real time data flow modes 6

7 MIPI HSI nvs: Deliverables Bus Functional Model (BFM) / Agent Bus-Monitor Traffic Monitoring Protocol Checking Test Suites (Sequences) Compliance Suite (Optional) Functional Coverage (Optional) 7

8 MIPI HSI nvs: User Interface Transaction Class 8

9 MIPI HSI nvs: Bus-Monitor (Raw log) 9

10 MIPI HSI nvs: Bus-Monitor (PL log- Full duplex) 10

11 MIPI HSI nvs: Bus-Monitor (TR log) 11

12 MIPI HSI nvs: Sequences (sample) 12

13 MIPI HSI nvs: Coverage Coverpoints to track the traffic flow in both directions Extensive coverage bins Transfer Type Packets Commands State Transitions Functional Checkpoints 13

14 nvs Advantages Available in native SystemVerilog (UVM/OVM/VMM) & Verilog Option of Licensed Source Code Availability of Compliance & Functional Coverage Test Suites Proven expertise in Domain & Verification Methodology Direct handling of customer queries by the design team Full Support for customization or proprietary features Ease of approach for any help via Support Portal 14

15 Thank You Accelerating designs nsysinc 15