Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs

Transcription

1 Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs July 2007, v1.0 Application Note 463 Overview Introduction f This application note describes the differences between Stratix II FPGA and HardCopy II structured ASIC implementation requirements for the ALTMEMPHY based DDR and DDR2 SDRAM external memory interfaces. This application note is best read before beginning Stratix II FPGA or PCB design, but assumes basic familiarity with the Altera external memory intellectual property (IP), tools, and methodology. This familiarity can be gained by reading the documents referenced in the introduction. Altera s ALTMEMPHY megafunction is a physical layer (PHY) of an external memory interface. The ALTMEMPHY megafunction greatly reduces the need for logic designers to manually create and verify the complex timing relationships required when interfacing to DDR and DDR2 SDRAM devices. The ALTMEMPHY megafunction handles many of the technology specific elements of a memory interface, allowing designers to be more productive by letting them focus on creating and verifying their custom logic designs. For more information, see the ALTMEMPHY Megafunction User Guide. Altera s high-performance controller megacore pairs the ALTMEMPHY megafunction with matching memory controller state machines (control logic), allowing logic designers to control large amounts of external memory through a relatively simple local interface (Figure 1). Figure 1. System-Level Diagram Utilizing DDR2 SDRAM High-Performance Controller Altera Devices DDR2 SDRAM High Performance Controller Application Specific Logic Local Interface Memory Controller (aka "Control Logic") ALTMEMPHY Megafunction DDR2 SDRAM Enhanced PLL Master DLL Slave DLLs Altera Corporation 1 AN Preliminary

2 Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs f For more information about Altera s High-Performance Controllers, refer to the DDR and DDR2 SDRAM High-Performance Controller User Guide. External Memory Interface Standards Table 1 shows the ALTMEMPHY megafunction supported DDR and DDR2 memory interfaces for use with HardCopy II structured ASICs. Table 1. Supported External Memory Interface Standards for HardCopy II Structured ASICs Memory Type ALTMEMPHY and High-Performance Memory Controller Legacy Integrated Static Data Path and Controller DDR SDRAM Supported Legacy support DDR2 SDRAM Supported Legacy support RLDRAM II Not supported Supported QDR II/+ SRAM Not supported Supported To implement external memory controllers for RLDRAM II and/or QDR II /+ SRAM, use the Legacy Integrated Static Data Path And Controller. f For more information about the Legacy Integrated Static Data Path and Controller, and its use with HardCopy II structured ASICs, refer to AN 413: Using Legacy Integrated Static Data Path and Controller Megafunction with HardCopy II Structured ASICs. This document focuses on the use of a single ALTMEMPHY instance. Stratix II FPGA and HardCopy II structured ASIC devices may also instantiate multiple memory controllers in a single device. While planning a design with multiple external memory interfaces, keep in mind the hardware limitations of the device, including the required sharing of a single master DLL for memory interfaces on the same edge of the device. This limitation implies that memory controllers on the same edge of the device should operate at the same frequency. Logical netlist connections need to be made manually to share the output of the master DLL. f For more information about using multiple ALTMEMPHY instances in a single design, refer to AN 462: Implementing Multiple Memory Interfaces Using the ALTMEMPHY Megafunction. 2 Altera Corporation JJuly 2007

3 HardCopy II Structured ASIC Specific Design Requirements HardCopy II Structured ASIC Specific Design Requirements HardCopy II structured ASICs have specific requirements with regard to external memory interface implementation. Some of these requirements are not enforced when using Stratix II FPGAs without HardCopy II structured ASIC compatibility. Generally, requirements specific to HardCopy II structured ASICs serve to augment the robust operation of the design and reduce the risk of design errors, at the cost of incremental engineering effort. Table 2 summarizes the requirements for HardCopy II structured ASICs. These requirements are more stringent than those for Stratix II FPGAs. Each requirement in Table 2 is also explained, following the table. Table 2. Summary of HardCopy II Structured ASIC versus Stratix II FPGA Requirements Note (1) Category HardCopy II Structured ASIC Stratix II FPGA PLL reconfiguration user access Required Optional Clock uncertainty Required Optional PLL reference clock pin Clock Input Corresponding to PLL from Table 4 Any Clock Input Memory clock pin location IOBANK 9-12 (depending on device and PLL location, see Table 4) Anywhere Memory clock output PLL dedicated clock output DDIO output (1) Supported performance specification Depends on package type and range of operating conditions Depends on device speed grade Note to Table 2: (1) PLL dedicated clock output is allowed, but only recommended for designs which also target HardCopy II structured ASICs. Phase-Locked Loop (PLL) Reconfiguration User Access Because HardCopy II structured ASICs are not reprogrammable, you must build reconfigurable PLL phase tuning capability into your design. HardCopy II structured ASIC designs must select Enable external access to reconfigure PLL prior to calibration when creating ALTMEMPHY variations in the Quartus II IP MegaWizard. Clock Uncertainty Clock uncertainty is budgeted as part of timing closure for HardCopy II structured ASICs. By including this uncertainty budget, HardCopy II Altera Corporation 3 July 2007

4 Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs designs achieve high performance and robust operation. This is achieved by modeling the specific PLL configuration used, and avoiding the need to excessively guard-band the cell and interconnect delay models to account for unused configurations. Because HardCopy II structured ASICs are designed once, then deployed in volume at low cost, the one-time engineering effort to include the clock uncertainty budget is well justified. 1 For further information about clock uncertainty in HardCopy II structured ASICs, refer to the HardCopy II Clock Uncertainty Calculator User Guide. Dedicated PLL Reference Clock Pins Dedicated PLL reference clock pins are used to improve the quality of the reference clock provided as the input to a PLL. When pins other than a PLL s corresponding dedicated clock input pins are used to provide a reference clock to a PLL, the reference clock must be routed inside the device via a global clock resource to arrive at the reference pin of the PLL. The reference clock signal may accumulate noise (for example, jitter) as it travels along this clock network. Because HardCopy II structured ASICs cannot be reconfigured, it is important to use the highest quality reference clock possible for timing critical paths such as those of external memory interfaces. Therefore, dedicated PLL reference clock input pins, which provide the shortest path to the PLL, are required for external memory interface reference clocks in HardCopy II structured ASIC devices. Dedicated PLL Clock Outputs (Including Pin Location and Logic Structure) The differential output memory clock is a critical memory interface signal. To minimize the jitter of this output clock, use a direct PLL output to pad path. When properly configured, the direct PLL output to pad path allows the memory clock to bypass the device s global routing resources, which reduces the potential for accumulated noise on the clock output. The memory clock signals must also be assigned to differentially matched pin pairs within the isolated PLL output clock banks (IOBANKS 9-12). The specific IOBANK used must correspond to the PLL which generates the output clock (see Table 4). Each PLL output clock bank contains three pin pairs. 4 Altera Corporation JJuly 2007

5 HardCopy II Structured ASIC Specific Design Requirements The use of dedicated PLL clock outputs requires phase alignment of the output clock to meet the SDRAM timing requirements relative to the memory clock. This process is illustrated in the design walkthrough later in this application note. Supported Performance Specification HardCopy II structured ASICs have different maximum supported operating frequencies, compared to Stratix II FPGAs (Table 1). Although the I/O cells are equivalent to those of Stratix II FPGAs (minus in-system reconfiguration), there are two important differences between Stratix II FPGAs and HardCopy II structured ASICs, which lead to performance differences: 1. Wire bond packaging HardCopy II structured ASICs are available in wire bond or flip chip packages. Because of the impact of simultaneous switching output (SSO) noise and lead inductance, wire bond packages have lower supported operating frequencies compared with their flip chip counterparts. 2. No speed binning Because HardCopy II structured ASICs are customized to your specific design, and are intended to be cost effective, they are not speed binned (in contrast to Stratix II FPGAs). Therefore, the very fastest speed grade of Stratix II FPGAs has no equivalent in the HardCopy II structured ASIC product family, since this bin represents only the very fastest parts produced and excludes all others. Another notable impact of the lack of speed bins is different performance between HardCopy II structured ASICs intended for commercial operating conditions versus industrial operating conditions. Stratix II FPGAs are able to maintain I/O performance at industrial conditions by maintaining a narrower process band, thus reducing the percentage of acceptable devices produced. In contrast, HardCopy II structured ASICs keep costs contained by accepting a wider range of process parameter values, but this requires limiting the performance of industrial grade parts. Altera Corporation 5 July 2007

6 Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs Table 3. Supported External Memory Performance (MHz) Note (1), and (2) Flip Chip Wire Bond (1) Device DDR DDR2 DDR DDR2 Stratix II Stratix II Stratix II HardCopy II - Commercial HardCopy II - Industrial Notes to Table 3: (1) For example, HC210W. (2) The supported operating frequencies listed above are technology maximums. Your design s actual achievable performance is based on design and system specific factors, as well as static timing analysis of the completed design. Before Beginning FPGA and/or PCB Design Choosing PLLs and Package Pins Possibly the most important consideration prior to FPGA or PC board design is the choice of package pins. The ability to achieve pin compatibility between Stratix II FPGAs and HardCopy II structured ASICs is predicated on choosing the right package pins for each signal. Before beginning your Stratix II FPGA, HardCopy II structured ASIC, or PC board design, select which enhanced PLL resources and I/O pin banks will be used for your external memory interface (Table 4). 6 Altera Corporation JJuly 2007

7 Before Beginning FPGA and/or PCB Design Table 4. ALTMEMPHY Megafunction Pre-Stratix II Development Resource Planning for HardCopy II Compatibility Note (1) Enhanced PLL Dedicated PLL CK/CK# Pins Primary DQ/DQS Pin Location Location (1) HC 210/210W/220 Compatible? PLL_5 IOBANK_9 IOBANK_4 Top-right Yes PLL_6 IOBANK_10 IOBANK_7 Bottom-right No PLL_11 IOBANK_11 IOBANK_3 Top-left Yes PLL_12 IOBANK_12 IOBANK_8 Bottom-left No Note to Table 4: (1) Altera s documentation shows PLL and pin locations as they appear from the package bottom. When using Pin Planner in the Quartus II software, choose View, Show, and then Package Bottom to match this orientation. w In the chart above, using IOBANK_3 can create voltage level compatibility problems if your Stratix II FPGA design uses EPCS configuration devices in user mode (for example, to hold boot software for a NIOS II processor). This is due to the presence of the shared user/configuration pins in IOBANK_3. Be sure to check the voltage level requirements of your configuration device with your IOBANK_3 voltage assignments. PC Board Level Considerations The fact that HardCopy II structured ASICs are configured by custom metal masks, and therefore are not reconfigurable in-system, makes considering device and PCB interaction even more critical than it is with a reconfigurable Stratix II FPGA. Be sure to familiarize yourself with the issues and recommendations for both PCB design and settings for your Altera device by reading the following documents prior to finalizing your PCB or logic design: AN 408: DDR2 Memory Interface Termination, Drive Strength and Loading Design Guidelines AN 444: Dual DIMM DDR2 SDRAM Memory Interface Design Guidelines Altera Corporation 7 July 2007

8 Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs ALTMEMPHY Related Licensing If you do not have the proper license, the Quartus II software defaults to an evaluation version of the DDR or DDR2 SDRAM high-performance memory controller. The evaluation version is not HardCopy II compatible. 1 Timing closure of both Stratix II FPGA and HardCopy II structured ASIC project revisions might need to be repeated if timing is closed initially with an evaluation version of the controller, and a full version of the controller is later used. For this reason, Altera recommends that you do not use the evaluation version of the controller for designs which target HardCopy II structured ASICs. Using ALTMEMPHY with SOPC Builder The ALTMEMPHY megafunction is available for use with SOPC Builder by instantiating the DDR or DDR2 SDRAM high-performance controller (ALTMEMPHY is, in turn, instantiated inside the high-performance controllers). The process of creating and customizing a controller variation is virtually identical, whether you are using the Quartus IP MegaWizard or the SOPC Builder tool. When a DDR or DDR2 SDRAM high-performance controller is added into the SOPC Builder, the same customization options are presented as in the Quartus IP MegaWizard. Design Walkthrough The following example design, with a single high-performance DDR2 SDRAM variation (called ahpmc ), targets a Stratix II FPGA/HardCopy II structured ASIC device pair. This simple case illustrates the basic principles of using the ALTMEMPHY megafunction with HardCopy II structured ASICs. Once you are familiar with the process, you can build on this example by creating a more customized variation, or adding the rest of your design. Figure 2 provides an overview of the basic example design flow. 8 Altera Corporation JJuly 2007

9 Design Walkthrough Figure 2. Design Walkthrough Flow Chart Stratix II FPGA Revision Setup Project Build IP Finish Binding IP to Project I/O Assignments Compile Stratix II FPGA Revision HardCopy II Structured ASIC Revision Create HardCopy II Structured ASIC Revision Compile HardCopy II Structured ASIC Revision Setup Project 1. In the Quartus II software, on the File menu, and click New Project Wizard (Figure 3). 2. Click Next after reading the introduction. Altera Corporation 9 July 2007

10 Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs Figure 3. New Project Wizard: Introduction 10 Altera Corporation JJuly 2007

11 Design Walkthrough 3. Fill in the values for the project name and top level (Figure 4): a. Project name: ahpmc_example_top b. Top-level: ahpmc_example_top 4. Click Next. Figure 4. New Project Wizard: Directory, Name, Top Level Entity Altera Corporation 11 July 2007

12 Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs 5. Skip adding files to the project. Click Next (Figure 5). Figure 5. New Project Wizard: Add Files 12 Altera Corporation JJuly 2007

13 Design Walkthrough 6. Configure the device and family settings for the project (Figure 6). Under Family, select Stratix II. Under Target Device, select Specific device selected in Available devices list. Select the following under Show in Available device list: a. Package: FBGA b. Pin Count: Any c. Speed Grade: 4 d. Show advanced devices: Checked e. HardCopy compatible only?: Checked f. Under Available devices, select EP2S130F1020C4 g. Under Companion device, select HC230F1020C h. Limit DSP and RAM to HardCopy II device resource: Checked 7. Click Next to confirm the device and family settings. Altera Corporation 13 July 2007

14 Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs Figure 6. New Project Wizard: Family and Device Setting 14 Altera Corporation JJuly 2007

15 Design Walkthrough 8. Skip EDA Tool Settings. Click Next (Figure 7). Figure 7. New Project Wizard: EDA Tool Settings Altera Corporation 15 July 2007

16 Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs 9. Click Finish after reviewing the new project summary (Figure 8). Figure 8. New Project Wizard: Summary 16 Altera Corporation JJuly 2007

17 Design Walkthrough Build IP In the Quartus II software: 1. Tools menu, click MegaWizard Plug-In Manager (Figure 9). 2. Select Create a new custom megafunction variation. 3. Click Next. Figure 9. Create a New Custom Megafunction The MegaWizard Plug-In Manager [page 2a] screen appears (Figure 10). 4. Under Select a megafunction from the list below: a. Select the Interfaces folder and then the Memory Controllers folder. b. Choose DDR2 SDRAM High Performance Controller v... w If you do not see the Interfaces option under Installed Plug-Ins, do not proceed. Instead, stop here and examine your Quartus II software installation for a problem with the IP installation. 5. For Which device family will you be using. select HardCopy II. 6. Under Which type of output file do you want to create. select Verilog HDL. 7. Under What name do you want for the output file, type /ahpmc.v after the name of the project directory. Altera Corporation 17 July 2007

18 Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs 8. Click Next. Figure 10. MegaWizard Plug-In Manager [page 2a] 1 After the Loading MegaWizard message, the window titled MegaWizard Plug-In Manager - DDR2 SDRAM High Performance Controller appears (Figure 11). 18 Altera Corporation JJuly 2007

19 Design Walkthrough Parameter Settings Memory Settings 1. For General Settings, complete the following (Figure 11): a. Device family: HardCopy II b. Speed Grade: 4 c. PLL reference clock frequency: MHz (3750 ps) d. Memory Clock Frequency: MHz (3750 ps) 1 The relationship between reference clock frequency and memory clock frequency impacts clock uncertainty values and therefore your design s performance. Optimal performance can be achieved when using the same frequencies. e. Local interface clock frequency: Half 1 The local interface clock frequency impacts design performance. The half rate option allows for higher I/O clock frequency and/or easier timing closure of memory control logic. 2. For Memory Presets, select: Qimonda HYS72T64000GU Click Next to confirm the memory settings. Altera Corporation 19 July 2007

20 Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs Figure 11. Memory Settings PHY Settings w The following two settings are critical HardCopy II structured ASIC requirements (Figure 12): 1. Turn on the Use dedicated PLL outputs to drive memory clocks box to enable this option. 2. Turn on the Enable external access to reconfigure PLL prior to calibration box to enable this option. 3. Turn on the Instantiate DLL externally box to enable this option. 20 Altera Corporation JJuly 2007

21 Design Walkthrough 1 This setting facilitates sharing the master DLL, which is necessary when placing multiple DDR controllers on the same side of a device. 4. In the Address/Command Clock Settings dialog box, choose clock phase: Click Next to confirm the PHY settings. Figure 12. PHY Settings Altera Corporation 21 July 2007

22 Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs Controller Settings 6. For the Local Interface Protocol option, select Avalon Memory-Mapped Interface (Figure 13). 7. Click Next to confirm the controller settings. Figure 13. Controller Settings 22 Altera Corporation JJuly 2007

23 Design Walkthrough Simulation Model 1. Turn on Generate Simulation Model (Figure 14). 2. For the Language option, choose Verilog HDL. 3. Click Next to confirm the simulation model settings. Figure 14. Simulation Model Altera Corporation 23 July 2007

24 Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs Summary 1. Check the files you wish to generate (Figure 15). 2. Click Finish after reviewing the summary page. Figure 15. Summary 3. The IP MegaWizard will spend a few minutes generating netlists, timing constraints for TimeQuest in Synopsys Design Constraints (.sdc) format, scripts, and report files (Figure 16). 4. Click Exit when the IP generation is complete. 24 Altera Corporation JJuly 2007

25 Design Walkthrough Figure 16. Generation - DDR2 SDRAM High Performance Controller 1 Note the Info messages, starting with Before compiling your variation in Quartus II, you should follow these steps:. Altera Corporation 25 July 2007

26 Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs Finish Binding IP to the Project Add Support for HardCopy II Clock Uncertainty To account for clock uncertainty inside the core logic (for example, the DRAM control logic and the example driver logic), create a constraint file called ahpmc_hcii_cu.sdc with the following contents: ### HardCopy II Specific: General (non-ddr specific) clock uncertainty set family $::TimeQuestInfo(family) if [string equal -nocase $family "HardCopy II"] { post_message -type info "Calculating HardCopy II Clock Uncertainty" derive_clock_uncertainty } Timing Analysis Settings On the Assignments menu, click Settings. Under Category select Timing Analysis Settings. 1. Under Timing analysis processing select Use TimeQuest Timing Analyzer during compilation (Figure 17). Figure 17. Timing Analysis Settings 26 Altera Corporation JJuly 2007

27 Design Walkthrough 2. In the Category list, select TimeQuest Timing Analyzer (Figure 18). 3. Include the constraint file ahpmc_phy_ddr_timing.sdc with the project. a. Click the ellipse button, and select the ahpmc_phy_ddr_timing.sdc file b. Click Open, and then click Add. 4. Include the constraint file ahpmc_hcii_cu.sdc with the project. a. Click the ellipse button, and select the ahpmc_hcii_cu.sdc file. b. Click Open, and then click Add. Figure 18. TimeQuest Timing Analyzer Altera Corporation 27 July 2007

28 Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs Fitter Settings 1. In the Category list, select Fitter Settings (Figure 19). 2. Under Fitter effort, choose Standard Fit (highest effort). 3. Click OK to confirm the project settings. Figure 19. Fitter Settings Implement HardCopy II Advisor Recommendations On the Project menu, point to HardCopy II Utilities and then HardCopy II Advisor. To set up Stratix II FPGA revision, follow these steps: (Figure 20): 1. Turn on Design Assistant. 2. Set up the timing constraints: a. Enable optimization of the hold time along all paths in the Fitter. 28 Altera Corporation JJuly 2007

29 Design Walkthrough b. Enable optimization of fast-corner timing in the Fitter. c. Enable Multicorner Analysis in the TimeQuest Timing Analyzer. 3. Check for incompatible assignments: a. Reserve all unused pins as inputs tri-stated with weak pull-ups. Figure 20. HardCopy II Advisor Add Support For Different PLL Settings in the HardCopy II Revision Add the following assignment to your Stratix II FPGA (.qsf) ahpmc_example_top.qsf file: # Explicitly include the HDL source file of the PLL set_global_assignment -name VERILOG_FILE ahpmc_phy_alt_mem_phy_pll_sii.v # Use a PLL with independent settings for Stratix II vs. HardCopy II revisions set_global_assignment -name MIGRATION_DIFFERENT_SOURCE_FILE ahpmc_phy_alt_mem_phy_pll_sii.v f For more information about using a different PLL in the HardCopy II structured ASIC revision of a design to allow for different PLL settings, refer to: AN 432: Using Different PLL Settings Between Stratix II & HardCopy II Devices. Altera Corporation 29 July 2007

30 Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs I/O Assignments I/O Electrical Standards 1. On the Quartus II software Tools menu, click Tcl Scripts... (Figure 21). 2. Under project, select ahpmc_pin_assignments. 3. Click Run to execute the Tcl script. Figure 21. Tcl Scripts I/O Location 1. From the Quartus II software, on the Assignments menu, and click Pin Planner (Figure 22). 1 Altera s documentation shows PLL and pin locations as they appear from the package bottom. When using Pin Planner in the Quartus II software, on the View menu, point to Show, and then click Package Bottom to match this orientation. 2. In the Quartus II software, on theview, Show, and then Package Bottom. 30 Altera Corporation JJuly 2007

31 Design Walkthrough 3. On the View, Show menu, point to Show Differential Pin Pair Connections. 4. On the View menu click All pins list. Figure 22. Pin Planner Memory Clocks Use Dedicated PLL Clock Output Pins Assign memory clocks to differential pin pairs in a PLL dedicated output bank (for example, IOBANK_9 for PLL_5). For this design, assign locations as follows: ## Dedicated PLL clock outputs set_location_assignment PIN_C16 -to mem_clk[0] set_location_assignment PIN_D16 -to mem_clk_n[0] set_location_assignment PIN_B15 -to mem_clk[1] set_location_assignment PIN_C15 -to mem_clk_n[1] set_location_assignment PIN_D15 -to mem_clk[2] set_location_assignment PIN_E15 -to mem_clk_n[2] PLL Reference Clock Pin 1. Assign clock_source, the PLL reference clock, to a dedicated PLL input pin. Altera Corporation 31 July 2007

32 Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs 2. Assign clock_source to a voltage level compatible with the other DDR2 SDRAM pins (1.8 v). For example: set_instance_assignment -name IO_STANDARD "1.8 V" -to clock_source set_location_assignment PIN_A16 -to clock_source 1 By choosing a PLL reference clock input pin in the correct location, the global clock resources can be avoided. Avoiding the global clock resources may result in a cleaner clock input to the PLL, due to reduced noise coupling. 1 The reference clock pin assignments serve to anchor the fitter. Without these assignments, or another set of assignments, the fitter may fail to place the design. 1 Once you are familiar with the process of generating the memory controller, it is important to assign explicit locations to all I/O pins. Without such assignments, the Quartus II software could move pins during fitting and timing closure could lack repeatability. Compile Stratix II FPGA Revision Perform a multi-pass compilation. The first pass will establish baseline timing reports. Then, clock phases will be tuned, based on the baseline timing. The second pass incorporates the tuned clock phases into a completed design. Additional iterations of clock phase tuning and recompiling may be necessary, if the second pass requires additional clock phase tuning. Compile Stratix II FPGA Revision First Pass 1. In the Quartus II software on the Processing menu, click Start Compilation. 1 The fitter will warn you about multiple output enable signals in each DQ/DQS group. It is safe to ignore these warnings. Align Memory Clock for the Stratix II FPGA Design Using the timing reports as a starting point, center the phase of the PLL s dedicated clock output in the Quartus II IP MegaWizard. 32 Altera Corporation JJuly 2007

33 Design Walkthrough Average Margin = The phase which will center the clock is determined by subtracting the worst setup margin from the arithmetic average of the setup and hold margins, and converting from nanoseconds to degrees. Thus, the equations for the correct phase are: 1 -- [ min ( setup_margin_slow, setup_margin_fast) + min( hold_margin_slow, hold_margin_fast )] degrees Phase = ( Average Margin setup_margin_slow) clock_period In the equation above, the phase value describes an absolute phase if the margin numbers on the right-hand side of the equation are those from timing analysis of a zero degree clock. The equation can also be used to calculate the amount of phase adjustment still needed if the timing margins result from analysis of a different clock phase. 1 If your design s average margin is less then zero, timing cannot be closed, regardless of your memory clock phase setting. 1 Timing margin numbers are reported in the compilation report s TimeQuest Timing Analyzer folder, and appear as numerical values in the "Slack" column. Update your PLL s phase settings in the Quartus II IP MegaWizard as follows: 1. On the Tools menu, click MegaWizard Plug-In Manager. 2. Choose Edit an existing custom megafunction variation and then click Next (Figure 23). Altera Corporation 33 July 2007

34 Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs Figure 23. Edit Existing Custom Megafunction Variation 3. Select the primary netlist for the PLL (ahpmc_phy_alt_mem_phy_pll_sii.v) and then click Next. 4. Select the Output Clocks tab at the top of the MegaWizard Plug-In Manager, and then select the clk c3 tab. (Figure 24). 34 Altera Corporation JJuly 2007

35 Design Walkthrough Figure 24. Tune Clock Phase 5. Revise the value of the requested setting of Clock phase shift to the value you previous calculated as your center value. 6. Note the phase under the Actual settings column; this is the closest value to your requested phase which the Quartus II software can implement. 7. Click Finish to exit the MegaWizard Plug-In Manager. Recompile Stratix II FPGA Design Second Pass 1. In the Quartus II software, on the Processing menu, click Start Compilation. 2. Check that all timing relationships were met before continuing. Altera Corporation 35 July 2007

36 Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs Compile HardCopy II Structured ASIC Revision Create a HardCopy II Revision 1. In the Quartus II software, on the Project menu, point to HardCopy II Utilities, and then click Create and Overwrite HardCopy II Companion Revision (Figure 25). 2. Click OK. Figure 25. Create HardCopy II Companion Revision Switch to HardCopy II Revision 1. In the Quartus II software, on the Project menu click Revisions. 2. Select ahpmc_example_top_hcii and click Set Current. 3. Click OK. 36 Altera Corporation JJuly 2007

37 Design Walkthrough Figure 26. Switch to HardCopy II Revision Include HardCopy II Specific PLL 1. Edit ahpmc_example_top_hcii.qsf to reflect the new PLL HDL source file for the HardCopy II revision, as shown in the following example: originally: # Explicitly include the HDL source file of the PLL set_global_assignment -name VERILOG_FILE ahpmc_phy_alt_mem_phy_pll_sii.v change to: # Explicitly include the HDL source file of the PLL set_global_assignment -name VERILOG_FILE ahpmc_phy_alt_mem_phy_pll_sii_ahpmc_example_top_hcii.v 1 This change may be automatic in a future version of the Quartus II software. Compile HardCopy II Revision First Pass 1. In the Quartus II software, on the Processing menu, click Start Compilation. Altera Corporation 37 July 2007

38 Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs 1 Because the design has not yet accounted for clock uncertainty, estimates of performance at this stage are optimistic. Align Memory Clock for HardCopy II Design Repeat the clock alignment process already performed on the Stratix II revision, but this time, select the netlist of the PLL for the HardCopy II revision (ahpmc_phy_alt_mem_phy_pll_sii_ahpmc_example_top_hcii.v) in the MegaWizard, rather than the PLL for the Stratix II revision (ahpmc_phy_alt_mem_phy_pll_sii.v). 1 The Quartus IP MegaWizard may change the HDL module name in the PLL netlist to match the file name of the netlist each time you edit the PLL settings for the HardCopy II structured ASIC. Ensure the module name in the PLL netlist matches the module name instantiated in your design. Recompile the HardCopy II Design Second Pass 1. In the the Quartus II software, on the Processing menu, click Start Compilation. 2. Check that all timing relationships were met. Add DDR Clock Uncertainty Constraints for HardCopy II Revision Once your design is finalized and meeting timing (including all PLL phase adjustments), it is time to consider the impact of your PLL setting on DDR interface timing. In TimeQuest, write PLLJ_PLLSPE_INFO.txt with the command: derive_clock_uncertainty -dtw Send this file to Altera. You will then be provided with a <variation>_cu.tcl script for each ALTMEMPHY instance in your design. For this example design, the following text can be saved as ahpmc_cu.tcl: ### Setup Uncertainty set fpga_tread_capture_setup_error 0 set fpga_resync_setup_error 0.07 set fpga_pa_dqs_setup_error 0.07 set WR_DQS_DQ_SETUP_ERROR 0.15 set fpga_tck_addr_ctrl_setup_error 0.19 set fpga_tdqss_setup_error 0 set fpga_tdssh_setup_error 0 38 Altera Corporation JJuly 2007

39 Conclusion ### Hold Uncertainty set fpga_tread_capture_hold_error 0 set fpga_resync_hold_error 0.07 set fpga_pa_dqs_hold_error 0.07 set WR_DQS_DQ_HOLD_ERROR 0.15 set fpga_tck_addr_ctrl_hold_error 0.19 set fpga_tdqss_hold_error 0 set fpga_tdssh_hold_error 0 Recompile HardCopy II Design Third Pass With the <variation>_cu.tcl scripts in place, re-analyze timing with TimeQuest. If desired, you can also re-run the whole compile process. Congratulations! You have built a DDR2 external memory interface which can be used with both Stratix II FPGAs and HardCopy II structured ASICs. Conclusion The ALTMEMPHY megafunction allows designers to incorporate external memory interfaces into their designs. To successfully use the ALTMEMPHY megafunction with HardCopy II, consideration must be given to the elements outlined in this application note prior to FPGA or PC Board design. Choosing package pins compatible with HardCopy II structured ASICs is especially critical. With the ALTMEMPHY megafunction and the guidelines presented in this application note, it is possible to create external memory interfaces compatible with both Stratix II FPGAs and HardCopy II structured ASICs. Using ALTMEMPHY not only makes designers more productive, it greatly reduces the risk associated with using different technology-specific IP from a different vendor, on a high-volume production ASIC versus that used on the prototype FPGA. Altera Corporation 39 July 2007

40 Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs Document Revision History Table 5 shows the revision history for this application note. Table 5. Document Revision History Date and Document Version Changes Made Summary of Changes June 2007 v1.0 Initial release 101 Innovation Drive San Jose, CA Technical Support: Literature Services: literature@altera.com Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 40 Altera Corporation Preliminary July 2007