Hybrid Prefix Adder Architecture for Minimizing the Power Delay Product

Transcription

1 Iteratoal Joural of Electrocs ad Commucato Egeerg Vol:3, No:4, 009 Hybrd Prefx Adder Archtecture for Mmzg the Power P.Ramaatha 1 ad.p.t.vaath Iteratoal Scece Idex, Electrocs ad Commucato Egeerg Vol:3, No:4, 009 waset.org/publcato/57 Abstract Parallel Prefx addto s a techque for mprovg the speed of bary addto. Due to cotug tegratg testy ad the growg eeds of portable devces, low-power ad hghperformace desgs are of prme mportace. The classcal parallel prefx adder structures preseted the lterature over the years optmze for logc depth, area, fa-out ad tercoect cout of logc crcuts. I ths paper, a ew archtecture for performg 8-bt, 16-bt ad 3-bt Parallel Prefx addto s proposed. The proposed prefx adder structures s compared wth several classcal adders of same bt wdth terms of power, delay ad umber of computatoal odes. The results reveal that the proposed structures have the least power delay product whe compared wth ts peer exstg Prefx adder structures. Taer EDA tool was used for smulatg the adder desgs the TSMC 180 m ad TSMC 130 m techologes. Keywords Parallel Prefx Adder (PPA), Dot operator, Sem-Dot operator, Complemetary Metal Oxde Semcoductor (CMOS), Odd-dot operator, Eve-dot operator, Odd-sem-dot operator ad Eve-sem-dot operator. I. INTRODUCTION LSI Iteger adders fd applcatos Arthmetc ad V Logc uts (ALU s), mcroprocessors ad memory addressg uts. Speed of the adder ofte decdes the mmum clock cycle tme a mcroprocessor. The eed for a Parallel Prefx adder s that t s prmarly fast whe compared wth rpple carry adders. Parallel Prefx adders (PPA) are famly of adders derved from the commoly kow carry look ahead adders. These adders are best suted for adders wth wder word legths. PPA crcuts use a tree etwork to reduce the latecy to O(log ) where represets the umber of bts. A three step process s geerally volved the costructo of a PPA. The frst step volves the creato of geerate, complemetary kll ad propagate sgals for all the put operad bts. G B (1) K + B B () P B (3) 1 P.Ramaatha s wth the PSG College of Techology as a Seor Lecturer Electrocs ad Commucato Egeerg Departmet, Peelamedu, Combatore , Tamladu, Ida (correspodg author phoe: ; fax: ; e-mal: pramaatha_000@yahoo.com). Dr.P.T.Vaath., s wth PSG College of Techology as a Assstat Professor Electrocs ad Commucato Egeerg Departmet, Peelamedu, Combatore , Tamladu, Ida. (Emal : ptva@yahoo.com). Secod step volves the geerato of carry sgals. I PPA, the dot operator ad the sem-dot operator are troduced. The dot operator s defed by the equato (4) ad the sem-dot operator s defed by the equato (5) ( g, k ) ( g, k ) = ( g, + k g, k k ) (4) ( g, k ) ( g, k ) = ( g, + k g ) (5) I the above equato, operator s appled o two pars of bts ( g, k ) ad ( g 1, K 1). These bts represet geerate ad propagate sgals used addto. The output of the operator s a ew par of bts whch s aga combed usg a dot operator or sem-dot operator wth aother pars of bts. Ths procedural use of dot operator ad sem-dot operator creates a prefx tree etwork whch ultmately eds the geerato of all carry sgals. I the fal step, the sum bts of the adder are geerated wth the propagate sgals of the operad bts ad the precedg stage carry bt usg a xor gate. The sem-dot operator wll be preset as last computato ode each colum of the prefx graph structures, where t s essetal to compute oly geerate term, whose value s the carry geerated from that bt to the succeedg bt. The structure of the prefx etwork specfes the type of the PPA. The Prefx etwork descrbed by Haku Zhu, Chug- Kua Cheg ad Roald Graham [1], has the mmal depth for a gve bt adder. Optmal logarthmc adder structures wth a fa-out of two for mmzg the area-delay product s preseted by Matthew Zegler ad Mrcea Sta []. The Sklasky adder [3] presets a mmum depth prefx etwork at the cost of creased fa-out for certa computato odes. The algorthm veted by Kogge-Stoe [4] has both optmal depth ad low fa-out but produces massvely complex crcut realzatos ad also accout for large umber of tercoects. Bret-Kug adder [5] has the mert of mmal umber of computato odes, whch yelds reduced area but structure has maxmum depth whch yelds slght crease latecy whe compared wth other structures. The Ha- Carlso adder [6] combes Bret-Kug ad Kogge-Stoe structures to acheve a balace betwee logc depth ad tercoect cout. Kowles [7] preseted a class of logarthmc adders wth mmum depth by allowg the faout to grow. Lader ad Fscher [8] proposed a geeral method to costruct a prefx etwork wth slghtly hgher depth whe compared wth Sklasky topology but acheved Iteratoal Scholarly ad Scetfc Research & Iovato 3(4) scholar.waset.org/ /57

2 Iteratoal Joural of Electrocs ad Commucato Egeerg Vol:3, No:4, 009 some mert by reducg the maxmum fa-out for computato odes the crtcal path. Related work o PPA lterature such as Lg adder [9], acheve mproved performace gas by chagg the equato of the dot operator. Taxoomy of classcal Prefx Parallel Adders based o fa-out, tercoect cout ad depth characterstcs has bee preseted by Harrs [10]. I ths paper, a ovel hybrd prefx adder structure for 8-bt, 16-bt ad 3-bt has bee proposed. The proposed structures have the least power delay product amogst all ts peer oe s. Iputs P= G + K (8) Iteratoal Scece Idex, Electrocs ad Commucato Egeerg Vol:3, No:4, 009 waset.org/publcato/57 II. EXISTING PARALLEL PREFIX ADDERS Bret Kug adder s oreted towards smpler tree structure wth a fewer computato odes. Kogge-Stoe adder possesses a regular layout ad s preferred for hgh performace applcatos. Ha-Carlso adder the reduces the hardware complexty whe compared to that of a Kogge- Stoe adder but at the cost of troducg a addtoal stage to ts carry merge path. I Sklasky adder, the fa-out from the puts to outputs alog the crtcal path creases drastcally whch troduces latecy the crcut. Lader-Fscher adder s a mproved verso of Sklasky adder, where the maxmum fa-out s reduced. TABLE I. summarzes the data regardg the requremet of umber of computato odes ad logc depth for varous exstg Parallel Prefx adders. Let be the word-legth of the adder terms of bts. TABLE I COMPARATIVE STUDY ON EXISTING PREFIX ADDERS Number of Computato Nodes Bret-Kug [* log ] [(*log ) ] Kogge-Stoe [( *log ) + 1] log Ha-Carlso )] [(log ) + 1] Lader-Fscher )] [(log ) + 1] Sklasky )] log III. PROPOSED PREFIX ADDER STRUCTURES The Proposed 8-bt, 16-bt ad 3-bt parallel prefx adder archtectures are show Fg. 1, Fg. ad Fg. 3 respectvely. The frst stage the archtectures of the proposed prefx adder structures volve the creato of kll ad complemetary geerate for dvdual operad bts usg the equatos (6) ad (7) K = A + B = A. B (6) G = ( A B) (7) I the above equatos, A, B represet put operad bts for the adder, where vares from 0 to 7 for 8-bt, 0 to 15 for 16-bt ad 0 to 31 for 3-bt adders respectvely. The Propagate sgal s derved usg the geerate ad kll sgals ad s gve by Iputs C 7 C 6 C 5 C 4 C 3 C C 1 C 0 Fg. 1 Proposed 8-bt Parallel Prefx Adder Stage C 15 C 14 C 13 C 1 C 11 C 10 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C C 1 C 0 Fg. Proposed 16-bt Parallel Prefx Adder All the proposed desgs are mplemeted usg CMOS logc famly. For dervg the carry sgals the secod stage, ths archtecture troduces four dfferet computato odes for achevg mproved performace. There are two cells desged for the dot operator. Stage Stage 5 Iteratoal Scholarly ad Scetfc Research & Iovato 3(4) scholar.waset.org/ /57

3 Iteratoal Joural of Electrocs ad Commucato Egeerg Vol:3, No:4, 009 Iteratoal Scece Idex, Electrocs ad Commucato Egeerg Vol:3, No:4, 009 waset.org/publcato/57 Iputs C 31 C 30 C 9 C 8 C7 C 6 C 5 C 4 C 3 C C 1 C 0 C 19 C 18 C C 15 C 14 C 13 C 1 C11 C 10 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C C 17 C 16 1 C 0 Fg. 3 Proposed 3-bt Parallel Prefx Adder Stage Stage 5 Stage 6 Stage 7 Stage 8 Stage 9 Frst cell for the dot operator amed odd-dot represeted by a, s defed by the equato (9) ( gk, ) = ( g, k) ( g 1, k 1) = ( g ( k+ g 1), k+ k 1 ) (9) The secod cell for the dot operator amed eve-dot represeted by a, s defed by the equato (10) ( gk, ) = ( g, k) ( g 1, k 1) = ( g+ k g 1, k k 1) (10) Smlarly, there are two cells desged for the sem-dot operator. Frst cell for the sem-dot operator amed odd-semdot represeted by a, the secod cell for the sem-dot operator amed eve-sem-dot represeted by a, works are defed usg equatos (11) ad (1) respectvely. ( g) = ( g, k) ( g 1, k 1) = ( g ( k+ g 1) ) (11) ( g) = ( g, k) ( g 1, k 1) = ( g+ k g 1) (1) The stages wth odd dexes use odd-dot ad odd-sem-dot cells where as the stages wth eve dexes use eve-dot ad eve-sem-dot cells. CMOS logc famly wll mplemet oly vertg fuctos. Thus cascadg odd cells ad eve cells alteratvely gves the beeft of elmato of two verters betwee them, f a dot or a sem-dot computato ode a odd stage receves both of ts put edges from ay of the eve stages ad vce-versa. But t s essetal to troduce two verters a path, f a dot or a sem-dot computato ode a eve stage receves ay of ts edges from ay of the eve stages ad vce-versa. From the prefx graph of the proposed structures, we observe that there are oly few edges wth a par of verters, to make ( g, k ) as ( g, k ) or to make ( g, k ) as ( g, k ) respectvely. The par of verters a path s represeted by a the prefx graph. By troducg two cells for dot operator ad two cells for sem-dot operator, we have elmated a large umber of verters. Due to verter elmato paths, the propagato delay these paths has reduced. Further we acheve a beeft power reducto, sce these verters f ot elmated, would have cotrbuted to sgfcat amout of power dsspato due to swtchg. The output of the odd-sem-dot cells gves the value of the carry sgal that correspodg bt posto. The output of the eve-sem-dot cell gves the complemeted value of carry sgal that correspodg bt posto. The fal stage volves geerato of sum bts from the derved Propagate sgals of the dvdual operad bts ad the carry bts geerated true form or complemet form. IV. SIMULATION ENVIRONMENT Smulato of varous Parallel Prefx Adder desgs were carred out wth Taer EDA tool usg TSMC 180 m ad TSMC 130 m techologes. All the Parallel Prefx Adder structures were mplemeted usg CMOS logc famly. The aspect rato of the MOS trasstor devces were chose such W W that = 3*. For TSMC 180 m techology, L L p threshold voltages of NMOS ad PMOS trasstors are aroud V ad V respectvely ad the supply voltage was kept at 1.8 V.. For TSMC 130 m techology, threshold voltages of NMOS ad PMOS trasstors are aroud 0.33 V ad V respectvely ad the supply voltage was kept at 1.3 V. The parameters cosdered for comparso are power cosumpto, worst case delay ad power-delay product. The varous PPA structures were the compared wth the umber of computato odes eeded for crcut realzatos. V. RESULTS AND DISCUSSION TABLE II, TABLE III ad TABLE IV lst out the structural characterstcs for varous 8-bt, 16-bt ad 3-bt Parallel Prefx adders. From the tables t s observed that the proposed 8-bt, 16-bt ad 3-bt Parallel Prefx adder has the least umber of computato odes amogst all other peer desgs. Structure of the proposed 3-bt adder also reveals that the prefx tree bulds alog the ma dagoal after the frst two stages. Iteratoal Scholarly ad Scetfc Research & Iovato 3(4) scholar.waset.org/ /57

4 Iteratoal Joural of Electrocs ad Commucato Egeerg Vol:3, No:4, 009 Iteratoal Scece Idex, Electrocs ad Commucato Egeerg Vol:3, No:4, 009 waset.org/publcato/57 TABLE II CHARACTERISTICS OF 8-BIT PARALLEL PREFIX ADDERS Number of Computato Nodes Bret-Kug Kogge-Stoe Ha-Carlso Lader-Fscher Sklasky Proposed TABLE III CHARACTERISTICS OF 16--BIT PARALLEL PREFIX ADDERS Number of Computato Nodes Bret-Kug Kogge-Stoe Ha-Carlso Lader-Fscher Sklasky Proposed TABLE IV CHARACTERISTICS OF 3-BIT PARALLEL PREFIX ADDERS Number of Computato Nodes Bret-Kug Kogge-Stoe Ha-Carlso Lader-Fscher Sklasky Proposed From the TABLES II, III ad IV we fer that the proposed structures have the least umber of Dot operator computato odes. TABLE V, TABLE VI ad TABLE VII lst out the performace comparso of the varous 8-bt, 16-bt ad 3-bt Parallel Prefx adders 180 m techology. TABLE VIII, TABLE IX ad TABLE X lst out the performace comparso of varous 8-bt, 16-bt ad 3-bt Parallel Prefx adders 130 m techology. TABLE V PERFORMANCE COMPARISON OF 8-BIT PARALLEL PREFIX ADDERS USING 180 m TECHNOLOGY Bret-Kug Kogge-Stoe Ha-Carlso Sklasky Lader-Fscher Proposed TABLE VI PERFORMANCE COMPARISON OF 16-BIT PARALLEL PREFIX ADDERS USING 180 m TECHNOLOGY Bret-Kug Kogge-Stoe Ha-Carlso Sklasky Lader-Fscher Proposed TABLE VII PERFORMANCE COMPARISON OF 3-BIT PARALLEL PREFIX ADDERS USING 180 m TECHNOLOGY Bret-Kug Kogge-Stoe Ha-Carlso Sklasky Lader-Fscher Proposed Iteratoal Scholarly ad Scetfc Research & Iovato 3(4) scholar.waset.org/ /57

5 Iteratoal Joural of Electrocs ad Commucato Egeerg Vol:3, No:4, 009 Iteratoal Scece Idex, Electrocs ad Commucato Egeerg Vol:3, No:4, 009 waset.org/publcato/57 TABLE VIII PERFORMANCE COMPARISON OF 8-BIT PARALLEL PREFIX ADDERS USING 130 m TECHNOLOGY Bret-Kug Kogge-Stoe Ha-Carlso Sklasky Lader-Fscher Proposed TABLE IX PERFORMANCE COMPARISON OF 16-BIT PARALLEL PREFIX ADDERS USING 130 m TECHNOLOGY Bret-Kug Kogge-Stoe Ha-Carlso Sklasky Lader-Fscher Proposed TABLE X PERFORMANCE COMPARISON OF 3-BIT PARALLEL PREFIX ADDERS USING 130 m TECHNOLOGY Bret-Kug Kogge-Stoe Ha-Carlso Sklasky Lader-Fscher Proposed VI. CONCLUSION It s observed that the proposed 16-bt ad 3-bt prefx adders have the least value of power delay product whe compared wth ts exstg peer oes. The proposed desg acheves about 0% to 40 % power savgs whe compared to Kogge-Stoe adder. The proposed desg attas a mprovemet of 5% to 14% power savgs whe compared wth Bret-Kug adder. A beeft of 7% to 5% power savg s acheved the proposed desg whe compared wth Sklasky adder. A beeft of 5% to % mprovemet power ca be attaed for the proposed adders whe compared wth Ha-Carlso adder. It s ferred that the power savg gradually creases for the proposed desg whe the sze of the prefx adder grows. It s also observed that the power delay product s mmal whe the word legth of the adder creases. The proposed desg cosumes least power wth very less delay pealty whe compared wth ts peer exstg prefx adders. Ths sgfcat mprovemet power makes the proposed desg more suted for ALU s, Multplers ad Dgtal Sgal Processors. REFERENCES [1] Haku Zhu, Chug-Kua Cheg ad Roald Graham, Costructg Zero Defcecy Parallel Prefx adder of Mmum Depth, Proceedgs of 005 Asa South Pacfc Desg Automato Coferece, 005, pp [] Matthew Zegler, Mrcea Sta, Optmal Logarthmc Adder structures wth a fa-out of two for mmzg area delay product, IEEE 001. [3] J. Sklasky, Codtoal Sum Addto Logc, IRE Trasactos o Electroc computers, vol. EC-9, 1960, pp [4] P.Kogge ad H.Stoe, A Parallel Algorthm for the effcet soluto of a geeral class of recurrece relatos, IEEE Trasactos o Computers, vol. C-, o.8, August 1973, pp [5] R.Bret ad H.Kug, A Regular Layout for Parallel adders, IEEE Trasacto o Computers, vol. C-31, o.3, March 198, pp [6] T. Ha ad D. Carlso, Fast Area Effcet VLSI adders, Proceedgs of the 8 th Symposum o Computer Arthmetc, September 1987, pp [7] S.Kowles, A Famly of Adders, Proceedg of the 15 th IEEE Symposum o Computer Arthmetc, Jue 001, pp [8] R. Lader ad M. Fscher, Parallel Prefx Computato, Joural of ACM, vol.7,o.4, October 1980, pp [9] Gorgos Dmtrakopoulos ad Dmtrs Nkolos, Hgh Speed Parallel Prefx VLSI Lg adders, IEEE Trasactos o Computers, vol.54, o., February 005, pp [10] Davd Harrs, A Taxoomy of Parallel Prefx Networks, Proceedgs of the 37 th Aslomar Coferece o Sgals, Systems ad Computers, 003, pp P.Ramaatha s curretly workg as a Seor Lecturer Electrocs ad Commucato departmet, PSG College of Techology, Peelamedu, Combatore Ida.. He has about 10 years of teachg experece ad s curretly dog research the area of VLSI Desg.. Dr.P.T.Vaath s curretly workg as a Assstat Professor Electrocs ad Commucato departmet, PSG College of Techology, Combatore Ida.. She has about 0 years of teachg experece. Her research are Speech Sgal Processg, Image Processg ad VLSI Desg.. Iteratoal Scholarly ad Scetfc Research & Iovato 3(4) scholar.waset.org/ /57