DESIGN AND IMPLEMENTATION OF HYBRID CASCADED ENERGY EFFICIENT KOGGE STONE ADDER

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1 ARPN Journal of Engneerng and Appled Scences Asan Research Publshng Network (ARPN). All rghts reserved. DESIGN AND IMPLEMENTATION OF HYBRID CASCADED ENERGY EFFICIENT KOGGE STONE ADDER J. Vgnesh 1, E. Gajendran 2, Sameeruddn Khan 3, N. Balakumar 4 and S. R. Boseln Prabhu 5 1 Department of Computer Scence and Engneerng, Sreyas Insttute of Engneerng and Technology, Hyderabad, Inda 2 Department of Computer Scence and Engneerng, Sree Dattha Group of Insttutons, Hyderabad, Inda 3 Sree Dattha Group of Insttutons, Hyderabad-Telangana, Inda 4 Department of Electrcal and Electroncs Engneerng, Taml Nadu College of Engneerng, Combatore, Inda 5 Department of Electroncs and Communcaton Engneerng VSB Engneerng College, Taml Nadu, Inda E-Mal: eben4uever@gmal.com ABSTRACT Addton plays a vtal role n all arthmetc operatons. It s used wdely n many VLSI systems such as applcaton specfc DSP archtecture and mcroprocessor archtecture. The energy effcent desgns have ganed more recent attenton and for hghly employed functonal unts, especally for the adders. The energy consumpton of an adder depends on the crcut mnmzng, the addton procedure, the recurrence structure and the wrng complexty. Wenberger and Lng are the two most commonly used bnary addton algorthms that are used n adders. Ths paper gves the performance evaluaton of addton algorthms on Kogge-Stone arrangement and have been observed to save energy by the proper selecton of addton algorthms n 16-bt adders. The desgn of Kogge-stone adder has been carred out by usng TANNER EDA tool. The effcency ofthe adder desgn can be mproved by prefx selecton, the algorthm, computatonal sum and logc depth. When compared to Wenberger algorthm, the number of gates used s less n case of the proposed lng recurrence algorthm. Keywords: arthmetc and logc unt, computer arthmetc logc, energy-effcent method, hgh-speed arthmetc, DSP archtecture, mcroprocessor archtecture. 1. INTRODUCTION Bnary addton s one of the greatest prmtve and commonly used applcatons n computer arthmetc operaton. A huge varety of recent algorthms and mplementatons have been formulated for bnary arthmetc addton [1-3]. Parallel-prefx adder tree topology network such as Kogge-Stone adder [4], Sklansky adder [5], Brent-Kung adder [6], Han- Carlson adder [7], and Kogge-Stone adder usng Lng adders [8, 9] can be used to realze hgher system operatng speeds wth hgher effcency. Parallel prefx adders are sutable for very large scale ntegrated mplementaton, snce they trust on the use of smple cells and sustan regular connectons between them. The VLSI nteger adders are crtcal elements n general purpose processor and dgtal sgnal processors, as they are employed n the desgn of ALU data paths. In nanometer range, t s very sgnfcant to develop dfferent types of addton algorthms that provde hgh energy performance whle reducng power consumpton of the system. The requrements of the adder are that, t should be ntally fast and secondarly effectual n terms of power consumpton, energy and chp area. For wde-rangng adders (N>16), the delay of carry look-ahead adders becomes subjected by the delay n passng the carry through the look- ahead stages. Ths delay can be decreased by lookng ahead across the look-ahead blocks. In general, a multlevel tree of look-ahead adders could be constructed to acheve delay that grows wth logn. Such adders are commonly referred as tree adders or parallel prefx adders. Many parallel prefx topology have been descrbed n the lterature, especally n the framework of addton. The basc modules of adders can be desgned n many ways. At second level, mnmzaton can also be acheved by usng specfc logc famles n the desgn. The energy and power consumpton of a mcroprocessor adder depends on the crcut szng, the addton algorthm, the recurrence arrangement and the wrng dffculty. In ths paper, adder components have been desgned, analyzed and compared wth the exstng technques n deep submcron technology. Several alternates of the carry look-ahead equatons, lke Lng adders [9] have been offered that smplfy the carry level computatons and can lead to faster adder structures. A comparatve survey on the above mentoned hgh-speed bnary adders have been entaled to afford a lst of energy-effcent crcut topology that would be applcable to any parallel prefx computaton algorthms. By way of desgnng and mplementaton of hgh-speed adders, an mprovement n energy and power performance have been perceved. The rest of the paper has been organzed as follows. Secton II descrbes about the detaled lterature survey of exstng adder crcuts. Secton III elaborates the archtecture of VLSI addton algorthms. Secton IV descrbes about the performance analyss of addton algorthms. Secton V entals the desgn of VLSI adder crcuts. Secton VI descrbes about the smulaton results and dscussons. Fnally the last secton descrbes the concluson. 2. REVIEW OF ADDER CIRCUITS 2.1. Carry look ahead adder A carry-look ahead adder (CLA) s a type of hgh speed adder used n dgtal logc crcuts. A carry-look ahead adder ncreases the speed by decreasng the amount 6248

2 ARPN Journal of Engneerng and Appled Scences Asan Research Publshng Network (ARPN). All rghts reserved. of tme requred to determne carry bts n the system. It can be dstngushed wth the smpler but usually slower, rpple carry adder for whch the carry bt s consdered together wth the sum bt, and each bt must wat untl the prevous carry has been calculated to begn computng ts own result and convey bts. The carry-look ahead adder determnes one or more carry bts before the sum, whch decreases the wat tme to calculate the result of the larger value bts. Consder the n-bt addton of two numbers: A = a n-1, a n- 2..a 0 and B =b n 1, b n 2...b 0 resultng n the sum, S = s n 1, s n 2. s 0 and a carry, C out. The frst stage n carry-look ahead adder calculates the bt generate and bt propagate as follows, g a. b and p a b (1) Where g s the bt generates and p s the bt propagate. These are then utlzed to calculate the fnal sum and carry bts n the last stage as follows: s p cand c 1 g p. c (2) Where, + and represents exclusve, addton and multply operatons respectvely. It s seen from equaton (2) that, the frst and last stages are nherently fast because they encompass only smple operatons on sgnals local to each bt poston. However, ntermedary stages represent the long-dstance propagaton of carres, as a result of the performance of the adder merges on ths part [10]. These ntermedate stages can be used to determne group generate bt and group propagate bt to avod watng for a rpple, whch n turn reduces the delay perod. These group generate and propagates are gven by, P P P and G: j G:k G k 1: j.p:k (3) : j :k k 1: j In ths paper, Kogge-Stone mplementaton of Wenberger, Sparse-2 mplementaton of Wenberger, lng wth merged frst recurrence stage and bt-wse operatons mplementaton of carry-look ahead adder have been carred out elaborately. 2.2 Hgh-speed bnary adder A novel method s used to represent the new carry bt formaton and propagaton bt based on the percepton of the complementng sgnal whch was ntroduced n 1965.To study the mpact of ths complementng sgnal n performng bnary addton and complementng sgnal look-ahead adder, one should estmate the formaton of H and H +1 as a functon of adjacent bt pars (, +1). Consder addng two bnary numbers A and B together where, A = a 0 2 n + a l 2 n-1 + a 2 2 n a 2 n a n 2 0 and B = b 0 2 n + b 1 2 n-1 + b 2 2 n b 2 n b n 2 0. The relaton among the new carry (H, H +1 ) and the adjacent bt pars (a, b, a +1, b +1 ) can be expressed all of these are generated by a, b or transferred through the low- order bts +1, +2,..., wth the transmttng-enable swtch to be ON. Ths sgnal or new carry can only be termnated when the nhbtor s ON (a +l + b +1 = 0) Carry skp adder The method s based on the detecton and bypassng of the stages of a parallel prefx bnary adder for the requred addton (x+y), there happens the condton for carry- propagaton. That s, the carry-sgnal s enabled to by-pass those steps of the carry paths for whch, x y (4) Another crteron whch does not make dfference between propagated bt and generated bt conveys, but whch s more effcent n the carry skp crcut s, x y (5) The crcut prescrbed by Morgan and Jarvs, dvdes the adder nto fxed groups both of sx stages. The carry sgnal lookng at the nput of any group for whch the condton s satsfed for each stage of the group, s transmtted to the next group through a specal skp gate. At the same tme, the carry s also allowed to propagate wthn the group to enter the determnaton of varous sum bts Carry-select adder The carry-select adder commonly conssts of two rpple carry adders and a multplexer. Addng two n-bt numbers wth a carry-select adder s done wth two adders n order to acheve the calculaton twce, one tme wth the supposton of the carry beng zero and the other assumng one. The number of bts n each carry select block can be unform. In the even case, the optmum delay occurs for a blockof sze. When a varable, the block sze must have a delay, from addton nputs A and B to the carry out, equal to that of the multplexer chan leadng nto t, so that the carry out s determned just n tme. 2.5 Condtonal-sum adder A condtonal sum adder s a recursve arrangement whch s based on the carry-select adder. In case of condtonal sum adder, the MUX level chooses between two n/2-bt nputs that are themselves made as condtonal-sum adder. The bottom level of the tree conssts of pars of 2-bt adders plus 2 sngle-bt multplexers. The condtonal sum adder undergoes a very large fan-out of the ntermedate carry outputs. The fan out could be hgh as n/2 on the prevous level. 3. ADDITION ALGORITHMS In ths paper, mathematcal analyss has been carred out for Wenberger adder and Lng adder [11-12]. 3.1 Kogge-stone adders 6249

3 ARPN Journal of Engneerng and Appled Scences Asan Research Publshng Network (ARPN). All rghts reserved. The major dfference between Kogge-Stone adders and other adders s hgher performance. It calculates carry equvalent to every bt wth the help of group generate bt and group propagate bt. In ths adder the logc levels are gven by log 2 N, and the fan-out s 2. generalzaton by factorng transmt, t from carry and expressed as, C g t.c and C t g C 1 1 (9) Fgure-1. Wenberger s recurrence for addton. (a) 3.2 Wenberger s recurrence for addton Wenberger offered a general form for carry recurrence whch s not restrcted n group szes and number of levels for carry computaton. The conventonal carry look-ahead adder s a defnte case of ths general carry recurrence. The sum and carry are defned and ndexed as follows, S a b C and C 1 a.b a b C (6) In Wenberger s recurrence method, the carry propagaton speed has been mproved by the usage of generate bt and propagate bt. Propagate can ether be executed usng an OR or XOR realzatons. To dfferentate the OR realzaton of propagate as transmt t, and the XOR realzaton as p, Wenberger s bt operatons s descrbed as, (b) g a.b and t a b (7) Substtutng (7) nto (6) results n, C 1 g t.c (8) Wenberger establshed that the recurrence apples to any prefx varaton by the usage of group generate bt G and group transmt btt. The computatons of G and T are assocatve and dempotent, whch permts for a wde range of recurrence tree structure possbltes for carry computaton Lng s transformaton Technology lmtatons on fan-n and wred-or n ECL (transstor stack heght n complementary metal oxde semconductor) nterested n the smplfcaton of Wenberger s recurrence. Lng establshed a transformaton whch became capablen achevng ths (c) Fgure-2. (a) Wenberger s recurrence (b) Intermedate form (c) Lng s transformaton. The overall transformaton from Wenberger s recurrence to Lng s recurrence has been depcted n Fgure-2. To create Lng s recurrence, ths transformaton s appled to C 6 whch allows for a recurrence for C 10 to be created usng H and T as shown n Fgure-3. For the recurrence, H 9 has one less term than G 9 n Wenberger s recurrence. To allow for recurrence T 8.6 s combned wth t 5, resultng n the same number of terms as T 9.6 used n Wenberger s recurrence. 6250

4 ARPN Journal of Engneerng and Appled Scences Asan Research Publshng Network (ARPN). All rghts reserved. Fgure-3. Lng s recurrence. Lng s recurrence s performed on, H : C 1 th and H g t 1.H 1 (10) The man advantage of Lng s transformaton s the compatblty wth the prefx operator for recurrence of H and T -1.As a result, Lng s H and T have the same favourable propertes as Wenberger s G and T when usng the prefx operator. Lng s transformaton decreases the dffculty of the recurrence by one term t n the frst stage of the carry tree wth the usage of H -1 nstead of C. However, the decrease n recurrence dffculty s acheved at the expense of ncrease n sum complexty. Fgure bt kogge stone Wenberger s adder. S A B (t H ) (11) 1 1 Improved sum complexty can be allevated by usng condtonal logc. The summaton can be mplemented usng a multplexer wth H -1 as the select. S A B f H 1 0 A B t 1 f H 1 1 (12) A multplexer permts for sum to be computed wth no mproved complexty on the crtcal path compared to Wenberger s n the delay mprovement acheved from decreasng the recurrence by one term. 4. ANALYSIS OF ADDITION ALGORITHMS As mentoned earler, Wenberger and Lng are the most commonly used addton algorthms n CMOS technology. Doran s transformatons are not sutable for effcent CMOS realzaton. Doran demonstratons the recurrences that are more sutable n CMOS technology are Wenberger and Lng. Wenberger ntroduced the concept of generate bt and propagate bt sgnals to permt parallel prefx computaton of carry sgnals to ncrease the system speed of addton. Lng transformaton smplfes the carry recurrence of Wenberger at the cost of ncreased sum complexty when compared to Wenberger. Also, Lng recurrence algorthm gves better performance than Wenberger adder. Fgure bt kogge stone Lng adder. Kogge-Stone (KS) adder s one of the wellknown hgh performance and mnmum depth parallel prefx adder arrangement, but t has hgh wrng complexty and energy consumpton. Ths structure can be appled over Wenberger and Lng addton algorthms. The schematc artculaton of 16-bt Kogge-Stone adder wth Wenberger addton algorthm s depcted n Fgure- 4, and the schematc artculaton of sparse-2 Lng adder wth merged frst recurrence stage s depcted n Fgure-5. The logc gates n carry path for both addton algorthms are the same except the frst carry combne stage. Lng recurrence uses NAND gate n the frst carry combne stage that s OAI gate n Wenberger. Also, the nternal network of gates are dfferent for each other s. Addtonally, the sum generaton blocks nclude dfferent logc gates and ther structures are dfferent. The number of nternal nodes present n Lng adder s hgher. 5. DESIGN OF ADDERS Adders have been appled wth statc CMOS, dynamc CMOS and CMOS compound domno logc famles. Several approaches have been proposed to ncrease the energy effcency: proper selecton of crcut 6251

5 ARPN Journal of Engneerng and Appled Scences Asan Research Publshng Network (ARPN). All rghts reserved. famly and prefx, reducng the number of logc gates wthout ncreasng gate count, reducng swtchng actvty, reducng number of logc gates, load bufferng and reducng the wrng complexty. Based on these approaches a hgh performance and energy effcent VLSI adders are constructed. 6. SIMULATION RESULTS AND DISCUSSIONS In ths paper, 16 bt Kogge Stone prefx-2 adder usng Wenberger and lng recurrence algorthm has been desgned n statc, dynamc and domno CMOS logc. For hgh-performance dynamc adders, Lng adder shows a fundamental advantage n CMOS by reducng the complexty of the frst stage of the recurrence tree. Fgure-7. Power versus delay parameters (KSW-DYN). Fgure-7 shows the power versus delay parameter values that are obtaned usng Wenberger structure n dynamc mode of operaton. It could be clearly observed that the power consumpton of KSW-Dynamc Mode of operaton s 650 mw. Dynamc mode of operaton consumes less power when compared to statc mode as well as domno mode. Fgure-6. Power versus delay parameters (KSW-STA). The desgns whch have the least number of stages are hghly energy-effcent. Reduced energy consumpton s a result of the decreased number of stages n the desgn, whch permts for the same delay to be acheved whle usng a greater fan-out per stage. The energy reducton and performance enhancement of these desgns s lmted due to ncreased branchng and gate complexty. The desgn of Kogge-stone adder has been carred out by usng TANNER EDA tool and the desgn parameters are obtaned for namely: power and delay. Fgure 6 depcts the power versus delay parameter values obtaned by usng Wenberger structure n statc mode of operaton. It could be clearly observed that the power consumpton of KSW-Statc Mode of operaton s 840 mw. Fgure-8. Power versus delay parameters (KSW-DOM). Fgure-8 shows the power versus delay parameter values that are obtaned usng Wenberger structure n domno mode of operaton. It could be clearly observed that the power consumpton of KSW-Dynamc Mode of operaton s 680 mw. Thereby, domno mode of operaton consumes less power when compared to KSW-Statc Mode of operaton but ncreased power consumpton when compared to dynamc mode of operaton. 6252

6 ARPN Journal of Engneerng and Appled Scences Asan Research Publshng Network (ARPN). All rghts reserved. Fgure-9. Power versus delay parameters (KSL- STA). Fgure-11. Power versus delay parameters (KSL-DOM). Fgure-11 shows the power versus delay parameter values that s obtaned usng Lng structure n domno mode of operaton. It could be observed that the power consumpton of KSL-Domno Mode of operaton s 560 mw, whch s less when compared to KSL-Statc Mode of operaton but hgher when compared to KSL- Dynamc mode of operaton. Table-1. Tabulated values of power of KSW and KSL. Fgure-10. Power versus delay parameters (KSL-DYN). Fgure-9 depcts the power versus delay parameter values that s obtaned usng Lng structure n statc mode of operaton. It could be clearly seen that the power consumpton of KSL-Statc Mode of operaton s 740 mw. As such, KSL-Statc mode of operaton consumes more power when compared to KSL-Dynamc Mode of operaton and KSL-Domno mode of operaton. Fgure-10 shows the power versus delay parameter values that s obtaned usng Lng structure n dynamc mode of operaton. It could be observed that the power consumpton of KSL-Dynamc Mode of operaton s 540 mw, whch s less when compared to both KSL- Statc Mode of operaton and KSL-Domno mode of operaton. Adder type Power (mw) KSW-STATIC 840 KSW-DYNAMIC 650 KSW-DOMINO 680 KSL-STATIC 740 KSL-DYNAMIC 540 KSL-DOMINO 560 The smulated values of KS-Wenberger adder and KS-Lng adderare compared and the results are shown n table 1. From the results t could be clearly seen that, KSW-Statc adder consumes 840 mw power whch s very much hgher when compared to the power consumpton by all other adders. Hence, KSW-Dynamc adder shows 29.23% reduced power consumpton when compared to KSW-Statc adder, 4.61% reduced power consumpton when compared to KSW-Domno adder and 13.84% reduced power consumpton when compared to KSL- Statc adder. KSW-Domno adder shows 23.52% reduced power consumpton when compared to KSW-Statc adder and 8.82% reduced power consumpton when compared to KSL-Statc adder. KSL-Statc adder shows 13.51% reduced power consumpton when compared to KSW- Statc adder. KSL-Domno adder shows 50% reduced power consumpton when compared to KSW-Statc adder, 16.07% reduced power consumpton when compared to KSW-Dynamc adder, 21.42% reduced power consumpton when compared to KSW-Domno adder and 32.14% reduced power consumpton when compared to KSL-Statc adder. KSL-Dynamc adder shows 55.55% reduced power consumpton when compared to KSW- Statc adder, 20.37% reduced power consumpton when 6253

7 ARPN Journal of Engneerng and Appled Scences Asan Research Publshng Network (ARPN). All rghts reserved. compared to KSW-Dynamc adder, 25.92% reduced power consumpton when compared to KSW-Domno adder, 37.03% reduced power consumpton when compared to KSL-Statc adder and 3.70% reduced power consumpton when compared to KSL-Domno adder. Among all these adder crcuts, KSL-Dynamc adder shows reduced power consumpton because of the novel concepts embedded wthn ths partcular adder. 7. CONCLUSIONS To ncrease the computatonal speed of the arthmetc unt, Kogge Stone adder has been employed. Ths paper gves a detaled evaluaton of the desgn of low power and hghly effcent VLSI adders n statc, dynamc and domno CMOS logc usng Wenberger and Lng recurrence structure. The power consumpton of Kogge- Stone adder has been analyzed for Wenberger and Lng recurrence structure. Smulaton result clearly shows that KSW-Statc adder consumes more power when compared to all type of adders. Also, KSW-Dynamc adder consumes less power when compared to KSW-Statc adder, KSW-Domno adder and KSL-Statc adder. Thereby, KSW-Domno adder consumes less power when compared to KSW-Statc adder and KSL-Statc adder. The proposed KSL-Statc adder consumes less power when compared to KSW-Statc adder. KSL-Domno adder shows reduced power consumpton when compared to the power consumpton of all type of adders, except KSL- Dynamc adder. KSL-Dynamc adder shows 55.55% reduced power consumpton when compared to KSW- Statc adder, 20.37% reduced power consumpton when compared to KSW-Dynamc adder, 25.92% reduced power consumpton when compared to KSW-Domno adder, 37.03% reduced power consumpton when compared to KSL-Statc adder and 3.70% reduced power consumpton when compared to KSL-Domno adder. Thus, KSL-Dynamc adder gves better performance (.e., reduced power consumpton) when compared to all other adders, asthese crcut employs less number of logc gates when compared to the exstng adders. [5] J. Sklansky Condtonal-sum addton logc. IRE Transactons on Electronc Computers. 9: [6] R. P. Brent and H.T. Kung A regular layout for parallel adders. IEEE Transactons on Computers. 31(3): [7] T. Han and D. Carlson Fast area effcent VLSI adders. Proceedngs of IEEE Symposum on Computer Arthmetc. pp [8] H. Lng Hgh-speed bnary adder. IBM Journal of Research and Development. 25: [9] A. Balga and D. Yagan Desgn of hgh speed adders usng CMOS and transmsson gates n submcron technology: a comparatve study. Proceedngs of the 4 th Internatonal Conference on Emergng Trends n Engneerng and Technology. pp [10] S. Knowles A famly of adders. Proceedngs of the 15 th IEEE Symposum on Computer Arthmetc. pp [11] B.R. Zeydel, T. Kluter and V.G. Oklobdzja Effcent mappng of addton recurrence algorthms n CMOS. 17 th IEEE Symposumon Computer Arthmetc. [12] D. Baran, M. Aktan, H. Karmyan and V.G. Oklobdzja Exploraton of swtchng actvty behavor of addton algorthms. IEEE Internatonal Mdwest Symposum on Crcuts and Systems (MWSCAS-2009). REFERENCES [1] I. Koren Computer arthmetc algorthms. A.K. Peters, Lmted. [2] B. Parham Computer arthmetc algorthms and hardware desgns. Oxford Unversty Press. [3] M. Ergecovac and T. Lang Dgtal arthmetc, morgan- kauffman. [4] P.M. Kogge and H.S. Stone A parallel algorthm for the effcent soluton of a general class of recurrence equatons. IEEE Transactons on Computers. 22(8):