Annealing Nano-to-Micro Contacts for Improved Contact Resistance

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Annealing Nano-to-Micro Contacts for Improved Contact Resistance Heather Chiamori*, Xiaoming Wu, Xishan Guo, Bao Quoc Ta, and Liwei Lin, Member, IEEE Berkeley Sensor & Actuator Center, Department of

1 Annealing Nano-to-Micro Contacts for Improved Contact Resistance Heather Chiamori*, Xiaoming Wu, Xishan Guo, Bao Quoc Ta, and Liwei Lin, Member, IEEE Berkeley Sensor & Actuator Center, Department of Mechanical Engineering University of California at Berkeley Berkeley, CA, USA Abstract Nano-to-micro electrical contact resistance between carbon nanotubes (CNTs) and larger-scale silicon systems are investigated using both low- and high-power annealing techniques. Carbon nanotubes locally synthesized and suspended between two silicon microbridges are used as the test platform. The annealing technique involves Joule heating of either the CNT/silicon system or the secondary silicon bridge only at low or high input power for various times. Of the 15 samples tested, results show that the contact resistance decreases for 60% of the samples and two of the 15 samples show a decrease in contact resistance greater than 50%. Higher power and longer time anneals show the greatest improvement in reducing the contact resistance. This technique can potentially reduce the contact resistance for integration of CNTs with MEMS or microelectronics systems. Keywords-MWCNT; NEMS; MEMS; contact resistance; annealing; localized synthesis I I. INTRODUCTION ntegration of nanomaterials into larger systems for applications such as electrical interconnects or sensors is a field of intense study [1]-[3]. Nanostructures often exhibit unique properties due to high surface to volume ratios, but hindering extensive use of these materials includes placement of nanomaterials at desired locations as well as contact resistance issues when connecting them to the macroscale. As a potential solution to the first issue, we previously demonstrated that a local synthesis method based on Joule heating of the substrate allows individual or small groups of CNTs to be placed at certain locations on a substrate and characterized across gaps spanning 5 to 20 µm [4]-[6]. In attempts to address the second aspect of nano-to-micro integration, researchers have attempted to reduce the contact resistance by using electrical breakdown [7], silicide or carbide formation [8]-[10], electron beam irradiation [11], ultrasonic bonding [12], rapid thermal annealing [13], or Joule heating of large area Pt or Pd contacts deposited by electron beam lithography [14]-[16]. Although the methods can potentially improve the contacts, they are either expensive, heat the entire chip or device to high temperatures, require unique equipment and/or are timeconsuming. Here we demonstrate a simple and fast annealing technique for locally synthesized CNTs not requiring any special or additional equipment. Preliminary results of higher temperature and longer time annealing of the secondary contact Figure 1. Schematic of annealing process using Joule heating of the secondary bridge structure. of locally grown CNTs indicates that contact resistance can be substantially reduced. II. EXPERIMENTAL SETUP The experimental silicon/cnt/silicon platform has been described in detail previously [4]-[6]. Briefly, two silicon microbridges are fabricated on SOI wafers with 15 µm device layers. Typically, a thin metal catalyst layer is deposited (~5nm) on the substrates using thermal evaporation or e-beam methods. The localized CNT synthesis process involves incrementally increasing the power input to one of the silicon bridges designated growth side, then monitoring the output voltage on the secondary side to determine a CNT connection. Initially, an inert gas is used to purge the chamber and growth occurs under low vacuum conditions (3.3 x 10 4 Pa). A bias voltage of up to 10 V is applied to help direct the CNT growth across the gap. A carbon source gas is flowed over the heated bridge initiating CNT growth. After a successful CNT connection is made across the silicon microbridges, indicated by a voltage jump, multiple current-voltage (I-V) curves are then measured from -1 to 1 V with a semiconductor parameter analyzer (HP-4145B) to establish stability of the CNT and contact. The authors are with the Berkeley Sensor & Actuator Center and the Department of Mechanical Egineering at the University of California at Berkeley. *Contact author: H. Chiamori (chiamori@me.berkeley.edu) X. Wu, is on leave from institute of microelectronics, Tsinghua University, Beijing, China. X. Guo is on leave from Department of Biosystems Engineering, Zhejiang University, China. B. Quoc Ta is on leave from Vestfold University, Norway.

Figure 2. SEM image of a typical silicon/cnt/silicon system. A single MWNT spans a gap distance of approximately 10 µm. The gaps between silicon microbridges range from 5 to 20 µm.

2 Figure 2. SEM image of a typical silicon/cnt/silicon system. A single MWNT spans a gap distance of approximately 10 µm. The gaps between silicon microbridges range from 5 to 20 µm. Once a stable CNT contact is verified, the annealing process is then applied. Two annealing techniques involving low- and high-temperature annealing are examined. During the annealing process, the chamber pressure is maintained at 3.3 x 104 Pa under Argon gas flowrate of 100 sccm. For lowtemperature annealing, two techniques are evaluated. First, low-power annealing is applied to the entire CNT/silicon system. After CNT growth, the chamber is purged with argon gas and exposure of the sample to the ambient environment is avoided. A voltage is applied between the growth and secondary sides to generate electric current in the silicon/cnt/silicon system. Because the resistance at CNT/silicon contact is much larger that those of CNT and silicon structures, most of Joule power is consumed at the contact and the contact areas are heated locally. The voltage is then incrementally increased by 0.5 V every 5 seconds until the power of 25 to 28 µw is obtained. These lower power inputs were chosen to avoid destroying CNTs [15] as well as utilizing previous experimental evidence that higher power through the CNT system could burn-out the CNT. During the ramp-up process, three I-V measurements are taken each minute to monitor the continued stability of the CNT contact. The voltage is held constant for three minutes, then stepped down in 0.5 V increments every 5 seconds until zero voltage. Finally, initial and post-anneal I-V measurements are compared to evaluate the curve stability. The second low power technique involves heating only the secondary bridge instead of the entire system, as shown in Fig. 1. In this case, burn-out of the CNTs can be avoided and potentially higher power values can be input into the system. The voltage of the bridge is incrementally increased 0.5 V every 5 to 10 seconds until the power input reaches approximately 30 mw, three orders of magnitude higher than the previous technique. The currents of both bridges are monitored separately. Any drastic drops in current indicate that the CNT is no longer connected to the substrate or the CNT is broken. I-V measurements are taken of the CNT/silicon system Figure 3. Simulated temperature vs. Joule heating power of secondary silicon structure. Figure 4. Typical I-V measurements of pre- and post- annealing of silicon/cnt/silicon system. to evaluate the stability of the contact and the resulting change in resistance. The high temperature annealing process consists of Joule heating the secondary bridge side with different power inputs. The voltage is stepped up in 0.5 V increments for 5 to 10 seconds each until the desired temperature is greater than 600 C, which is evaluated by the emission color of the secondary bridge. The annealing processing is applied for approximately 5 minutes. The currents of both bridges are again monitored during the process to verify they are maintained steady. After annealing, multiple I-V measurements are recorded to verify that the CNT connection remains intact and the contacts are robust. Fig. 2 is a scanning electron microscopy (SEM) image of a typical silicon/cnt/silicon system. The I-V curves are used to determine the resistance of the CNT/silicon system. To estimate the annealing temperature of the silicon bridge based on input power, we use ANSYS (version 11.0) to

TABLE I. CNT ANNEALING SAMPLES WITH PRE- AND POST- ANNEALING RESISTANCE VALUES BASED ON STABLE I-V CURVES CNT Sample # Resistance (MΩ) After growth Post-anneal Metal Stack a Annealing Method b 1 6.

3 TABLE I. CNT ANNEALING SAMPLES WITH PRE- AND POST- ANNEALING RESISTANCE VALUES BASED ON STABLE I-V CURVES CNT Sample # Resistance (MΩ) After growth Post-anneal Metal Stack a Annealing Method b A A A A B B B A A B B B A A B 1 a. metal thin films evaporated onto the bridges: (A) Fe only; (B) Mo-Al-Fe; b. Annealing methods are as follows: (1) low temperature CNT/silicon system; (2) low temperature secondary side only; (3) high temperature secondary side only Figure 6. Resistance change ratio (%) vs. annealing time with respect to heating of secondary bridge. we define as change in resistance divided by as-growth resistance: Resistance ratio change (%) = (1) Figure 5. Statistical data of resistance values pre- and post- annealing process. simulate a temperature vs. power curve (Fig. 3). For low power annealing of approximately 30 mw (technique 2), we estimate the bridge temperature is less than 100 C. Although the ANSYS simulation does not evaluate technique 1 conditions, the power input is much smaller than technique 2 so that low temperatures are assumed as well. For higher power inputs of 100 to 150 mw, annealing temperatures are estimated greater than 600 C. At this temperature, a dull red emission is observed from the secondary bridge. III. RESULTS Resistance values are calculated by assuming a linear current-voltage relationship from the stable I-V curves. As shown in Fig. 4, the I-V measurements illustrate typical curves from before and after the annealing process. These values are used to calculate the percentage change resistance ratio, which To date, we have tested 15 samples, nine of which show a decrease in contact resistance with two samples decreasing over 50% in resistance. As shown in Fig. 5, initial and postanneal resistance values are tabulated in histogram form. The resistance change ratios are plotted versus time and as a function of annealing temperature as shown in Fig. 6. Table 1 shows the pre- and post- annealing resistance values as well as the annealing techniques and metal layers used. The time range for all low temperature annealing samples is three minutes or less, except for one sample that was annealed for approximately five minutes. Both low temperature annealing techniques use either the iron catalyst thin film or a multi-metal stack (Mo-Al) beneath the iron catalyst layer. Thus far no significant differences with respect to CNT/silicon resistance changes are noted at low temperatures, but will be investigated in future studies at higher power inputs and longer times. The Mo-Al stack was developed previously in our lab and has significantly improved the contact resistance between CNT forests and the substrate [17]. We use it here as an attempt to reduce the interface resistance for locally synthesized CNTs. For higher power annealing at longer times, the secondary bridge temperature is estimated from input power values of 100 to 150 mw corresponding to approximately 500 to 900 C. Of the four samples annealed for longer times, all showed decreases in post-annealing resistance values with one resistance ratio decreasing over 80%.

4 IV. DISCUSSION Dong, et. al, suggested that a reduction in CNT and metal electrode interface resistance is due to an increased CNT surface area in contact with the melted metal electrode material [13]. For the samples annealed at higher temperatures and longer times, this may be a contributing factor to the resistance decreases. All of those samples showed decreases in resistance ratios ranging from 20 to over 80%. While the estimated temperatures of the silicon bridges are not high enough to obtain the bulk melting temperature values of the respective metals, it has been shown that melting point depression scales with decreasing size and dimensions of the materials [18]-[19] and that the thin films on the microbridge substrates may be melting and wetting the surface of the CNT. The low temperature techniques may not be affecting the metal/cnt interface as drastically since the initial low-power annealing process through the entire CNT/silicon system involves low currents and low estimated annealing temperatures. The low temperature annealing results indicate that the contact resistance can increase or decrease under similar conditions as shown in Fig. 5. These results are in agreement with other reports in the literature [14]-[15]. In this case, the metal thin films may not be contributing to the reduction of the interface resistance by increased CNT surface area/electrode contact. The heating of the secondary contact via secondary bridge is an effort to reduce the overall contact resistance. The resistance of the silicon bridges is on the order of several hundred Ω, reported values for single MWNT resistance ranges from Ω to kω [20], and the electrical contact at the interface between CNTs and larger scale materials is much higher, often with values on the order of MΩ. For the local synthesis silicon/cnt/silicon platform, where the highest expected contact resistance is at R contact2. Thus, by heating the secondary bridge, higher temperatures can be achieved which can potentially contribute to the reduction of the overall resistance of the system by lowering R contact2. From the higher temperature and longer time annealing sample results, trends indicate that higher power input yields improved results and will be the focus of future studies. V. CONCLUSION Research to improve NEMS-based contacts for large-scale integration of nanomaterials into microelectronics and microelectromechanical systems is of continued importance. Reducing the interface electrical resistance of these materials will help enable their widespread use. Here, we have reported on fast and simple methods to reduce the contact resistance of in-situ grown CNT/silicon contacts using low- and high-temperature annealing. Two techniques were evaluated. The first involved low power inputs to the entire CNT/silicon system resulting in varied changes in resistance ratios. The second low temperature process involved (2) heating the secondary silicon bridge only. The low power inputs again yielded varied resistance ratio results. The higher power and longer time annealing process yielded the best results with all samples showing a decrease in resistance. Overall, the experimental results indicate that annealing via Joule heating improved the contact for 60% of the samples. The high temperature samples had resistance ratio decreases from 20 to over 80%. Further work is ongoing to determine optimal temperature and time ranges for reducing the contact resistance at the NEMS interface. ACKNOWLEDGMENTS The authors thank Siemens and DARPA S&T program for partial financial support for this work, Brian Sosnowchik for writing the data acquisition software program, and Yingqi Jiang for fabrication assistance. X. Wu and X. Guo are supported by China Scholarship Council program for their work at BSAC. X. Guo is also funded by the NSFC Project (No ) for research abroad from China. REFERENCES [1] Z. Chen, J. Appenzeller, J. Knoch et al., The Role of Metal-Nanotube Contact in the Performance of Carbon Nanotube Field-Effect Transistors, Nano Letters, vol. 5, no. 7, pp , [2] A. Javey, J. Guo, Q. Wang et al., Ballistic carbon nanotube field-effect transistors, Nature, vol. 424, pp , [3] A. Naeemi, and J. D. Meindl, Carbon Nanotube Interconnects, Annual Review of Materials Research, vol. 39, no. 1, pp , [4] T. Kawano, D. Christensen, S. Chen et al., Formation and characterization of silicon/carbon nanotube/silicon heterojunctions by local synthesis and assembly, Appl. Phys. Lett., vol. 89, pp , [5] O. Englander, D. Christensen, and L. Lin, Local synthesis of silicon nanowires and carbon nanotubes on microbridges, Appl. Phys. Lett., vol. 82, no. 26, pp , [6] T. Kawano, H. C. Chiamori, M. Suter et al., An Electrothermal Carbon Nanotube Gas Sensor, Nano Letters, vol. 7, no. 12, pp , [7] Y. Jiang, M. Q. H. Zhang, T. Kawano et al., Activiation of CNT Nanoto-Micro Contact via Electrical Breakdown, in Micro Electro Mechanical Systems, MEMS IEEE 21st International Conference on, Tucson, AZ, 2008, pp [8] Y. Chai, Z. Xiao, and P. C. H. Chan, Low-Resistance Carbon Nanotube Contact Plug to Silicon, Electron Device Letters, IEEE, vol. 30, no. 8, pp , [9] Y. Zhang, T. Ichihashi, E. Landree et al., Heterostructures of Single- Walled Carbon Nanotubes and Carbide Nanorods, Science, vol. 285, no. 5434, pp , [10] H. Maki, M. Suzuki, and K. Ishibashi, Local Change of Carbon Nanotube-Metal Contacts by Current Flow through Electrodes, Jpn. J. Appl. Phys., vol. 43, pp , [11] J. A. Rodriguez-Manzo, F. Banhart, M. Terrones et al., Heterojunctions between metals and carbon nanotubes as ultimate nanocontacts, PNAS, vol. 106, no. 12, pp , [12] C. Chen, L. Liu, Y. Lu et al., A method for creating reliable and lowresistance contacts between carbon nanotubes and microelectrodes, Carbon, vol. 45, no. 2, pp , [13] J.-O. Lee, C. Park, J.-J. Kim et al., Formation of low-resistance ohmic contacts between carbon nanotube and metal electrodes by a rapid thermal annealing method, J. Phys. D: Appl. Phys., vol. 33, no. 16, pp , [14] Y. Woo, G. S. Duesberg, and S. Roth, Reduced contact resistance between an individual single-walled carbon nanotube and a metal electrode by a local point annealing, Nanotechnology, vol. 18, 2007.

5 [15] L. Dong, S. Youkey, J. Bush et al., Effects of local Joule heating on the reduction of contact resistance between carbon nanotubes and metal electrodes, J. Appl. Phys., vol. 101, no. 2, [16] A. A. Kane, T. Sheps, E. T. Branigan et al., Graphitic Electrical Contacts to Metallic Single-Walled Carbon Nanotubes Using Pt Electrodes, Nano Letters, vol. 9, no. 10, pp , [17] Y. Q. Jiang, Q. Zhou, and L. Lin, "Planar MEMS Supercapacitor using Carbon Nanotube Forests." pp [18] A. N. Goldstein, C. M. Echer, and A. P. Alivisatos, Melting in Semiconductor Nanocrystals, Science, vol. 256, pp , And references contained therein. [19] M. Takagi, Electron-Diffraction Study of Liquid-Solid Transition of Thin Metal Films, J. Phys. Soc. Jpn., vol. 9, pp , [20] Q. Ngo, D. Petranovic, S. Krishnan et al., Electron Transport Through Metal-Multiwall Carbon Nanotube Interfaces, IEEE Transactions on Nanotechnology, vol. 3, no. 2, pp , 2004.

ENS 06 Paris, France, December 2006

ENS 06 Paris, France, December 2006 CARBON NANOTUBE ARRAY VIAS FOR INTERCONNECT APPLICATIONS Jyh-Hua ng 1, Ching-Chieh Chiu 2, Fuang-Yuan Huang 2 1 National Nano Device Laboratories, No.26, Prosperity Road I, Science-Based Industrial Park,