Electromigration Measurements in Thin-Film IPD and ewlb Interconnections

Transcription

1 Electromigration Measurements in Thin-Film IPD and ewlb Interconnections by Robert Frye, Kai Liu*, KyawOo Aung**, and M. Pandi Chelvam** RF Design Consulting, LLC 334 B Carlton Avenue Piscataway, NJ 0885 USA bob@rfdesignconsulting.com * STATS ChipPAC, Inc West Greentree, Ste. 117 Tempe, AZ USA Tel: kai.liu@statschippac.com ** STATS ChipPAC, Ltd. 5, Yishun Street 23, Yishun, , Singapore kyawoo.aung@statschippac.c Copyright Reprinted from 2012 Electronic Components and Technology Conference (ECTC) Proceedings. The material is posted here by permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any STATS ChipPAC Ltd s products or services. Internal or personal use of this material is permitted, however, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or distribution must be obtained from the IEEE by writing to pubs-permission@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

2 Electromigration Measurements in Thin-Film IPD and ewlb Interconnections Robert Frye, Kai Liu*, KyawOo Aung**, and M. Pandi Chelvam** RF Design Consulting, LLC 334 B Carlton Avenue Piscataway, NJ 0885 USA bob@rfdesignconsulting.com * STATS ChipPAC, Inc West Greentree, Suite 117 Tempe, Arizona 85284, USA Tel: kai.liu@statschippac.com ** STATS ChipPAC, Ltd. 5, Yishun Street 23, Yishun, , Singapore kyawoo.aung@statschippac.com pandi.marimuthu@sg.statschippac.com Abstract In this paper we describe measurements of electromigration failure times in the metal traces of silicon Integrated Passive Devices (IPDs) and in the redistribution layers of embedded Wafer-Level BGA (ewlb) structures, for both and traces, and for via connections between the two metal layers. The results of the test are used to determine the coefficients of Black s Equation, which is then used to find the extrapolated lifetimes. Maximum current density design guidelines are derived from these results to ensure device reliability in worst-case operation. Some minor differences are observed between these results and similar results for interconnections in conventional ICs. These differences probably arise from the larger conductor cross section and the softer organic dielectrics in IPDs and ewlb packages. Introduction Early in the development of integrated circuit technology, electromigration was identified as a problem in interconnections. The phenomenon was examined by Black in 1967 [1]. Statistical analysis of failures showed that the median time to failure (MTTF) of an electronic component as a result of electromigration could be modeled by the equation A Ea kt MTTF e (1) n J In Equation 1 (Black s equation) A is a constant, J is the dc current density in the conductor, and E a is the activation energy. The current exponent, n, was typically observed to have a value of about 2, but larger and smaller values have been observed. Furthermore, the failures showed a log-normal distribution 1 f ( t) exp t 2 1 ln 2 t MTTF 2, (2) where σ is the standard deviation. Figure 1 shows a sketch of the basic processes that occur as a result of electromigration. The dc flow of electrons from the cathode to the anode of the conductor imparts momentum to the metal atoms. The flux of metal atoms toward the anode results in compressive stress at this end of the conductor. Similarly, there is a reverse flux of vacancies that propagate toward the cathode, resulting in tensile stress at this end. The stress build-up occurs in regions of flux divergence i.e. regions where the metal atoms or vacancies accumulate. These anode (+) excess metal atoms (compressive stress) electron flow vacancies (tensile stress) Figure 1: Electromigration processes cathode (-) regions may be the ends of the conductors, a transition from hot to cold or a transition in the current density due to a widening or narrowing of the conductor. In analytical treatments of the problem of electromigration, the boundary conditions play an important role. Electromigration is largely understood today to be the linked to diffusion processes, and is inherently related to mechanical stresses in the conductors. Studies by Blech [2] showed that failure does not occur in conductors that are shorter than a critical length. As indicated in Figure 1, there is a stress gradient along the conductor. This may produce a diffusive flow of atoms or vacancies that counters the electromigration. Conductors that are shorter than the socalled Blech length reach a steady-state condition in which the two forces of electromigration and stress-induced diffusion are in balance. Such short conductors are immune to electromigration failure. Failure of the conductor may result from one of two mechanisms. In the region of compressive stress, the conductor may form hillocks or extrusions that push outward, shorting to adjacent conductors. More commonly, in the region of tensile stress, the vacancies may coalesce and nucleate a void. Once formed, voids block the flow of current. This leads to increased current density in the bottleneck that is formed, accelerating the electromigration process near the void. These voids may rapidly grow and eventually result in open circuit failure. Like other diffusion processes, vacancy diffusion is a thermally activated process, accounting for the behavior observed by Black. The process is complicated, however, by the fact that there are several different pathways for vacancy diffusion in thin-film metal interconnections. The conductors themselves are typically polycrystalline with grain size on the order of a few microns. Most of the cross section is filled by the bulk lattice of the crystallites making up the metal trace. However, the atoms in the crystal lattice are in a low-energy state, very tightly bound. The grain boundaries make up a much smaller fraction of the cross section, but it is much /12/$ IEEE 1304

3 easier for diffusion to occur in these disordered regions since the atoms are less strongly bound. Similarly, diffusion may occur along the outer surface of the conductor. Some metals are deposited using a barrier layer or seed layer, and interfacial diffusion may occur at the boundary between these two different metals. Each of these mechanisms has its own characteristic activation energy. The predominance of any particular mechanism depends on a variety of factors, including the conductor geometry, average grain size, surrounding dielectric or barrier metal, etc. Typical activation energies for diffusion in the pathways discussed above are listed in Table 1 [3]. Table 1: Typical activation energies (ev) for diffusion processes in interconnections. metal or alloy lattice grain boundary interface surface Al NA NA Al/Cu NA Cu Initially, in silicon integrated circuits using conductors, electromigration was a major reliability problem. Aluminum, being a relatively light atom and having a low melting temperature for a conductor, is especially prone to electromigration. As Table 1 shows, the activation energies for diffusion through the crystal lattice are high. At ordinary operating temperatures, this pathway does not account for appreciable electromigration. Also, forms a very strong surface oxide that binds up the surface atoms and essentially eliminates surface migration. It was found that the grain structure of the metal film strongly affects the susceptibility to electromigration failure. The mean time to failure can be increased by one to two orders of magnitude by the addition of a few atomic percent to the metal film [4]. The added resides preferentially in the grain boundaries between adjacent crystallites, and forms a barrier to diffusion. The used in the interconnections described in this study (and essentially all semiconductor interconnections, for that matter) is doped with a small percentage of for this reason. The electromigration resistance of modern IC interconnections is strongly influenced by their small dimensions. For both and traces, submicron trace widths are much smaller than the average grain size, so over much of its length, the trace cross-section is filled by a single crystallite. This so called bamboo structure results in greatly improved electromigration resistance, since the grain boundary pathway is not continuous. Copper has become the conductor of choice in more recent generations of ICs. Copper is a heavier atom and has a higher melting temperature than, so it is expected to be more resistant to electromigration. This is reflected in the very high activation energy for lattice diffusion. However, in active silicon devices is a fast-diffusing impurity that degrades the carrier minority lifetime, so it is necessary to surround the metal with a suitable barrier metal. In submicron interconnections, a significant fraction of the conductor cross section is taken up by this material, and interfacial diffusion often dominates. The object of electromigration testing is to determine the variables in Black s equation. In ordinary operation, it is expected that the time to failure of a particular interconnection will be very large (e.g. decades), making it experimentally impractical to observe. The basis of all electromigration tests is to accelerate the failure by conditions of high current or high temperature so that it occurs in a reasonably observable amount of time. Assuming the dependence expressed by Black s equation to be valid, the measured behavior can be extrapolated to ordinary operating conditions. For operation at current density J OP and temperature T OP, the relationship between the time-to-failure in operation and the observed time-to-failure in the test, from Black s Equation, is expected to be n JTEST Ea ktop Ea kt TTF TEST OP TTFTEST e J. (3) OP An issue of some controversy in many electromigration studies is the value of the current exponent, n. Temperature dominates the observed time-to-failure, with current density playing a secondary role. Electromigration testing is typically performed at temperatures of 200 to 300C and at current densities more than an order of magnitude above maximum rated use. The temperature effect accounts for about 7 orders of magnitude decrease in the time-to-failure. However, the value of the current exponent n between 1 and 2 makes a difference of more than an order of magnitude in the calculated MTTF. Experimentally, it is often difficult to independently measure n. The high current densities that are used to accelerate failure generally lead to some self-heating, so the effects of current density variations are masked by the strong thermal dependence. In the development of as an interconnection conductor for ICs, there was considerable debate about the appropriate value of the current exponent. Experiments suggested that surface or interfacial diffusion is the dominant pathway for electromigration in most interconnections. Early theoretical analysis suggested that a value of n=1 was appropriate for this pathway, leading to fairly pessimistic extrapolations of the electromigration properties of. Subsequent analysis, however, has led to a generally accepted resistance t n ~1/J 2 time failure t g ~1/J Figure 2: Time evolution of trace resistance in electromigration failure 1305

4 and more sophisticated model of the sequence of events leading to electromigration failure [5,6]. Figure 2 shows the time evolution of trace resistance in a typical electromigration failure [7]. The first stage involves the nucleation of voids. During this stage, the resistance is relatively unaffected as vacancies diffuse toward the cathode. When the number of vacancies and the associated stress reach a critical threshold, they coalesce into a void. This void creation may be associated with a large release of stress. The time required for void nucleation, t n, is expected to depend inversely on the square of the current density (n=2). Void formation is followed by a period on void growth, t g. Void growth is a runaway effect, since the growth of the void increases the current density in the remaining metal adjacent to the void. Void growth is accompanied by an increase in resistance, and eventually leads to open circuit failure. The time required for this void growth is expected to vary inversely with current (n=1). The experimentally observed value of n depends on which of these two times dominates the time-to-failure. As mentioned above, vacancy diffusion in submicron IC interconnections using is mainly along surface or interfacial pathways. These are strongly influenced by process and structural conditions, including surface barrier layers and the surrounding dielectric material. These conditions may vary considerably from one device to another, and surface conditions on significantly affect the kinetics of void nucleation and growth. This sensitivity to process probably accounts for the wide variation on observed values of n. Moreover, at high current density where electromigration is performed, t g may dominate the time-to-failure leading to observed n=1 behavior, whereas at lower currents where devices are operated t n becomes dominant. EM tester structure Figure 3 shows a cross section of the interconnection structures in the electromigration testers. This sketch is roughly shown to vertical scale. The interlevel dielectric is a photo-definable organic film. Two different conductors were used: The lower layer of metal is a 2μm thick layer of deposited directly onto the surface of an oxidized silicon substrate by physical vapor deposition (PVD). that receive a subsequent redistribution layer (RDL) for flip-chip or ewlb products. The upper layer is an 8μm thick layer of deposited by selective electroplating. The layer is plated up from a seed layer that serves as a barrier between the and the underlying dielectric, and 8μm 2μm dielectric 8μm barrier metal also promotes adhesion. This type of structure is common to IPD, fan-in Chip-Scale Packages (CSPs) and fanout ewlb products. The layer is consistent with those used in IPD products, but may also be considered to be representative of the layer in the bond pads of packaged ICs. In comparison to the inorganic dielectrics (silicon nitride and oxide) used in conventional semiconductor devices, the organic dielectrics are much softer material. This may affect the stress build-up during electromigration, resulting in significantly different behavior in these types of structures as compared with conventional semiconductor devices. For the layer, the barrier metal layer also may play a significant role in the electromigration, since interfacial diffusion along the boundary between the and the barrier layer is a key mechanism in the process. In these structures, the barrier metal occupies a much smaller fraction of the trace cross section than in ICs. Moreover, as compared with ICs, the trace dimensions are much larger. Minimum linewidth in both the and layers for these technologies is typically 10μm. This is significantly larger than the average grain size in the metal films. Consequently, grain boundary diffusion may play a greater role. Commonly-used rules-of-thumb in IC design for interconnections is to limit the dc current density to a maximum of 1mA/μm 2 in and 5mA/μm 2 in. However, the conductor dimensions, deposition methods and surrounding dielectric material are quite different for packaging structures than for ICs. All of these factors influence the microstructure and stress in the metals, and may also affect the electromigration characteristics. The purpose of this study is to evaluate electromigration in representative structures to validate or modify the design guidelines. Experimental device configuration Figure 4 shows the layout of the electromigration test structures. The testers use a four-probe Kelvin structure, and are modeled after the testers used in the JEDEC SWEAT (Standard Wafer-Level Electromigration Accelerated Test) method [8]. The M2 layer tester is shown on the left and the M1 layer tester on the right. In the plot, the M1 layer is shown in blue, and the M2 layer in orange. In each tester, current is forced through the wide I TEST + V SENSE - silicon oxide Figure 3: EM tester conductor structure Figure 4: Electromigration test structure 1306

5 traces connected to the probe pads in the upper-left and lowerleft. Voltage is sensed across the narrow portion of the path through the other two probe pads on the right. The narrow segment is nominally 10μm wide and 200μm in length. Accelerated failure testing is typically performed at current densities of several MA/cm 2, two orders of magnitude above the rated operating current. Assuming an exponent n=2 in Black s equation, this would accelerate failure by about four orders of magnitude. A much stronger effect, however, is the self-heating that occurs from the passage of high currents through the conductors. With these types of structures it is possible to observe electromigration failure in times on the order of minutes. The use of the Kelvin structure for the tester makes it possible to monitor the temperature of the conductor using the thermistor effect. As the temperature of the conductor increases, its resistivity also increases. By measuring the resistance of the sample in the early stages of the test (before the effects of electromigration start to cause local resistance increases) it is possible to infer the temperature rise caused by self-heating. The temperature coefficient of resistance (TCR) of metal films can be affected in some cases by added impurities that are introduced intentionally (as in the case of doped with a small percentage of ) or inadvertently (as in the case of electroplated ). As an initial check, the testers were first evaluated on a hot chuck at low current, where selfheating is negligible, over a range from room temperature to 130C. These tests are inherently limited by the uncertainties that arise from temperature gradients in a hot-chuck experiment. Within experimental uncertainty of a few degrees Celsius the temperature dependence of both the and samples closely matched the expected behaviors of pure and. These values are used in the subsequent analysis. No dedicated testers were available to measure electromigration in M1-M2 via structures, but the test samples also included via daisy-chain testers with a variety of via sizes. An example tester is shown in Figure 5. These testers have a similar Kelvin probe arrangement to measure resistance. Based on the resistivity versus temperature characteristics of pure and [9], both testers would show a nearly linear relationship between resistance and temperature over the temperature range from 200 to 700K. The behavior of is well modeled by the relationship 3 2 R R R T ( K) (4) R0 R0 R0 where R 0 is the measured resistance at room temperature (298K) and R is the resistance measured at high current where self-heating occurs. Similarly, for the relationship is 3 2 R R R T ( K) (5) R0 R0 R0 Note that in the Kelvin structure, the measured resistance only applies to the narrow part of the current path, so the measurement is insensitive to temperature variations near the probe pads from the heat sinking effects of the probes. I TEST Series chain of 100 vias + - V SENSE Figure 5: Via daisy-chain tester In the above relationship, the temperature is inferred from the change in the baseline resistance R 0. This quantity can be independently measured for the device under test (DUT). However, the value of the current density in Equation 1 is deduced from the applied current and the conductor cross section area. The test structure design uses a minimum dimension path width (10μm) to concentrate the current into the smallest possible cross-sectional area and to maximize the self heating that is obtained at a particular current value. The actual cross-section area of these small dimension conductors is especially sensitive to small deviations in the patterned linewidth that occur as a result of process variation, and the widths of narrow lines, in particular, are more prone to lithographic bias. The measured room-temperature resistance in the testers was used to determine R 0, and this value was compared with its ideal simulated value to determine the actual patterned linewidth in the testers. These results are listed in Table 2. Table 2: Tester parameters Parameter R 0 (Ω, measured) R 0 (Ω, simulated) inferred patterned line width (μm) The inferred values of line width listed in Table 2 were used to calculate the current densities in the testers. The simulated values shown in the table assume that the electrical conductivities in the metal films are S/m for and S/m for. These are a few percent lower than the ideal conductivity values, but past comparisons of sheet resistance and cross-sectional dimensions in IPDs have shown these values to give a better fit to measured results. These discrepancies between simulated and measured values may arise from either linewidth or layer thickness being somewhat different from the nominal designed value, but for current density calculations either correction is equivalent since only the cross-sectional area of the tester is important. 1307

6 Test procedure Example test current and measured response are illustrated in Figure 6. The test procedure consisted of first applying a low current stimulus (26mA) for 20s to measure R 0. This value is the lower set limit of the current supply, and is sufficiently low that it causes negligible self-heating. After measuring R 0, the current was ramped linearly to the test value over a period of 10s. The test values ranged from 820mA to 900mA for the samples and from 1900 to 2200mA for the. An example of the observed resistance versus time is shown in the lower part of Figure 6. At the start of the ramp-up, there is a dip in the measured resistance. This is an artifact caused the transient response of the voltmeter. Shortly after the completion of the current ramp, the resistance assumes a nearly constant value that is indicative of the sample temperature resulting from self heating. In the time between the application of the high test current and the eventual failure the resistance shows a small gradual increase. Equation 4 or 5 was used to convert the measured resistance into temperature. An example result from one of the testers is shown in Figure 7. After the initial fast rise in response to the current ramp-up, the calculated temperature settled to a nearly constant value with a gradual rise. Some of this rise may be attributable to the thermal timeconstant of the sample as it self-heats, but most of it, especially near the end of the test, is non-recoverable degradation caused by electromigration. As the test approaches complete open circuit failure, the resistance often shows a noisy characteristic. For subsequent analysis, the time-to-failure (TTF) is considered to be the elapsed time between completion of the ramp-up and this open-circuited condition. The test temperature, T 0, is measured 4s after completion of the ramp-up to allow for the system transient. A limitation of the self-heating test for IPDs is that the usable range of test conditions is restricted. At one extreme, low currents result in very long observed TTF. Higher currents decrease the observed TTF to a more practical experimental value, but excessive heating may cause other undesirable changes in the sample, obscuring the effect that is being measured. For these structures, in particular, the organic dielectrics typically show appreciable weight loss, indicating decomposition, above about 350C. This may cause blistering or other mechanical changes that can affect the mechanical environment of the conductors. The practical range of the test ranged from about 190 to 340C. - + before after Figure 8: Micrographs of example testers before and after electromigration testing. Figure 6: Test current and measured response Figure 7: Example observed temperature versus time characteristic After failure, visual inspection of the samples shows a charred spot, indicative of localized heating above 270C for the dielectric. The site of the failure is located in the narrow part of the tester nearer the cathode (negative voltage terminal). Example micrographs of the testers before and after electromigration failure are shown in Figure 8. The site of the failure, near the cathode, is indicated by the arrow. The higher current density and temperature in the narrow part of the trace causes a more rapid migration of metal compared with the wider regions near the probe contacts, so there is a flux divergence in the flow of vacancies. The accumulation of vacancies in this region leads to eventual void nucleation and a localized high resistance area, accompanied by increased localized heating near the eventual failure point. This sequence leads to accelerated run-away failure at the site of the void. It is this localized failure that gives rise to the sharp resistance increase in the latter parts of the test sequence. The observed charring of the dielectric in this region occurs near the end of the failure sequence. The fact that the failure point is invariably located toward the cathode 1308

7 end of the tester is visual evidence that these failures are a result of electromigration. For the testers, the darkening of the dielectric is more widespread and pronounced, suggesting that the local temperature immediately before failure is higher. In addition, for the samples the failure is located nearer the center of the narrow line section. This suggests that there is some difference in the flux divergence in the two cases, or perhaps some difference in the temperature profile along the length of the testers. Experimental results and analysis As mentioned above, the experimentally accessible range of temperatures was from 190 to 340C. For the testers, these limits correspond to test current levels ranging from 840 to 900mA, and for from 1800 to 2200mA. At lower currents and temperatures the TTF becomes inconveniently long (e.g. many hours) for wafer-probe testing. Higher currents and temperatures may result in thermal damage to the integrity of the sample. These test conditions correspond to current densities of several MA/cm 2. Such levels are one to two orders of magnitude higher than the maximum levels specified by common design guidelines. A problem in general with self-heating electromigration tests is that over the experimentally observable range of test conditions it is not possible to independently determine the value of the current exponent, n. The fitted value of the activation energy is very nearly the same for different assumed values of n between 1 and 2. But as discussed above, the extrapolated value of MTTF to ordinary conditions of Figure 9: Resistance versus time for two example tests temperature and current varies greatly depending on this assumption. Figure 9 shows example resistance versus time plots for the and testers. From the observed time evolution of the resistance, it is clear that failure in these devices is dominated by the very gradual increase in resistance leading up to the void nucleation process. By comparison, the time required for void growth leading to failure is short, especially for the sample in which it is hardly apparent. Based on these observations, it is reasonable to assume that n=2 kinetics apply to these samples. Black s Equation can be rearranged as n ln( TTF J ) ln( A) Ea kt. (6) Figure 10 shows a plot of the measured results for testers using this relationship, assuming n=2. Plotting the data in this way, the values of A and E a can be derived from the intercept and slope, respectively, of the fitted data. Furthermore, the standard deviation, σ, can be calculated from the scatter in the data points assuming a log-normal distribution. In this plot, the units of current density are MA/cm 2. The solid lines are least-squared-error fits to the measured data. The fitted activation energy for the samples is 0.597eV, consistent with the value for electromigration resulting from diffusion of along the grain-boundaries listed in Table 1. The fitted activation energy for the observed in these samples is 0.857eV, consistent with interfacial diffusion [10]. Figure 11 shows extrapolation of the measured results for the and electromigration testers. The dashed lines in the figure show one standard deviation in the measured data, assuming the log-normal distribution described by Black. At the higher temperatures and currents of the test, is actually less robust to electromigration than. However, when extrapolated to typical operating temperatures it shows greater expected time to failure because of its higher activation energy. Also, in these tests the observed variation in TTF about the median value was less for. As described above, the via tests were performed on a Figure 10: Experimental results, assuming n=2. Current density, J, is A/cm 2, TTF is seconds. Figure 11: Extrapolated lifetime. The dashed lines show one standard deviation in the measured data assuming log-normal distribution. 1309

8 structure consisting of a chain of 100 vias. This raises two experimental issues. The first issue is a statistical one. Because the tester consists of a series arrangement of vias, it is only possible to observe the earliest failure in the measured population. Consequently, the observation is restricted to the worst-case tail of the experimental distribution. The second issue is that because the metals on the two sides of the via are dissimilar, it is expected that there will be polarity dependence to the failure. This is illustrated in Figure 12. ANODE + void formation barrier metal void formation CATHODE - Figure 12: Void formation in the via chain. Figure 12 shows a pair of vias in the chain. Assuming that failure occurs in the via (as opposed to line failure) it is expected to occur from the formation of voids in the via contact area, leading to open circuit failure. The direction of electron flow will be from the cathode to the anode. Consequently, in the via shown on the left, voids will develop from the action of the electron flow, and in the via shown on the right voids will form. The observed failure will depend on which of these two mechanisms is the more active. Since there are 50 such back-to-back via pairs in the tester, the outcome of the test corresponds to the bottom 2% (2.326σ) of the time-to-failure distribution for the weaker of the two metal interfaces. Figure 13 shows the time evolution of resistance in an example via test. Similar to the trace tests, the resistance shows a very gradual rise followed by an abrupt transition to failure. This indicates that it is also appropriate to use n=2 in Black s equation for these structures. The experimentally fitted activation energy for the via electromigration test was 1.038eV. This is similar to the value found for the trace failures, leading to the tentative conclusion that the void formation at the via is predominantly formed in the. Because the experiment only allows observation of the tail of the distribution for via failure, it does not provide direct information about the statistical distribution of the failures. Moreover, a much smaller number of experimental samples were available for this test. However, based on the observed similarity to the trace failures, it is reasonable to assume that the statistical spread in failure times will also be similar. Figure 14 shows the measured results for the via tests, corrected upward by 2.326σ, using the standard deviation measured for the traces. As indicated in Figure 12, two different via sizes are included in the results. The vias were octagonal in shape, with diameters of 12um and 14μm. The current density used in the plot was derived by dividing the total applied current by the area of the via opening. In actual fact, it is likely that this current is nonuniform owing to current crowding effects. The metal traces in the via testers were 20μm wide, and the currents used in the test would not be expected to cause electromigration failure in the lines, so it is reasonably certain that the observed failures occurred in the vias, not in the traces. Unfortunately, the back-to-back arrangement of the vias in the via test chains does not permit the independent measurement of vias under different polarities. Consequently, it was only possible to observe failure attributed to migration. As observed in the trace measurements, is more susceptible to electromigration than at high temperature. However, at the lower temperatures of device operation, is more susceptible. So, it may be the case that migration limits the reliability of vias in ordinary operating conditions. It is not possible to resolve this question without further measurements on testers designed to measure individual vias with either polarity. There is some possibility that the measured results lead to overly optimistic predictions of via reliability, but at the high end of the range of device operating temperatures used to determine design guidelines, and are actually comparable in performance, so the resulting error in the predicted reliability is probably small. Table 3 lists the fitted parameters from all of the above results. Figure 13: Example resistance versus time for a via test Figure 14: Experimental results for the via daisy-chain test, assuming n=2. Current density, J, is A/cm 2, TTF is seconds. These results have been corrected to account for the large number of vias in the series tester, using the statistical parameters derived from the trace testers. 1310

9 Table 3: Fitted electromigration parameters for IPD and Layer A (A 2 s/cm 4 ) Ea (ev) Electromigration guidelines. The parameters of Black s equation listed above can be used to calculate cumulative failure statistics for these metal structures. Maximum current density guidelines are chosen such that the 3σ tail of the distribution (the weakest 0.1% of the population) is 10 years under worst-case operating conditions. In other words, 99.9% of the population will survive at least 10 years. The resulting design guidelines and cumulative failure statistics are summarized in Table 4. Conclusions The guidelines for maximum current density in traces derived from this study are quite similar to those commonly adopted for IC traces. The structural differences in the surrounding dielectrics appear to have little effect on the electromigration characteristics of the traces. This is not very surprising, since naturally forms a strong surface oxide and interfacial or surface diffusion is not generally found to be significant for this metal. n 80C Aluminum Copper Al-Cu via * *assumed Table 4; Maximum current density guidelines and cumulative time-to-failure for IPD, RDL and ewlb structures structure Max J (ma/μm 2 ) Sustained operation at 80C Time to cumulative failure (years) 0.1% (3σ) 2.3% (2σ) 15.9% (σ) Al trace Cu trace Al-Cu via structure Max J (ma/μm 2 ) Sustained operation at 100C 50% (MTTF) Time to cumulative failure (years) 0.1% (3σ) 2.3% (2σ) 15.9% (σ) Al trace Cu trace Al-Cu via % (MTTF) The maximum current guidelines for the traces are somewhat lower than in typical IC interconnections, by a factor of 3 to 5. The observed activation energy of the failure suggests that it is mainly controlled by interfacial or surface diffusion. Considering this, it is reasonable to suppose that the difference in the surrounding dielectric may be responsible for much of this difference. In particular, the soft organic dielectrics used in these types of structure are mechanically quite different from the hard, inorganic dielectrics used in ICs and these mechanical differences may substantially change the stresses and, thereby, the kinetics of vacancy diffusion. The lower resistance to electromigration in the, as compared with conventional ICs, does not pose a practical limitation in most situations. The thickness in these package structures is sufficient to ensure that electromigration reliability is almost always limited by other factors like the underlying IC metallization or by the solder connections. The establishment of the guidelines is important, however, mainly for the design of power supply routing in package structures where sufficient trace linewidth is needed to ensure reliability. Acknowledgments The samples used in these electro-migration tests were made by StatsChipPAC R&D team. The electrical testing was done by Robert Melville at Emecon, LLC. References 1. J. R. Black, Mass Transport of Aluminum by Momentum Exchange with Conducting Electrons, 6 th Int l Reliability Phys. Symp. IEEE, p148, I. A. Blech, Electromigration of Thin Aluminum Film on Titanium Nitride, J. Applied Physics, 47, , J. R. Lloyd, Reliability of Copper Interconnections, Reports form Lloyd Technology Associates, Inc M. C. Shine and F. M. d Heurle, Activation Energy for Electromigration in Aluminum Films Alloyed with Copper, IBM J. Research and Development 15, 378, Sep M. A. Korhonen, P. Borgesen, D. D. Brown and C. Y. Li, Stress Evolution due to Electromigration in Confined Metal Lines, J. Appl. Phys 73, 3790, M. Shatzkes and J. R. Lloyd, A model for conductor failure considering diffusion concurrently with electromigration resulting in a current exponent of 2, J. Applied Physics, 59, J. R. Lloyd, Electromigration Failure, J. Applied Physics, 69, , JEDEC Publication 119A, Dorf, The Electrical Engineering Handbook, p CRC Press, 1993 ISBN C. K. Hu, R. Rosenberg and K. Y. Lee, Electromigration Path in Cu Thin-film Lines, Applied Physics Letters, Vol 74, No. 20,