SiC MOSFET Gate Oxide Breakdown From Extrinsic to Intrinsic

Transcription

1 SiC MOSFET Gate Oxide Breakdown From Extrinsic to Intrinsic J. Chbili,3, Z. Chbili,, A. Matsuda, J. P. Campbell, K. Matocha 4, K. P. Cheung * ) NIST, MD ) George Mason University, VA 3) Laboratoire SSC, Faculté des Sciences et Techniques, Morocco 4) Monolith Semiconductor Inc, TX

2 Two years ago in this workshop.

3 3 Our normalized data shown last year Ln(-Ln(-F)) % 5% -4-5 % -6-7.% Assume power system with % failure probability in years Each system has multiple chips making each chip s failure probability even lower The extrinsic part of the failure distribution is what really counts. 3 TBD

4 Thick oxide data in the silicon world had similar problem. Ogier, J. L. et al., Solid State Dev. Res. Conf., ESSDERC '95. pp 99-3 > Effective thinning model does not work. > Analysis should be done with joint distributions. 4

5 LN(-LN(-F)) % % T 63 : 5s, β: LN(-LN(-F)) Typical extrinsic β value is < Failure rate decreases with time. Screening possible but not guaranteed. Effective thinning tends to have successful screening T 63 : 5s, β: 5-5 Stress Time [s] 4% extrinsic case If extrinsic β value > Failure rate increases with time. Screening impossible. Direct analysis leads to large intrinsic characteristic time underestimation... The extrinsic distribution with low beta determines failure. Failure fraction scaling: LN(-LN(-F)) % 5% ~6s ~9s LN(-LN(-F)) Active area scaling: Stress Time [s] 5

6 Small sample size can be very misleading when studying extrinsics Failure distributions of different sample sizes 4 k devices 5devices 4 Failure distributions of different sample sizes k devices 5devices Ln(-Ln(-F)) Ln(-Ln(-F)) E+ E+ E+ E+3 E+4 E+5 E+6 Tbd (s) - - E+ E+ E+ E+3 E+4 E+5 E+6 Tbd (s)

7 The literature is full of reports on the effect of contamination on oxide breakdown Yamabe, K. & Taniguchi, K., IEEE Trans. Electron Dev., 3(), 43 48(985). Uchida, H. et al. IEDM '9. pp Verhaverbeke, S. et al., IEDM '9. pp Vermeire, B. et al., IEEE Advanced Semiconductor Manufacturing Conf. pp Yamabe, K. & Taniguchi, K., IEEE J. Solid-State Circuits (), (3). Gui, D et al. Physical and Failure Analysis of Integrated Circuits, IPFA 8. pp - 4 Contamination tends to weaken the oxide substantially not a subtle effect lead to the idea of effective (localized) thinning model Lee, J., I. C. Chen, et al. Symposium on VLSI Technology 986 Since it does not work, we need a new model that can point the direction to improvement. - One that can explain why further improvement of cleaning does not work. 7

8 The lucky defect model for early breakdown failure Differentiate from contamination related extrinsic failures 8

9 Lucky Defect Model High-Field Stress High-Field Stress with lucky defect Current increases locally!!! Most oxide breakdown models are current driven. 9

10 How to quantify this? What kind of defect distribution can lead to the observed TDDB extrinsic tail?

11 Trap Assisted Tunneling is defined by the joint probability of : Tunneling into the defect (T ) Tunneling out from the defect (T )... Maximum when probabilities T and T are equal. when defect is at xx EE oooo = WW EE oooo Independently of the barrier height!! Important condition: Defect energy matches the electrons in the inversion layer.

12 TAT leads to higher current locally Evaluating the impact on lifetime must account for this. Area scaling: T BD = T BD A A /β + The weakest link model Net result: TT BBBB = TT BBBB JJ FFFF JJ FFFF + JJ TTTTTT AA AA DDDD /ββ = TT BBBB ηη AA AA DDDD /ββ Area (size) of the defect

13 AA DDDD? Cannot be a point with no dimension because of quantum confinement effect. If it was a point, there can be no energy level in it! For our model : nm². Physically reasonable Impacts very little the model results. 3

14 Uniform distribution with a density of defects 8 cm -3 (E OX = 8.3 MV/cm, x(e OX ) = nm ) Z (nm) Uniform Defect Distribution 4K Ln(-Ln(-F)) k devices - Uniform distribution of defects % %. %.5 Y (cm).5.5 X (cm) % T BD [s] % of the simulated devices experience early failures similar to the experimental results 4

15 Z(nm) Exponential distribution peak at the interface and zero at the gate with a density of defects 8 cm -3 (E OX = 8.3 MV/cm, x(e OX ) = nm ) Y(cm) Exponential Distribution 4K.5 X(cm).5 Ln(-Ln(-F)) k devices - Exponential distribution of defects % T BD [s] % %.95 % % of the simulated devices experience early failures Higher amount of lucky defects in this distribution. 5

16 Normal distribution centered at 5nm with.58 nm standard width and a defect density of 8 cm -3 (E OX = 8.3 MV/cm, x(e OX ) = nm ) Normal Defect Distribution 4K k devices - Normal distribution of defects Z(nm) %.5.5 Y(cm) X(cm) Normal Defect Distribution 4K Ln(-Ln(-F)) Z(nm) 5 T BD [s] 4 3 Y(cm).5 X(cm).5 6

17 Normal distribution centered at 5 nm with.9 nm standard width and a defect density of 8 cm -3 (E OX = 8.3 MV/cm, x(e OX ) = nm ) Normal Defect Distribution 4K Z(nm) Z(nm) Y(cm) X(cm) Normal Defect Distribution 4K.5 Ln(-Ln(-F)) k devices - Normal distribution of defects % % % T BD [s] Y(cm).5 X(cm).5 7

18 Normal distribution centered at.5 nm with.9 nm standard width and a defect density of 8 cm -3 (E OX = 8.3 MV/cm, x(e OX ) = nm ) Normal Defect Distribution 4K 5 Z(nm) Z(nm) Y(cm).5.5 X(cm) Normal Defect Distribution 4K Ln(-Ln(-F)) k devices - Normal distribution of defects % % - 3% % T BD [s] Y(cm).5 X(cm).5 8

19 CCoooooooooooooooooo Defects in the oxide contribute to the early failures Improvement of the oxide process growth 9

20 SiC MOSCAP fabricated in a silicon foundry Leverage the low extrinsic failure oxide technology.

21 Cumulative failure distribution for more than 75 SiC MOS caps showing no extrinsic failures (raw data) SiC nmos capacitors (4 x 5 um ) with 5 nm thermally grown SiO

22 Previously, we reported that SiO on SiC is quite similar to on Si C 8-35C Our data Log(T 63% ) C McPherson IEDM98 75C 9nm McPherson IEDM98 5 9nm Suehle TED97 4C nm Suehle TED97 4C (5nm) E OX (MV/cm)

23 Our new data is a lot better than our old data 9 Log(T 63% ) C 8-35C - 375C 5C C C 3C New E OX (MV/cm) 3

24 Our SiO on SiC is better than Si data! 9 8 5C Log(T 63% ) C 5C 3C McPherson IEDM98 75C 9nm McPherson IEDM98 5 9nm Suehle TED97 4C nm E OX (MV/cm) Suehle TED97 4C (5nm) How is it possible? 4

25 Silicon data for thicker oxide are influenced by extrinsic failures... LN(-LN(-F)) % 5% ~6s ~9s LN(-LN(-F)) In mid to late 9s, most companies figure out how to grow gate oxide with negligible extrinsic failures. However, by then there are very few studies of thick oxide grown using the new technology Stress Time [s] 5

26 Measured lifetime exhibits a steep field dependent activation energy (Not previously observed in SiC) 6

27 Thin oxide Thick oxide 7

28 Proc. 9th European Solid-State Device Research Conf., 999, pp356. Temperature effect is oxide thickness dependent 8

29 Measured lifetime exhibits a steep temperature dependent field acceleration (Not previously observed in SiC) Suehle et al. IRPS- 94, pp. 3.9 nm Yassine et al. EDL-, 39(999) 9

30 Can we explain why the slope is steeper for SiC? Log(T 63% ) C C 5C 3C McPherson IEDM98 75C 9nm McPherson IEDM98 5 9nm Suehle TED97 4C nm Suehle TED97 4C (5nm) E OX (MV/cm) 3

31 One potential source is extrinsic failure distribution that depends on stress condition. Oussalah et al. TED-54, 73(7) 3

32 Besides difference in extrinsic failures Part of it is due to sub-band energy different. EE jj = ħ mm 3 3 ππππf ss,eff jj F ss,eff = qq(ηηnn ss + NN dd )/εε Si or F ss,eff = ηηff ss ηη: weighting coefficient..75 for electrons in inversion,.8 for holes in accumulation For high oxide field, only the lowest sub-band matters For silicon, the longitudinal effective mass: m l =.98 For SiC, the transverse effective mass: m t =.4 3

33 .7 Barrier height from st subband.6 Barrier height [ev] Si SiC Oxide field [MV/cm] 33

34 FN tunneling Tunneling current [A].E-7.E-8.E-9.E-.E-.E-.E-3 SiC Si Si vs SiC Oxide field [MV/cm] Cuurent ratio, SiC/Si 5.E-4 5.E Oxide field [MV/cm] As field drops, the tunneling current for SiC drops faster exponentially. Steeper slope 34

35 Conclusion & 3C --- with high β C C Failure fraction scaling: Log(T63%) EOX (MV/cm) 5C 3C McPherson IEDM98 75C 9nm McPherson IEDM98 5 9nm Suehle TED97 4C nm Suehle TED97 4C (5nm) Lifetime factor for, times larger device.e-.e-3.e-5.e-7.e-9.e-.e-3.e-5.e-7.e-9.e-.e-3.e-5 For minimum processed capacitors. Active area scaling:,µ cm Shape factor β =, 35