Defect Engineering in Advanced Devices on High-Mobility Substrates
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1 Defect Engineering in Advanced Devices on High-Mobility Substrates C. Claeys 1,2 1 IMEC, Leuven, Belgium 2 E.E. Dept., KU Leuven, Leuven, Belgium
2 Outline Introduction Defect Studies Why important Challenges ITRS and Scaling Problems Solutions Dislocation Generation High Mobility Substrates Fabrication Aspects Defect Identification Electrical Performance (leakage, lifetime, LF noise) Conclusions
3 Introduction Interest in defects due to their impact on: physical processes (e.g. diffusion) electrical device performance yield Interest since the early days of semiconductors, but now there is physical insight No longer trial and error but ENGINEERING Origin of defects can be Grown-in (dislocations, vacancies, interstitials, swirls, COPs ) Process-induced (dislocations, precipitates, metals, twinning, ) Scaling is putting stringent requirements on the resolution of the analytical techniques
4 Introduction Downscaling Channel doping levels: UTSOI High-κ dielectrics FUSI/Metal gates carrier mobility control
5 Scaling Aspects: Mobility Control Use of high-k dielectrics Reduction of the low-field mobility due to remote phonon scattering Use of metal gates or FUSI Increase of the low-field mobility R.Chau et al., IEEE Electron Device Lett., 25, (2004) 408
6 Scaling Aspects: Mobility Boosting Use of high-k dielectrics + metal gate + strained Si n-mos S. Datta et al, IEDM 2003, p % increase for strained Si/SiGe
7 Strain Engineering Mobility improvement: Strain engineering Strained Si on SiGe virtual substrates Strain engineering: global or local Ge or GeOI substrates
8 Strain Engineering Approaches Channel Strain Global Strain CESL Local Strain SiGe SRB sgoi ssoi Silicides Metal Gate Stress Liner STI Thin Thick SRB ssdoi S/D Recessed Uniaxial or Biaxial
9 Goal LOW FIELD MOBILITY CONTROL ESSENTIAL FOR HIGH PERFORMANCE DEVICES SUBSTRATE ENGINEERING: SOI, SiGe, Ge, GeOI,.. STRAIN ENGINEERING 65 nm CMOS platform available. DEFECT ENGINEERING IN THESE MATERIALS
10 Stress & Dislocation Nucleation Stress leads to the nucleation of dislocations when higher than the yield stress of the material stress relaxation of precipitates isolation induced stress interfacial stress due to lattice mismatch
11 Stress and Defects Electrical activity of the dislocations? Role of metallic impurities Stress can beneficially be used for gettering e.g. Fe getting by SiO 2 precipitates enhanced Cu precipitation due to strain relaxation Isolation-induced stress dislocations are the source of pipeline defects leading to an increase of the off-state leakage current
12 Stress-induced dislocations J.W. Sleigh, C. Lin and G.J. Grula, IEEE Electron Device Lett., 20, (1999) 248
13 Strained Si Device architecture: Strained Si Poly Strained Si channel Salicide Source Drain Relaxed Si 1-x Ge x buffer layer Relaxed SiGe
14 Strain S/D versus Channel
15 Strain and Spacer Overlap P.R. Chidambaram et al., Digest 2004 Symp. on VLSI Technology, (2004) 48
16 Dislocation Nucleation Misfit Dislocations (MDs) and Threading dislocations (TDs) may be generated in hetero-epitaxial systems. Lattice mismatch: elastical relaxation by increasing the strain plastically by dislocation generation Critical film thickness (Van der Merwe, JAP, 34, 117, 1963) t c = (1 2ν ) a 4π (1 ν ) 2 f 0 [ln 1 ν + 1] 2πf 0 ν dislocation velocity f 0 spacing mismatch Δa/a a =lattice spacing Strain relaxed buffer layers: gradual Ge increase : thick layer composition (2-4 mm) thin layer approach ( nm) Strain relaxation can be facilitated by a C-rich layer
17 Strained Si on SRB Layers Strained Si on SRB Dislocation density Graded channel approach (1-2 μm layers) Heat control in thick layers IMEC approach Thin ( nm) approach with C-doped layer for strain relaxation Can also be used in a SEG scheme (e.g. SEG for n-mos & SiGe S/D for p-mos)
18 Strain Relaxed Buffer Layers Thin SRB s Standard buffers
19 Epilayer Structure 8 nm Strained Si SiGe (20%), variable thickness 70 nm SiGe (22%) 5 nm SiGe:C (22%) 140 nm SiGe (22%) Threading dislocations <= 3x10 6 cm -2 C layer: defect-rich x x x x x x x x x x x x x x x x x x x Misfit dislocations Total layer thickness: nm After defect etching: Etch Pit Density <= cm -2
20 TEM Analysis
21 p + /n and n + /p Diode Structure implanted n-well or p-well Dopant activation: by spike annealing ( C) Ni silicidation Junction depth of ~50 nm
22 Chemical Defect Etching Misfit Dislocations At the Si/SRB interface Dislocation pile-ups Individual threading dislocations
23 EMMI Analysis n + p junction Si reference: Breakdown edges Thin SRB: MD bottom interface No electrical activity of threading dislocations revealed Thick SRB: Uniform distributed spots
24 EMMI Analysis p + n junction Si reference: Breakdown edges Thin SRB: distributed spots Electrical activity of threading dislocations and dislocation pile-ups revealed. Thick SRB: Distributed spots of TDs
25 Electrical Activity Defects - EBIC W. Seifert, M. Kittler, J. Vanhellemont, E. Simoen and C. Claeys, Inst. Phys. Conf. Ser., 149, 319, 1996)
26 EBIC Strained Si/ Si 0.8 Ge 0.2 H.C. Huang et al., Appl. Phys. Lett., 84, 3316, kev and 0.3 na a) 300 K and b) 65 K. 20 kev and 1 na a) 300 K and b) 65 K.
27 Diode Current Behavior G. Eneman et al., Proc. First CADRES Workshop, Catania 2004, J. Phys. C: Solid State Physics, vol 17, pp. S (2005) p+/n junctions Si ref SSi, thin SSi, thick I (A/cm 2 ) Si ref SSi, thin SSi, thick V (V) I (A/cm 2 ) n+/p junctions V (V)
28 Bulk Leakage Current Density versus TD Density Reverse Current Density (A/cm 2 ) V R =-1V n + /p junctions p + /n junctions n + p: 10 pa/td at V r =-1 V and 25ºC Different behavior p + n D c at 270 nm Different electrical activity? Threading Dislocation Density (cm -2 )
29 Activation Energy Arrhenius plot of n + -p diode current density for thin and thick SRB s, measured at a reverse voltage of 0.1V. Activation anneal was 1000 C. J (A/cm 2 ) ~ exp(-0.996x) ~ exp(-0.590x) V=0.1V reverse SSi-Thick (350 nm) Bandgap E act : diffusion SSi-Thin (250 nm) Near midgap E act : defects SSi, thin SSi. thick /kT (ev -1 )
30 Generation Lifetime versus TD Density τ -1 (s -1 ) Experimental τ -1 Linear Fit 1 = σ ν n τ g n t D N For n D 10 6 cm -1 σ n : cm 2 TD Threading Dislocation Density (cm -2 )
31 Generation Lifetime Effective generation lifetime at 0 V versus spike anneal temperature for p + -n junctions in a thick (350 nm) and a thin (250 nm) SRB 10-5 p + /n junctions at 0 V Si references Effective Generation Lifetime (s) thick SRB thin SRB Spike Anneal Temperature ( o C)
32 Discussion Higher thermal budget: Reduce leakage current Dopant diffusion: lower E Anneal defects SiGe with TDs Temperature increase: Wider W More TDs in depletion region J reverse ~ W n D N TD W: depletion width n D : number of traps per length dislocation N TD : threading dislocation density
33 Location C-rich Layer & Defect Density Impact of the position of the C-rich layer and the defect density on the reverse current density of n + -p diodes J R (A/cm 2 ) n+/p junctions C at 100nm C at 200nm C at 270nm Si ref (a) V R (V) J R (A/cm 2 ) ~10 9 defects ~10 7 defects ~10 5 defects Si ref (b) n+/p junctions V (V) R
34 Impact Type of Defect TDs increase the trap-assisted tunneling at RT, while above 100ºC the diffusion current dominates over the TD generation current. The C-rich layer defects introduce relaxation of the SiGe substrate. Moving the layer closer to the junction increase the generation current. Residual implantation damage makes the junction leakage current sensitive to the anneal temperature. For junction inside the SiGe layer this component is negligible compared to the leakage caused by other defects.
35 Low Frequency Noise E. Simoen et al., ULSI Process integration IV, Quebec, May 2005 Normalised noise spectral density (1/Hz) μmx5 μm n-mosfet TD no TD V =0.1 V DS thin SRB Drain Current (A) Input-referred Noise Spectral Density (V 2 /Hz) μmx1 μm n-mosfets V DS =0.1 V Si reference f=10 Hz SRB wafer Gate Voltage Overdrive (V)
36 Stress and Oxide Defects A. Stesmans et al., APL 82 (2003) 3038
37 Process Induced Stressors Tensile or compressive Geometry/design of devices has an impact Stress parallel or perpendicular to the current flow Uniaxial or biaxial Variety of stressors SiGe recessed source/drain Hybrid orientation techniques (HOT) Stress memorization effects (e.g. disposable stress liners) Contact etch stop layer (CESL)
38 Processing-Induced Stressors A. Collaert et al., IEEE TED, 20 (2005) 820 I off V gs =-0.3 V V ds =1 V -30% 20% reference tensile compressive I on V gs =0.7 V (a) I off V gs =0.2 V reference tensile compressive 10% V ds =-1 V I on V gs =-0.8 V (b) I on I off behavior of (a) nmos devices and (b) pmos devices; W = 35 nm; the strained layers obtained by SiN CESL have an intrinsic stress of 800 Mpa
39 LF Noise and Stressors G. Giusi, E. Simoen, G. Eneman, P. Verheyen, F. Crupi, K. De Meyer, C. Claeys and C. Ciofi, accepted for EDL, 2006 (in press) 10-8 A S ID / I 2 D ((µm)2 /Hz) 10-9 Reference #1 Reference #2 SiGe #1 SiGe #2 Cap #1 Cap #2 SiGe+Cap #1 SiGe+Cap #2 f = 10 Hz W = 10 µm L = 1 µm V 10 0 GS -V T (V)
40 Strain Engineering Critical factors [Ge] and the layer thickness Ge can outdiffuse during processing Thermal stability of the stress? Different behavior n- and p-channels Mobility enhancement is f(channel doping) Narrow width effects on strain behavior Defect generation Impact strain on noise performance STRAIN ENGINEERING HAS SUCCESSFULLY BEEN DEMONSTRATED BUT REMAINS COMPLEX
41 1947: 1 st transistor: J. Bardeen, W. Brattain,W. Shockley Ge Device
42 Defects in Ge Vanhellemont et al., in Defects and Diffusion in Semiconductors An Annual Retrospective VII, Trans. Tech. Publ. Inc., 230, 149 (2004) Defect in as-grown Ge (row of dislocations) * High-res. Ge, H-atm. crystal growth * 30, 60 and 90 disl. * Disl. sink for [V] Tilted 35 away [001] pulling axis No V 2 -H complexes
43 K.K. Bourdelle, APL, 86 (2005) Defects in GeOI {311} defect
44 Control n-type dopants in Ge Rs (Ohm/sq) kev P in Ge; no SiO 2 cap 0 1E+13 1E+14 1E+15 1E+16 Dose (at/cm 2 ) P, 500C-60s P, 500C-1s P, 600C-1s Above SS implant 15 kev 5x10 15 cm -2 P, 60 s at 50 C
45 Noise in GeOI Transistors Ge devices have a higher noise than their silicon counterparts, due to the quality of the interfacial layer.
46 GaAs on Si Fitzgerald et al., IEDM Techn. Digest, (2005) 519 TEM image of a GaAs on Si structure with a graded SiGe buffer to reduce the threading dislocations and a top Si cap
47 Conclusions Defect analysis requires a combination of state of the art characterization tools for defect detection and identification Strain engineering is a viable approach for sub 45 nm technology nodes Alternative substrates are strongly gaining interest and will know a real breakthrough Local strain engineering has a strong potential Defect engineering remains of crucial importance New physical models will be needed (e.g. LF noise)
48 Acknowledgement The author wants to acknowledge the discussions with and the use of co-authored results of the members of the IMEC highmobility and Ge teams. Special thanks to M. Bargallo, F. Crupi, M. Caymax, E. Delhougne, G. Giusi, R. Loo, R. Rooyackers, A. Satta, P. Srinivasan, J. Vanhellemont and P. Verheyen.
49
Processing and Defect Control in Advanced Ge Technologies
Processing and Defect Control in Advanced Ge Technologies C. Claeys* IMEC, Kapeldreef 75, 3001 Leuven, Belgium *Also E.E. Dept, KU Leuven, Kasteelpark Arenberg 10, 3001 Leuven, Belgium Outline Introduction/Motivation
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