Vaasa University. TehoFPGA 20th Nov 2013 Matti Tommiska, Altera

Transcription

1 Vaasa University TehoFPGA 20th Nov 2013 Matti Tommiska, Altera

2 Agenda Altera University Program Altera Industrial Market Solutions Industrial Networking Functional Safety HSR/PRP

3 Altera University Program Provides complete support for introducing students to digital technology Hardware Development and Education boards (DE0, DE1, DE2-115, and DE4) Software Quartus II Nios II soft processor Simulation tools Teaching materials Tutorials Laboratory exercises

4 Example DE board, DE de2-115/unv-de2-115-board.html Designed by professors, for professors Academic price $299

5 Altera and Industrial Solutions Industrial Networking C-based Design Entry Design Flow and Tools Model-based Design Entry SoC EDK, DS5 HDL Qsys HDL Functional Safety C (ARM) C (ARM) Development Kits Reference Designs 5

6 Commitment To Long Industrial Life Cycles Military, Industrial, Automotive, Computer, Medical Alignment to application lifecycle dynamics R&D 2 4 years Active 5 10 years Phase Out 1-3 years Obsolete t = 0 ASSP 5 years (typical) Low Prices, Consumer Driven MCU 7-10 years (typical) ASIC 10 years (typical) Low Prices, Embedded Driven Altera PLD 15+ years (typical) High NRE, 100% Application Specific Long life, Lower cost of ownership, Off-the-shelf, Wide MIC customer base Altera s PCN procedure meets or exceeds industry standards (JEDEC, ISO-9000, etc.) 6 6

7 Key Industrial Ethernet Implementation Trends Flexibility to support any one of multiple protocols Modules Discrete Device Integrated Function 7

8 Altera Industrial Ethernet Offering Simplified, no-hassle implementation for most of the popular Industrial Ethernet protocols + Profibus Hardware tested protocols HW IP & SW protocol stack NO upfront license fee Royalty embedded in the security CPLD Uniform software API and HW I/F Profinet RT Profinet IRT EtherCAT Ethernet POWERLINK Ethernet/IP (soft DLR) ModBus/TCP Profibus DP Ethernet/IP (hard DLR)

9 Functional Safety with Altera Value Proposition

10 Functional Safety Trends, Challenges Legislation forces the machinery market into certification Providing safety certified automation components is mandatory for industrial companies in EU/NA/JP (2012) Time to market Functional Safety development process increases TTM by months Development and material costs Functional Safety increases development & material costs significantly Machine builders will not pay a significant premium over long term Quality and project management required Productivity 24/7 operation - cost of maintenance down time (time to recovery) Functional Safety Assessors (TÜV, UL, Exida) Experience and uncertainty of cooperating with independent certification bodies 10

11 Functional Safety Value Proposition of Altera FPGAs Reduce Cost of Functional Safety Designs Fewer components, lower obsolescence risk Combine FS with application + Networking enables lower cost designs Reduces development time by as much as 2 years Safety Data Package lowers hurdles to start with FS designs Significantly reduces TÜV interaction and certification risks Reduce obsolescence risk by replacing ASICs/ASSPs and microcontrollers 11 11

12 Altera Deliverables for Functional Safety TÜV-Qualified Safety Data Package: Safety Manuals FPGA Device All devices fully supported by Quartus version below will be qualified for use based upon currently available FIT rates and SEU data Toolflow QuartusII v11.0 SP1 and QuartusII v9.0 SP2- TÜV qualified Standard IP Altera IP available in QuartusII will be qualified Include NIOSII and SOPC Builder Altera Safety Manuals will contain a TÜV qualification approval document Diagnostic IP Diagnostic IP blocks will be developed in accordance with IEC SIL3 CRC Check, SEU Check, Derived Clock Checker 12 12

13 Reduces Development Time Development Without TUV-Qualified Safety Package Safe Requirement Specification Qualification of Used Devices and Tools Implementation of Safe Functionality Development of Application-Specific Hardware and/or Software Implementation of Safe Diagnostic Functions Certification by TÜV Development with TUV-Qualified Safety Package Safe Requirement Specification Development of Application-Specific Hardware and/or Software Certification by TÜV 13 13

14 Altera s TÜV-Qualified Functional Safety Data Package Altera Functional Safety Value Altera tools and IP are sufficiently free of systematic errors The Altera Functional Safety Data Package saves months in certifying a safe application 14

15 Announcement February 25, Embedded World Altera announced a High-availability Seamless Redundancy (HSR) and Parallel Redundancy Protocol (PRP) reference design targeting smart grid substation automation equipment. The solution strives to improve system efficiency, reliability, economics, and sustainability to meet electric service needs The IEC compliant reference design includes Flexibilis Redundant Switch (FRS) IP implemented on a low-power, low-cost Cyclone class FPGA or Cyclone V SoC 15

16 FPGAs For PRP/HSR High-Availability Networks Flexibility Evolving with standards PRP/HSR with IEEE 1588 Add/change I/O interfaces Integration PRP/HSR GbE switch with monitoring/control functions Reliability with fewer components Performance Hardwired real-time detection PRP/HSR Gbps Ethernet switch traffic over microcontroller unit/dsp capabilities Total Cost of Ownership Example: Protection relay IED with PRP/HSR module Integration, device longevity to lower total cost Hassle-free business model No up-front non-recurring fees Reduce development risk Time to market 16

17 PRP/HSR Reference Design Security CPLD Scalable 3-8 port PRP/HSR Gigabit Ethernet switch Ethernet Layer 2 switch compatible with IEC PRP and HSR standards Compatible with IEEE 1588 PTP transparent clock From PRP/HSR on Cyclone IV or V Integrated SoC Target markets: Substation & utility automation, factory automation Flexibilis Redundant Switch (FRS) IP for mission-critical systems Support for Cyclone IV and V FPGAs, and Cyclone V SoCs Demo shows 4-port FRS on CIV, CV, and CV SoC platforms 17

18 Thank You