CIRCUIT performance variability continues to increase as

Transcription

1 Ths artcle has been accepted for ncluson n a future ssue of ths journal. Content s fnal as presented, wth the excepton of pagnaton. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1 Synthess and Analyss of Desgn-Dependent Rng Oscllator (DDRO) Performance Montors Tuc-Boon Chan, Student Member IEEE, Puneet Gupta, Member IEEE, Andrew B. Kahng, Fellow IEEE, and Langzhen La, Student Member IEEE Abstract Wth CMOS technology scalng, crcut performance has become more senstve to manufacturng and envronmental varatons. Hence, there s a need to measure or montor crcut performance durng manufacturng and at runtme. Snce each crcut may have dfferent senstvtes to process varatons, prevous wors have focused on the synthess of crcut performance montors that are specfc to a gven desgn. We develop a systematc approach for the synthess of multple desgndependent montors, as well as the correspondng calbraton and delay estmaton methods. Our approach syntheszes desgndependent rng oscllators (DDROs) usng standard-cell lbrary gates and conventonal physcal mplementaton flows. Our delay estmaton method lmts the memory usage overhead by clusterng crtcal paths wth smlar delay senstvtes. Expermental results show that our delay estmaton method usng multple DDROs reduces overestmaton (tmng margn) by up to 25% compared to usng a sngle montor. Furthermore, our slcon measurement results for montorng an ndustral mcroprocessor mplemented n a 45-nm slcon-on-nsulator process show that DDRO can reduce the mean delay estmaton error by 35% compared to nverter-based rng oscllators. Index Terms Adaptve voltage scalng, crcut performance montorng, clusterng, rng oscllators. I. INTRODUCTION CIRCUIT performance varablty contnues to ncrease as a result of process varablty, wde operatng ranges, and other factors. Performance varablty can often be compensated by accurate crcut performance estmaton and subsequent adaptaton. For example, crcut performance can be montored n the manufacturng flow for process tunng, or systems wth adaptve mechansms can optmze the tradeoff between energy and performance based on feedbac from runtme crcut performance montors [12]. In ths paper, we defne crcut performance montorng as a process that estmates the worst case delay of a crcut, based on measurements obtaned from on-chp montors. Prevous wors on VLSI crcut performance montorng can be classfed accordng to the taxonomy shown n Manuscrpt receved March 31, 2013; revsed August 9, 2013; accepted September 12, Ths wor was supported n part by SRC and n part by NSF Varablty Expedton under Grant CCF T.-B. Chan s wth the Department of Electrcal and Computer Engneerng, Unversty of Calforna at San Dego, La Jolla, CA USA (e-mal: tbchan@ucsd.edu). P. Gupta and L. La are wth the Electrcal Engneerng Department, Unversty of Calforna at Los Angeles, Los Angeles, CA USA (e-mal: puneet@ee.ucla.edu; langzhen@ucla.edu). A. B. Kahng s wth the Department of Computer Scence and Engneerng and Department of Electrcal and Computer Engneerng, Unversty of Calforna at San Dego, La Jolla, CA USA (e-mal: ab@ucsd.edu). Color versons of one or more of the fgures n ths paper are avalable onlne at Dgtal Object Identfer /TVLSI Fg IEEE Taxonomy of performance montorng methods. Fg. 1. Generc montors range from smple nverter-based rng oscllators (ROs) to more sophstcated process-senstve ROs (PSROs) [2], [17] and alternatve montorng structures such as phase-loced loops (PLLs) [13]. However, such generc montors are nadequate for capturng desgn characterstcs such as mx of devce types, whch dffer n responses to process varatons. As a result, delay estmaton usng generc montors s less accurate, whch leads to larger tmng margns. Desgn of montorng structures that are correlated to crcut performance (desgn-dependent montors) has been addressed n several ways. Lu and Sapatnear [16] propose a method to synthesze a sngle representatve crtcal path (RCP) for postslcon delay predcton. The RCP s desgned such that t s hghly correlated to all the crtcal paths for some expected process varatons. Ths approach uses only a sngle RCP to estmate the worst case delay of multple crtcal paths. Snce the crtcal paths may have dfferent senstvtes to process varatons, usng a sngle RCPs may be naccurate. The tunable replca crcut (TRC) method n [10] can synthesze dfferent delay paths to more flexbly mmc crcut performance, but has hgher desgn overhead compared to RO approaches. TRC also requres costly calbraton to obtan confguratons that correspond to dfferent operatng condtons. Alternatvely, Chan and Kahng [6] propose tunable ROs whch can be used as generc or desgn-dependent montors. To obtan more accurate (desgn-dependent) performance estmatons, the tunable ROs requre calbratons at sewed process corners. By couplng process parameters extracted from parametrc montors wth a desgn-specfc delay model, more accurate delay estmaton can be obtaned from generc test structures [4], [7], [19]. Such an approach s flexble because an arbtrary delay model can be used and calbrated post-manufacturng. Meanwhle, parametrc montors can

2 Ths artcle has been accepted for ncluson n a future ssue of ths journal. Content s fnal as presented, wth the excepton of pagnaton. 2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS be desgned such that they are hghly senstve to the targeted process varaton. However, ths approach requres a large amount of calbraton and resources for storage and computaton of parameters. Another class of desgn-dependent montors, called n stu montors [3], [11], [14], [18], [20], [23], [24], estmates crcut performance by measurng delays of the crtcal paths. However, use of an n stu montor for each crtcal path ncurs a hgh area overhead. To reduce the number of montors, La et al. [14] propose to selectvely measure the delays of nodes n a netlst to estmate crtcal path delays. Although n stu montors are accurate, they may ncrease desgn turnaround tme because embeddng n stu montors nterferes wth the tmng of actual crtcal paths. In ths paper, we propose a systematc methodology to synthesze multple desgn-dependent ROs (DDROs) for crcut performance montorng. A crucal and enablng observaton s that the crtcal path delay senstvtes form natural clusters (see Fg. 4). Therefore, we can capture the desgn-specfc delay senstvtes by syntheszng a montor to match the delay senstvtes of each cluster. Ths approach has a lower mplementaton overhead compared to tracng each crtcal path because the number of clusters s much smaller than the number of the crtcal paths. Our DDRO approach offers several potental benefts compared to prevous wors. 1) DDROs are more accurate compared to conventonal ROs because they are syntheszed to match the delay senstvtes of the crtcal paths. 2) DDROs are more accurate compared to a sngle RCP because multple DDROs are used to account for the dfferences between the crtcal paths. 3) DDROs are less ntrusve compared to n stu montorng methods. 4) The total number of ROs (slcon area) s greatly reduced because of the clusterng of crtcal paths. Only a few DDROs are requred to provde accurate delay estmaton. 5) DDROs can be used for early process tunng, postslcon tunng, and real-tme performance montorng. Swtchng the montorng purpose s smply a matter of redefnng target varaton sources (manufacturng or real-tme varatons) wth mnmal desgn modfcatons. Snce DDROs are replca-le montors, they can only replcate the mpact of global varaton on crtcal paths. Thus, our montorng approach s more sutable for long crtcal paths that pass through many gates. If wthn-de varaton domnates chp performance (e.g., chp performance s lmted by hold-tme crtcal paths and wthn-de varaton s large), an n stu montor s requred for accurate performance estmaton. Due to ths nherent lmtaton of replcale montors, we only consder setup-tme crtcal paths n ths paper. Our contrbutons can be summarzed as follows. 1) We propose a systematc methodology to desgn multple DDROs. Our expermental results show that the use of multple DDROs can reduce delay overestmaton by 15% to 25% compared to usng only one DDRO. TABLE I GLOSSARY OF TERMINOLOGY 2) We tape out a testchp and obtan slcon measurement results showng that DDRO can reduce the mean delay estmaton error by 35% compared to a generc nverterbased RO. 3) We propose a method to estmate chp delay and mnmze guardband margn by usng multple DDRO measurements. Our delay estmaton method has neglgble dfference compared to a path-based estmaton method, but the number of parameters used by our estmaton method s sgnfcantly reduced. 4) We propose a calbraton method to reduce delay estmaton error due to a sewed process, voltage, and temperature (PVT) corner.

3 Ths artcle has been accepted for ncluson n a future ssue of ths journal. Content s fnal as presented, wth the excepton of pagnaton. CHAN et al: SYNTHESIS AND ANALYSIS OF DDRO PERFORMANCE MONITORS 3 Fg. 2. Overvew of DDRO desgn methodology. The rest of ths paper s organzed as follows. Secton II gves an overvew of our methodology. We present two delay estmaton methods n Secton III. In Secton IV, we dscuss the mplementaton detals of DDRO synthess. In Secton V, we present expermental data to llustrate the use of DDROs to estmate crcut tmng. Fnally, we summarze our conclusons and future wor n Secton VI. All notatons used n ths paper are defned n Table I. II. OVERVIEW OF DDRO APPROACH An overvew of our montorng strategy s shown n Fg. 2. Frst, gven a netlst (de area for DDROs s preallocated), we extract the crtcal paths of a desgn by runnng statc tmng analyss (STA) usng both fast (FF) and slow (SS) corner lbrares. We consder a path to be crtcal f ts setup tmng slac dffers by 10% of the cloc perod from the mnmum (worst) tmng slac over all paths at the correspondng process corner. For example, when the desgn has a mnmum tmng slac of 10 ps and cloc perod of 1 ns, paths wth tmng slac less than 110 ps are consdered to be crtcal paths. We then characterze delay senstvtes of the crtcal paths to varaton sources usng HSPICE [30] wth a typcal corner process model. 1 Delay senstvty of the th crtcal path (v path ) s obtaned usng fnte dfferences [ ] v path d = path 1,..., dpath M dnom_path (1) d nom_path d nom_path d nom_path where d path m s the delay of the th crtcal path when the mth varaton source s based by one standard devaton from ts nomnal value, and d nom_path s the nomnal delay of the th crtcal path. Second, we cluster the crtcal paths based on ther path senstvtes, and synthesze one DDRO per cluster. We formulate DDRO synthess as an nteger programmng problem, n whch we see the set of gates (gate types and number of gates of each gate type) to be concatenated as a DDRO that matches cluster delay senstvtes. Snce the gate delays are senstve to the gate capactance and slew of adjacent gates, we use gate modules (.e., several dentcal gates connected n seres) as basc buldng blocs for DDRO (see 1 Improved crtcal-path selecton algorthms have been proposed n [25] and [26]. Study of alternatves for path selecton s beyond the scope of ths paper. Secton IV-C). To replcate the effect of nterconnect, each gate module has varants wth dfferent wrelengths (e.g., INVX1 wth 5 and 20 μm wrelengths). By matchng DDRO and cluster delay senstvtes, we ensure that the syntheszed DDROs have good correlaton wth the crtcal paths. Snce we use standard cells to synthesze the DDROs, the desgn and placement of DDROs can be easly ntegrated wth conventonal mplementaton flows. By measurng on-chp DDRO delays, we can estmate chp delay durng manufacturng or runtme. A crcut performance montor typcally feeds bac the estmated delay wth some margn to ensure chp functonal correctness. However, the margn should be mnmzed to avod sgnfcant performance penalty due to a pessmstc delay estmaton. Thus, our goal for crcut performance montorng s mnmze: μ(d est_max d max ) subject to: P(d est_max d max )>Z (2) where d max s the actual chp delay, whch s defned as the maxmum delay across all crtcal paths. Also, d est_max s the estmated chp delay; P(d est_max d max ) s the probablty that d est_max s larger than d max ;andμ(d est_max d max ) s the expectaton of delay overestmaton. We use Z to denote a user-specfed confdence. For smplcty, we call crtcal paths as paths n the remander of ths paper when there s no ambguty. III. DELAY ESTIMATION USING DDROS Gven a set of DDROs, dfferent chp performance estmaton methods lead to dfferent estmaton errors, runtme, memory requrements, etc. We frst analyze a path-based delay estmaton method based on a lnear model. Then, we propose a cluster-based estmaton method that acheves smlar accuracy but runs sgnfcantly faster and consumes less memory. A. Delay and Varaton Model We use the varaton model n [8], whereby lot-to-lot, wafer-to-wafer, and de-to-de process varatons are lumped and modeled as global chp varaton. The global varaton also ncludes de-to-de supply voltage and temperature fluctuatons. Wthn-de gate delay msmatches are modeled as random delay varatons. Spatal varaton s gnored n ths paper as t s small for most chps [8]. When the effect of spatal varaton s sgnfcant, DDROs can be dstrbuted wthn a de as n [21] to mprove correlatons between DDROs and the crtcal paths. We model the crtcal path delay (d path ) as a lnear functon of the varaton sources d path = d nom_path ( path 1 + v g + l path ) 1.. l path l path I = R F 1.. F I r(1, 1) r(i, 1) R =..... r(i, 1) r(i, Y ) (3)

4 Ths artcle has been accepted for ncluson n a future ssue of ths journal. Content s fnal as presented, wth the excepton of pagnaton. 4 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS TABLE II LIST OF VARIATION SOURCES For DDROs, we also use the delay model n (3). Snce each RO has many dentcal gates, uncorrelated local varaton s nsgnfcant due to averagng of uncorrelated delay devaton. Therefore, we do not model local varaton n the DDROs,.e., we use d ro = d nom_ro (1 + v ro g) (4) where d nom_ro s the nomnal delay of the DDRO (obtaned from smulaton) and v ro s a 1 M vector that represents the delay senstvty of the th DDRO to the vector g of all M global process varatons. Fg. 3. Ran correlaton between delays obtaned from HSPICE smulaton and the lnear model of (3). where g s an M 1 vector that represents the global varaton of M varaton sources. l path s local delay varaton of the th path. R s a I Y correlaton matrx that represents the correlaton between paths, where I s the total number of crtcal paths and Y s the total number of gate nstances n all I crtcal paths. F 1,...,F I are ndependent random varables, each of whch follows a standard normal dstrbuton. When the yth gate nstance s on the th path, the entry r(, y) n R s the standard devaton of the yth gate delay varaton due to wthn-de process varaton. If the yth gate nstance s not on the th path, the entry r(, y) s zero. Dfferent gate nstances wth the same gate type have the same standard devaton for ther gate delay varaton. 2 For example, all NAND2X1 gates have the same standard devaton. To verfy the accuracy of our delay model, we frst smulate a crtcal path usng HSPICE wth random global varatons whose sources are as lsted n Table II (100 trals). Then, we compare the smulated path delays wth the delays calculated usng the lnear model n (3). Fg. 3 shows that path delays obtaned from the lnear model correlate very well wth those from HSPICE smulaton. 2 The standard devaton of the gates are extracted from HSPICE smulatons wth a varaton model that s embedded n the foundry process desgn t for the 45-nm slcon-on-nsulator (SOI) process. B. Path-Based Delay Estmaton A straghtforward delay estmaton method s to extract global varaton usng multple process varaton-specfc montors and calculate chp delay based on the lnear model n (3). In other words, montorng methods n [4], [7], and [19] can be combned and extended for delay estmaton. However, we use ths approach only as a reference because t requres a large amount of memory to store parameters, as well as long computaton tme. Gven K DDROs, we can decompose the vector of delay senstvtes v path as a lnear combnaton of v ro ( = 1,...,K ) to utlze measurements from the DDROs K v path = b v ro + vres_path (5) =1 where b s a constant coeffcent and v res_path s a 1 M vector that represents the resdue of the delay-senstvty decomposton. 3 The values of b are obtaned by solvng a lnear program (see Secton IV-D). Substtutng v path n (3) as a lnear combnaton of v ro, we obtan measurable uncertanty d path = d nom_path K {}}{ 1 + (b v ro g) + {}}{ u where u = l path =1 + v res_path g. (6) Equaton (6) shows that d path conssts of a measurable term and an uncertanty term. Whle the value of the measurable term can be determned from the delays of DDROs, the value of the uncertanty term cannot be measured drectly. To estmate the maxmum chp delay wth the uncertanty u, we calculate the dstrbuton of the chp maxmum frequency, d max, by usng the method n [22]. Then, we can express d max as a normal dstrbuton usng a mean μ(d max ) and a standard devaton σ(d max ).Gvenμ(d max ) and σ(d max ), d est_max can be readly obtaned usng the erf functon for Gaussan dstrbuton ( d est_max μ(d max ) ) erf σ(d max > Z. (7) ) 3 Snce there wll be no resdue when K = M, t s preferred to have K < M. In ths paper, we try K ={1, 3, 5, 7, 12} and show that K = 5 s suffcent for our test cases wth 12 varaton sources (M = 12).

5 Ths artcle has been accepted for ncluson n a future ssue of ths journal. Content s fnal as presented, wth the excepton of pagnaton. CHAN et al: SYNTHESIS AND ANALYSIS OF DDRO PERFORMANCE MONITORS 5 Fg. 4. Every dot n the fgure represents a crtcal path s delay devaton for one standard devaton n nmos threshold voltage (Vthn) and pmos threshold voltage (Vthp). The crtcal paths are extracted from a benchmar crcut AES mplemented usng a foundry 45-nm SOI technology and smulated usng HSPICE. We cluster the paths nto three clusters (accordng to all 12 varaton sources) and ndcate the three-way clusterng by dfferent colors. C. Clusterng The next step s to mnmze delay margn and fnd v ro. Equatons (6) and (7) show that the value of d est_max s manly determned by the v res_path. A larger v res_path wll ncrease the magntude of σ(d path ), whch leads to a larger d est_max. Therefore, t s desrable to select a set of v ro that mnmzes v res_path.wefndv ro by clusterng crtcal paths wth smlar v path senstvty vectors, and then assgnng the centrod of the th cluster as v ro. To cluster the paths, we use the means++ algorthm [1] and choose the best clusterng soluton among 100 random starts. The objectve functon of the clusterng s defned as I { path mnmze P(d > cloc perod) =1 v path v ro }, path cluster. (8) Snce the maxmum chp delay s usually determned by the slowest path, we mpose a hgher penalty for havng msmatched delay senstvtes on a path wth hgher probablty of tmng falure,.e., P(d path > cloc perod). For each path, the probablty of tmng falure s calculated based on the delay model n (3) and the dstrbutons of varaton sources, g. Mnmzng the cost functon n (8) helps to reduce the upper bound of v res_path v path v ro because the upper bound s defned by. An example clusterng result s shown n Fg. 4. D. Cluster-Based Delay Estmaton The path-based delay estmaton method requres O(IY) parameters for runtme delay estmaton. To reduce the number of parameters, we represent path delays n a cluster by the delay of the cluster (dx clust ). We calculate the maxmum delay of paths n each cluster usng the method n [22] and the path delay model (3). The outcome of ths step gves us the expected maxmum delay of cluster x. But more mportantly, t also extracts the senstvtes of the maxmum delay to varaton sources (v max x ). Smlar to the path-based approach, we represent v max x as a functon of v ro K v max x = =1 {a x v ro }+vres_clust x (9) where a x s a constant coeffcent, and v res_clust x s the resdue of the delay senstvty decomposton. Note that when v ro s equal to v max x, v res_clust x = 0. However, the syntheszed v ro are usually slghtly dfferent from v max x. Thus, havng a x s useful to reduce v res_clust x. The approxmate delay of the x th cluster s gven by ( K ) dx clust = dx nom_clust 1 + {a x v ro g}+vres_clust x g + r x =1 (10) where dx clust denotes the delay of the xth cluster, dx nom_clust represents the nomnal delay of the xth cluster, and r x represents the random local delay of the xth cluster. After measurng DDROs, we can obtan the mean and standard devaton of dx clust as n (11) σ(d clust x ) = μ(dx clust ) = dx nom_clust { ( ) } 1 2 σ v res_clust x g + σ(rx ) 2 2 ( 1 + K =1 a x v ro g ). (11) Then, we can calculate the maxmum delay dstrbuton of a chp, d max, usng the method n [22] and fnd the value of d est_max usng (7). Although X and K need not be the same, we let X = K (exactly one DDRO per cluster) for experments n ths paper. Usng ths cluster-based approxmaton method consumes less memory compared to the path-based method because the total number of parameters s reduced from O(IY) to O(K 2 ),wherek I Y. Moreover, the number of operatons to calculate the maxmum of two delay dstrbutons s reduced from O(I) to O(K ). Ths reduces maxmum-delay calculaton tme from 1 mn (wth the path-based method) to less than 1 s (wth the cluster-based method). 4 The clusterbased (fast) delay estmaton method enables the use of DDROs for real-tme performance montorng, whch requres montors to feed bac chp performance varaton (due to temperature or voltage varaton) as soon as possble so that the chp can adapt to the changes accordngly. When DDROs are used for post-slcon tunng, the cluster-based delay estmaton method can reduce calbraton tme. IV. SYNTHESIS OF DDROS Gven a delay senstvty target (v ro ), we want to construct a DDRO, so that the delay senstvtes of the DDRO match the targeted delay senstvtes. Ths DDRO synthess problem s dffcult because there can be many combnatons of gates to construct a RO. Here, we descrbe an nteger lnear programmng (ILP) formulaton to solve the DDRO synthess problem. Further, we descrbe varous aspects whch must be consdered durng DDRO synthess. 4 In our experment, calculatng the maxmum delay dstrbuton of several hundreds of paths wth a 3-GHz sngle-core CPU taes up to 1 mn of CPU tme.

6 Ths artcle has been accepted for ncluson n a future ssue of ths journal. Content s fnal as presented, wth the excepton of pagnaton. 6 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS A. ILP Formulaton Snce each gate module type s nstantated a dscrete number of tmes, we formulate DDRO synthess as an ILP problem H { } mn.: d nom_gate h S h v ro s.t.: H h=1 h=1 H h=1 { d nom_gate h } S h v gate h (12) d nom_gate h S h mnmum DDRO delay H h=1 S h maxmum gate count where d nom_gate h s the nomnal delay of canddate gate module type h, ands h s the nteger varable that ndcates the number of copes of gate module type h n the DDRO. H s the total number of gate module types. After solvng the ILP, S h copes of gate module type h are used n the DDRO. If S h s zero, gate module type h s not used n the DDRO. In our experments, solvng the ILP wth the publc-doman solver [15] taes 1 h on a 3-GHz sngle-core CPU. Instead of mnmzng the dfference n relatve delay senstvty, the formulaton n (12) mnmzes the absolute delay senstvty dfference so that the objectve functon s lnear n S h.ths favors a soluton wth a smaller DDRO nomnal delay, whch may be suboptmal n term of normalzed delay senstvty dfference. To compensate ths nherent bas n the ILP, we add a constrant to defne the mnmum DDRO delay. We then sweep the value of mnmum DDRO delay at 10 evenly spaced ntervals along ts feasble range. B. Selectng Major Varaton Sources To dentfy the major varaton sources that affect delay senstvty, we smulate a seven-stage RO usng the foundrysuppled 45-nm SOI SPICE model. The SPICE model has 13 process-related parameters for process varaton analyss. In our experment, we perturb all of these 13 parameters (one at a tme), as well as the supply voltage and temperature. Based on the results n Fg. 5, we can see that most of the varaton sources have notceable effect on the delay except for C gdl, C gsl,andc jswg. Therefore, we only consder 12 out of the 15 major varaton sources; these are summarzed n Table II. We do not nclude second-order senstvtes to the varaton sources because ther magntudes are very small. Ths assumpton s supported by the data n Fg. 3. In our expermental setup, the mpact of nterconnect s modeled by parastc resstance and capactance extracted from desgn layout. However, we do not model nterconnect as a varaton source because ts mpact s relatvely small compared to that of actve devces [5]. If nterconnect varatons are to be ncluded, the DDRO must be bult wth components that are senstve to nterconnect varatons. Fg. 5. Delay senstvtes of an RO to dfferent varaton sources show that most of the sources have notceable effect except for C gdl, C gsl,andc jswg. Delays (y-axs) are normalzed wth respect to the nomnal delay of the RO wth no varaton. C. Characterzng Gate Senstvtes Our ILP formulaton n (12) assumes that delay senstvty of a gate (standard cell) s not senstve to other gates connected before and after t. Ths s a ey assumpton that smplfes the problem. If we model v gate h as a functon of ts adjacent gate type, the total number of varables and the desgn space become ntractable. To decouple the load and slew nteracton between the gates, we ntroduce gate modules as basc buldng blocs for DDRO. A gate module s defned as several dentcal gates connected n seres, as llustrated n Fg. 6. Smulaton results n Fg. 7 show that the senstvty dfference due to dfferent nput slew and output load s reduced from 0.15% to 0.03% as the number of stages n a gate module ncreases from 1 to 15. In ths paper, we use fve-stage gate modules as a tradeoff between stablty of senstvty and total area of a gate module. For a gate wth multple nput pns, gate delays through dfferent nput pns wll have dfferent delay senstvtes. Thus, each gate module type s defned wth respect to a specfc nput pn. For example, gate module types NAND2X1_A and NAND2X1_B use the same gate type (NANDX1) but the gate modules toggle dfferent nput pns (A versus B). Extra nput pns of a multnput gate are assgned to hgh or low to mae a gate module nvertng or bufferng (see Fg. 6). To obtan a lst of canddate gate module types for DDRO synthess, we use logc standard cells (e.g., AND, OR, OXR, INV gates) to buld gate modules. For multnput gates, we generate a gate module type for each nput pn. Snce there are many gate module types, we select those that have smlar gate capactance. Ths s because gate modules wth smlar gate capactance have less mpact on the delay senstvtes of adjacent gate modules when they are concatenated to form a DDRO. Snce the nterconnect also affects path delay senstvty, we use dfferent wrelengths n buldng our gate modules. Gate modules wth dfferent wrelengths are consdered as dfferent nstance types even f they have the same gate type. Note that the gate module wrelengths need to be defned based on both the technology and the crtcal paths that are to be montored. In our experment, the wrelengths of crtcal paths are typcally less than 20 μm (see Fg. 8). Thus, we use two types of nterconnect lengths n our gate modules,.e., the wrelength between consecutve gates n a module can be

7 Ths artcle has been accepted for ncluson n a future ssue of ths journal. Content s fnal as presented, wth the excepton of pagnaton. CHAN et al: SYNTHESIS AND ANALYSIS OF DDRO PERFORMANCE MONITORS 7 Fg. 6. Illustraton of a gate module n a DDRO. Fg. 9. Custom nterconnect cell wth a snang route to reduce total area of long nterconnect. Fg. 7. Smulaton results showng that the senstvtes under dfferent nput slew {5 ps, 50 ps} and output load {FO1, FO5} combnatons converge as the number of stages n a gate module ncreases. Fg. 8. Wrelength dstrbuton of each net on crtcal paths. The crtcal paths are extracted from an ARM M3 processor mplemented n 45-nm SOI process. ether short (5 μm) or long (20 μm). As depcted n Fg. 9, we create custom nterconnect cells wth snang routes to match the desred nterconnect wrelengths as well as reduce the total area of DDROs. Durng physcal mplementaton, we synthesze each DDRO usng gate modules whch consst of standard cells and custom nterconnect cells. The gates modules n each DDRO are placed n two rows to form a loop. The standard cells and the custom nterconnect cells n each gate module are placed n seres. D. Extracton of b and a x As mentoned n Secton III, we represent v path and v max x as lnear combnatons of v ro,usngb and a x, respectvely. The b (resp. a x ) extracton s acheved by solvng (5) [resp. (9)] usng smple least-squares fttng to mnmze the resultng resdue v res_path (resp. v res_clust x ). However, the smple fttng approach can lead to overfttng when K M, whch results n large b (resp. a x ) values and ncreases delay estmaton error. For example, Fg. 10 (left) shows that solvng (5) usng a lnear least-squares method wthout constrants on b leads to Fg. 10. Estmaton error of a test case (MIPS) wth dfferent setups. (a) Lnear model results (left) versus HSPICE results (rght) usng lnear least-squares method on b for the MIPS test case. Lnear least-squares method wors for lnear model but becomes unstable wth SPICE results. (b) Lnear model results (left) versus HSPICE results (rght) usng our method for the MIPS test case wth λ = Wth our method, the results are consstent for both lnear model and HSPICE results. (c) HSPICE model results wth (left) λ = 0.01 and (rght) λ = 0.1. Our method s robust and nsenstve to the value of λ. lttle delay overestmaton when we consder global varaton only. However, Fg. 10 (rght) shows that ths s not true when we repeat the experment wth global and local varatons, as well as other varatons that are absent n our delay model. Ths s because the large b (resp. a x ) values magnfy delay nose,.e., the dfferences between the actual delays and the delays calculated usng the lnear delay model n (3). The delay nose s manly due to the fact that crtcal path and DDRO delays have nonlnear dependence on the parameters n Table II, when subjected to PVT varatons. To reduce the mpact of large b (resp. a x ) values, [27] formulates the extracton problem as a lnear program wth upper and lower bounds on b (resp. a x ). Although the

8 Ths artcle has been accepted for ncluson n a future ssue of ths journal. Content s fnal as presented, wth the excepton of pagnaton. 8 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS method of [27] avods large estmaton error, the upper and lower bounds are determned by tral and error to mnmze delay estmaton error. In ths paper, we consder both RO delay senstvty decomposton resdue and delay nose as errors and formulate the b (resp. a x ) extracton problem as a lnear program mn.: g +[b 1...b K ] v res_path e 1. e K (13) where e s a random varable that represents the delay nose of DDRO ntroduced by the lnear delay approxmaton n (4). Note that the e also ncludes hgher order delay senstvtes, any unmodeled varaton, as well as the local varaton n DDRO due to process varatons. The value of e can be estmated by calculatng the dfference of the delay obtaned from HSPICE Monte Carlo smulaton and that from (4). Alternatvely, we can defne λ as the rato between g and e and smplfy the lnear program (13) as b 1 mn.: 2 + λ v res_path. b K. (14) 2 Based on our emprcal results, we set λ = 0.02 n ths paper. Results n Fg. 10 show that, by usng a x extracted by solvng (14), the delay estmatons are not senstve to delay nose caused by crcut nonlnearty and other varatons. Moreover, Fg. 10 shows that the delay estmaton errors are not senstve to λ. Thus, the formulaton n (14) s more robust than that n [27]. E. Synthess Results Fg. 11 shows examples of syntheszed DDROs for test case M0 wth K = 3. As shown n the fgure, the syntheszed DDROs have three sets of lnearly ndependent delay senstvtes. Ths s an mportant property because we wll use lnear combnatons of the delay senstvtes to match the delay senstvtes of crtcal paths or path clusters (DDROs wth lnearly dependent delay senstvtes are redundant). Fg. 12 shows that, by usng lnear combnatons of delay senstvtes of DDROs (.e., a x v ro ), we can acheve smaller delay senstvty errors wth respect to a crtcal path compared to usng DDROs drectly or smple nverter-based ROs. The standard cells n the DDROs are descrbed n Table III. F. Delay Estmaton Wth Sewed PVT Corner The estmaton methods n Sectons III-B and III-D assume that the nomnal RO delays (d nom_ro ) are obtaned from HSPICE smulaton at the nomnal PVT corner,.e., the measurable term n (6) s defned as v ro g j = dmeas_ro j d nom_ro 1 (15) where d meas_ro j s the delay of the th DDRO measured from the jth chp and g j s the global process varaton Fg. 11. Delay senstvtes of synthesze DDROs of test case M0. Cluster number = 3. The delay senstvtes (y-axs) s normalzed to DDRO delay wth no varaton. Fg. 12. Delay senstvty errors of dfferent ROs wth respect to the delay senstvtes of a crtcal path n test case M0. By usng lnear combnaton of DDROs, the total delay senstvty error s reduced compared to smple nverter ROs or DDROs wthout applyng lnear combnaton. of the jth chp. If the actual operatng PVT corner of the chps s sgnfcantly sewed compared to the nomnal corner, d nom_path and d nom_ro obtaned from HSPICE smulaton wll be naccurate. Ths s especally mportant for low-volume producton runs. Therefore, we propose a method to calbrate d nom_path and d nom_ro when chp samples are avalable. Gven a set of chp samples, we can obtan the mean RO delay across all samples (μ(d meas_ro )). By replacng the d nom_ro n (15) wth μ(d meas_ro ), we compensate for the error caused by a sewed process and/or msmatch between HSPICE model and slcon data v ro g j = dmeas_ro j 1. (16) μ(d meas_ro ) After applyng the calbraton n (16), we can estmate the delay of the jth chp (d est_max j ) usng (11). Smlarly, the chp delay s also susceptble to the sewed process as well as msmatch between HSPICE model and slcon data. Moreover, chp delay can be sewed dfferently wth respect to the DDRO. To mnmze delay estmaton error resultng from the systematc msmatch between chp and DDRO delays, we propose to apply an addtonal calbraton procedure durng chp delay estmaton. Frst, we obtan the expectaton of

9 Ths artcle has been accepted for ncluson n a future ssue of ths journal. Content s fnal as presented, wth the excepton of pagnaton. CHAN et al: SYNTHESIS AND ANALYSIS OF DDRO PERFORMANCE MONITORS 9 TABLE III STANDARD CELLS IN DDROs TABLE IV PHYSICAL IMPLEMENTATION RESULTS OF BENCHMARK CIRCUITS actual chp delay (μ(d max )) by calculatng the average of sample chp delays. Second, we calculate the expectaton of chp delay estmaton (μ(d est_max )) by averagng chp delay estmatons (d est_max j ) across all chp samples. In other words, (μ(d est_max )) s defned as the average of the expectaton of estmated chp delay μ(d est_max ) = 1 total samples j ( d est_max j Z=50% ). (17) The calbrated maxmum-delay estmate for chp j (d cal_max j ) s gven by d cal_max j = μ(dmax ) μ(d est_max ) dest_max j. (18) V. EXPERIMENTAL RESULTS To valdate our performance montorng methodology, we syntheszed, placed, and routed three benchmar crcuts usng a commercal 45-nm SOI technology. Detals of the mplemented benchmar desgns are lsted n Table IV. The benchmar crcuts are obtaned from ARM [32] and Opencores [34]. Then, we follow the DDRO desgn flow n Fg. 2. We frst run STA usng both FF and SS corner lbrares. As mentoned n Secton II, we consder a path to be crtcal f ts setup tmng slac at ether FF or SS corner dffers from the worst tmng slac at the correspondng process corner by no more than 10% of the cloc perod. We extract delay senstvty of each crtcal path to each of the varaton sources n Table II usng HSPICE wth a typcal process corner model. Note that HSPICE-based senstvty characterzaton s not mandatory n our desgn flow, and that t can be replaced by other methods (e.g., the statstcal method n [24]). To evaluate the qualty of our DDRO synthess and delay estmaton methodologes, we run Monte Carlo experments wth global and local varatons on the crtcal paths and DDROs. For HSPICE smulaton, we use the bult-n Monte Carlo setup n the 45-nm commercal devce model. Snce each crtcal path s defned for a specfc nput and smulated ndependently, we cannot capture the correlaton of local varaton due to gate sharng. As an alternatve, we run another set of Monte Carlo experments usng the lnear model n (3). In both smulatons, we use the path and DDRO delay senstvtes extracted from HSPICE smulaton results to mnmze the dscrepancy between them. In the lnear model experment, we sample the values of varaton sources by usng the Gaussan random number generator n MATLAB [29]. The number of trals n the Monte Carlo experment s 1000 and 100 for the lnear model and for HSPICE smulaton, respectvely. Unless otherwse specfed, we set the user-specfed confdence Z = 99%. 5 A. Smulaton Results Experments usng lnear model. The smulaton results n Fgs. 13 and 14 show that our approxmate delay estmaton method acheves smlar results compared to the path-based method. 6 The results also show that mean delay overestmaton of all benchmar crcuts decreases notceably as the number of clusters ncreases from 1 to Ths confrms our hypothess that havng multple DDROs that correlate well wth the crtcal paths can reduce chp delay overestmaton. The results also show that delay overestmaton s nonzero even when the number of DDROs = 12 (.e., K = M = 12). Ths s because v res_path and v clust x are nonzero. We further observe that the beneft of usng multple DDROs s more sgnfcant when the local varaton s relatvely less compared to the global varaton. Ths s because replcale montors (e.g., PSRO, DDRO, PLL) can only replcate the mpact of global varaton on the crtcal paths. If local varaton domnates, more ntrusve montorng s requred to measure the mpact of local varaton. Based on the smulaton results wth global and local varatons (Fg. 14), mnmum delay overestmaton values for 5 When number of trals s small, our delay estmaton s more senstve to the nstances of the trals, especally for a hgh confdence Z = 99%. 6 The results n ths paper are slghtly dfferent from those n [27] because we fxed an error n characterzaton of DDRO delay senstvtes n [27]. 7 When the number of clusters (K ) = 1, our DDRO method s smlar to the representatve crtcal path replca method [16].

10 Ths artcle has been accepted for ncluson n a future ssue of ths journal. Content s fnal as presented, wth the excepton of pagnaton. 10 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS Fg. 13. Lnear model smulaton results wth global varatons only. (a) AES. (b) M0. (c) MIPS. Fg. 14. Lnear model smulaton results wth global and local varatons. (a) AES. (b) M0. (c) MIPS. Fg. 15. HSPICE results for global and local varatons. (a) AES. (b) M0. (c) MIPS. the AES, M0, and MIPS test cases are 2.5%, 2.7%, and 3.4%, respectvely. The results for K = 12 n Fgs. 13 and 14 show that the achevable mnmum delay overestmaton s lmted by the local varaton of a desgn. Therefore our performance montorng method may be more suted for low-speed desgns wth longer crtcal paths that are less susceptble to local delay varatons. HSPICE smulatons. HSPICE results n Fg. 15 are smlar to the lnear model results. Dscrepances between HSPICE and lnear model results are manly due to the fact that our delay estmaton does not account for nonlnearty n crcut delay. Despte a user-specfed confdence of 99%, the results n Table V show that we underestmate the delays of 1.96% and 5.9% nstances n the lnear model and HSPICE experments, respectvely (average across three benchmars for cluster-based estmaton). Snce the results of the lnear model experment are free from nonlnearty error, the underestmaton error s manly due to the approxmaton n the statstcal maxmum functon gven by [22]. The HSPICE results have more underestmated nstances because local varaton s not modeled correctly,.e., HSPICE smulates the crtcal paths wth uncorrelated local random varaton but our delay estmaton accounts for correlaton between local varatons. As a result, our delay estmates are slghtly smaller than the path delays obtaned from HSPICE smulaton. B. Delay Estmaton Wth Calbraton We set up two experments to evaluate our calbraton method n Secton IV-F. Frst, we shft both chp and DDROs supply voltages from nomnal supply voltage (0.9 V) to 0.8 V. Ths experment setup represents the typcal scenaro where

11 Ths artcle has been accepted for ncluson n a future ssue of ths journal. Content s fnal as presented, wth the excepton of pagnaton. CHAN et al: SYNTHESIS AND ANALYSIS OF DDRO PERFORMANCE MONITORS 11 TABLE V AVERAGE UNDERESTIMATED INSTANCES ACROSS K ={1, 3, 5, 7, 12} TABLE VI AVERAGE OF MEAN DELAY ESTIMATION ERROR NORMALIZED TO MEAN CHIP DELAY MIPS WITH 100 HSPICE MONTE CARLO TRIALS Fg. 16. dvder. RO bloc schematc. In ths test chp, we use a 12-stage frequency TABLE VII DESIGN INFORMATION OF THE TEST CHIP the nomnal PVT corner s shfted. Second, we eep the chp supply voltage at 0.9 V but shft all DDROs voltages to {0.8, 0.9, and 1.0 V}. Ths experment setup represents the scenaro when there s systematc wthn-de varaton between the chp s crtcal paths and DDROs (e.g., voltage drop n chp s power delvery networ). For each test case, we smulate the crtcal paths (obtaned from MIPS) and DDRO delays usng HSPICE Monte Carlo wth 100 trals. Based on the smulaton results, we estmate chp delay usng the cluster-based method n Secton III-D wth fve DDROs (Z = 50%) and compare t wth the smulated chp delay. Among the 100 trals, we randomly choose a subset of the chp samples and apply the calbraton procedure descrbed n Secton IV-F. Snce the delay estmaton s affected by the selecton of chp samples, we repeat ths experment 50 tmes and report the average values of mean delay estmaton error. Results n Table VI show that, when both chp and DDROs voltages are at the nomnal corner (0.9 V), the mean delay estmaton error s only 1.25% wthout applyng any calbraton. Even when both chp and DDRO voltages are shfted to 0.8 V, the estmaton error s only 1.70%. However, f chp voltage remans at 0.9 V but DDROs voltage s shfted to 0.8 or 1.0 V, the estmaton error ncreases sgnfcantly (12% to 21%). The estmaton error can be reduced sgnfcantly when we apply our calbraton method (Secton IV-F). As the number of samples ncreases, the average mean delay estmaton error reduces rapdly. For nstance, the maxmum of the average mean delay estmaton error s less than 2.5% wth 30 samples. C. Proof-of-Concept Slcon Results We have taped out a test chp wth DDRO-based performance montorng usng a 45-nm IBM SOI technology wth dual-v th lbrares. The test chp has an ARM Cortex- M3 mcroprocessor [33] wth DDROs. To synthesze the DDROs, we extract the crtcal paths from the mcroprocessor and cluster ther senstvtes nto fve clusters by usng the means++ algorthm. The results of the path senstvtes clusterng s shown n Fg Then, for each cluster, we synthesze a DDRO whch has delay senstvtes smlar to the mean delay senstvtes of paths n the cluster. The synthess method s the same as that n Secton IV. To control DDRO oscllaton, a NAND (or AND) gates added n each RO as shown n the schematc n Fg. 16. An on-chp dgtal counter s used to obtan the RO frequences,.e., the counter wll count the number of cycles of a RO wthn a measurement wndow. We repeat RO measurements wth 40- and 100-ms measurement wndows and measure the ROs n dfferent sequences to mae sure that the results are consstent and systematc measurement error s mnmzed. For comparson, we also mplemented nverter-based ROs. The desgn nformaton of the Cortex-M3 and ROs are lsted n Table VII. The RO cell count ncludes the addtonal NAND (or AND) gate and a 12-stage frequency dvder (total 13 cells). The test chp layout and de photo are shown n Fg. 17. We measured the processor maxmum operatng frequency and RO frequency usng the test bed shown n Fg. 18. There are two mcrocontroller unts (MCUs) on the test bed. One of the MCUs s used to control the dgtal counter of the RO bloc and to measure the frequency of the ROs. The other MCU s used to control the processor and the on-chp PLL. We measure chp frequency by runnng a test 8 At the tme of our test chp tapeout, the clusterng method of (8) had not yet been developed.

12 Ths artcle has been accepted for ncluson n a future ssue of ths journal. Content s fnal as presented, wth the excepton of pagnaton. 12 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS Fg. 17. Test chp de photo and layout llustraton. Fg. 18. Test bed for RO frequency measurement and processor frequency measurement. Two mcrocontroller unts are desgned to control the processor and RO blocs, respectvely. program (fast Fourer transform) and ncreasng the processor s cloc frequency (through PLL) untl the processor generates ncorrect results compared to the precalculated golden results. For each chp, we supply both RO and processor wth the same supply voltage. The measured mean chp and RO delays (14 test chps) are about 2 tmes the correspondng smulaton results. Ths suggests that the chps are operatng at a very sewed PVT corner compared to the HSPICE smulaton. Therefore, we use the calbraton method descrbed n Secton IV-F to estmate chp delays. To mnmze the estmaton error, we use all 14 chps for the calbraton. For each nverter-based RO, we treat t as one DDRO desgned for the all crtcal paths,.e., x = = 1. Then we apply the same calbraton as n Secton IV-F and estmaton method as n Secton III-D for the nverter-based ROs (wth a x = 1). The results of the mean delay estmaton error are shown n Fg. 19 (Z = 0.5). The measurement results show that, by usng fve DDROs, we can reduce the mean delay estmaton error by 35% (from 2.3% to 1.5%) compared to generc nverter-based ROs. To ensure that our results are not senstve to measurement errors, we repeat the analyss by njectng random nose (standard normal dstrbuton wth σ = 1%, 3%, and 5% wth respect to RO frequency) nto all RO measurements. Results n Table VIII show the average mean delay estmaton error of DDRO and nverterbased ROs across 30 random trals. The mprovement of DDRO over nverter-based ROs s approxmately 25% 30%, whch s consstent wth our observaton drawn from Fg. 19. We also deploy ROs wth dfferent numbers of stages to estmate the effect of local varaton. The results n Fg. 19 show that the errors of 61-stage nverter ROs are smlar to those of ther 21-stage counterparts. Ths suggests that random local varaton n ROs has lttle mpact on the estmaton error n our experment. In Fg. 20, we plot the statstcs of the delay estmatons. The results show that the mnmum and maxmum delay estmaton errors usng DDROs are smaller to those of nverter-based ROs. Note that our results are based on measurements on 14 test chps from a sngle wafer. Fg. 19. Mean delay estmaton error obtaned from DDROs and nverterbased ROs. Estmaton errors are calculated by tang the absolute dfference between normalzed estmaton and normalzed chp delay. TABLE VIII MEASUREMENT ERROR SENSITIVITY ANALYSIS Fg. 20. Maxmum and mnmum delay overestmaton obtaned from DDROs and nverter-based ROs. The edges of the boxes are the correspondng 25th and 75th percentles of the data. Wth multple wafers from dfferent lots, we expect that the mprovements may be dfferent (mprovement s lely to be hgher snce the magntude of global varaton wll ncrease compared to local varaton). D. Comparson Wth Other Montorng Methods Table IX summarzes the dfferences among dfferent replca-le desgn-dependent montorng methods. The method proposed n [16] has small mplementaton overheads

13 Ths artcle has been accepted for ncluson n a future ssue of ths journal. Content s fnal as presented, wth the excepton of pagnaton. CHAN et al: SYNTHESIS AND ANALYSIS OF DDRO PERFORMANCE MONITORS 13 TABLE IX COMPARISON OF DIFFERENT REPLICA-LIKE DESIGN-DEPENDENT MONITORING METHODS To verfy the performance of DDROs and our delay estmaton approach, we taped out a test chp usng 45-nm SOI technology together wth an ARM CORTEX M3 CPU. Our slcon results have shown that DDRO can reduce the mean delay estmaton error by 35% (from 2.3% to 1.5%) compared to generc nverter-based ROs. because t uses a sngle representatve crtcal path to estmate chp delay. Although ths method does not requre any calbraton, t s relatvely less accurate because t reles on a sngle representatve crtcal path to estmate a set of crtcal paths. 9 The method of [6] also has small mplementaton overheads because t requres only a set of smple ROs. However, onetme calbratons at sewed process corners are requred to mae the ROs to be desgn-specfc. Even wth calbraton, the method n [6] s not necessarly accurate because t calbrates the confguratons of ROs to guardband for the worst possble delay. Tunable replca crcuts n [10] are more accurate but requre more complex crcuts and calbraton steps. By contrast, ths paper has proposed a method that also has small mplementaton overheads because the montor conssts of only a few DDROs. Our method requres a calbraton step to compensate for any dfference between the smulaton model and actual slcon as descrbed n Secton V-B. We expect that our method s more accurate than the method of [16] because we use multple DDROs to trac the delays of crtcal paths. Our method s also more accurate than that n [6] because we estmate the crtcal path delays nstead of the worst-possble delay. Although our method may be less accurate than the tunable replca crcut, our method does not requre calbraton for every chp and also has less mplementaton overhead. VI. CONCLUSION In ths paper, we have proposed methods to systematcally desgn multple DDROs, and to estmate crcut performance (chp delay) based on the measurements from the multple DDROs. We showed that our delay estmaton method can acheve smlar results as the path-based method wth sgnfcantly less booeepng overhead. We also showed that by usng multple DDROs we can reduce the mean delay overestmaton by up to 25% (from 4% to 3%). The reducton s manly lmted by local varaton, whch cannot be captured by replca-le montors. Further delay overestmaton reducton wll requre n stu-type montors, whch have much hgher area and desgn mplementaton overheads. We also observe that the beneft of usng replca-le montors (such as DDROs) s more sgnfcant when the local varaton s relatvely less compared to the global varaton. If local varaton domnates, then n stu montorng, although expensve, wll fare better. Wth shrnng feature dmensons, ncreasng wafer szes, and changng devce structures (e.g, fully depleted SOI, FnFETs), t s dffcult to project whch of the two components of varaton s gong to domnate n future technologes. 9 Ths approach s smlar to our DDRO method wth K = 1. ACKNOWLEDGMENT The authors would le to than Prof. D. Sylvester, Dr. D. Fc, M. Fojt, and Dr. D. Km, Unversty of Mchgan, for ther generous support n tapng out the test chp. REFERENCES [1] D. Arthur and S. Vasslvts, K-means++: The advantages of careful seedng, n Proc. ACM-SIAM Symp. Dscrete Algorthms, 2007, pp [2] M. Bhushan, A. Gatter, M. Ketchen, and K. K. Das, Rng oscllators for cmos process tunng and varablty control, IEEE Trans. Semcond. Manuf., vol. 19, no. 1, pp , Feb [3] T. Blac, A crtcal path based parametrc rng oscllator, M.S. thess, Dept. Electr. Eng., Texas Tech Unv., Lubboc, TX, USA, Dec [4] L. M. Burns, L. Dauphnee, R. A. Gomez, and J. Y. C. Chang, Process montor for montorng and compensatng crcut performance, U.S. Patent , May 20, [5] T.-B. Chan, R. S. Ghada, and P. Gupta, Electrcal modelng of lthographc mperfectons, n Proc. IEEE/ACM Int. Conf. VLSI Desgn, Jan. 2010, pp [6] T.-B. Chan and A. B. Kahng, Tunable sensors for process-aware voltage scalng, n Proc. IEEE/ACM ICCAD, Nov. 2012, pp [7] T.-B. Chan, A. Pant, L. Cheng, and P. Gupta, Desgn dependent process montorng for bac-end manufacturng cost reducton, n Proc. IEEE/ACM ICCAD, Nov. 2010, pp [8] L. Cheng, P. Gupta, K. Qan, C. Spanos, and L. He, Physcally justfable de-level modelng of spatal varaton n vew of systematc across wafer varablty, IEEE Trans. Comput.-Aded Desgn Integr. Crcuts Syst., vol. 30, no. 3, pp , Mar [9] B. Das, B. Amrutur, H. Jamadagn, N. Arvnd, and V. Vsvanathan, Wthn-de gate delay varablty measurement usng reconfgurable rng oscllator, IEEE Trans. Semcond. Manuf., vol. 22, no. 2, pp , May [10] A. Drae, R. Senger, H. Sngh, G. Carpenter, and N. James, Dynamc measurement of crtcal-path tmng, n Proc. IEEE ICICDT, Jun. 2008, pp [11] D. Fc, N. Lu, Z. Foo, M. Fojt, J.-S. Seo, D. Sylvester, and D. Blaauw, In stu delay-slac montor for hgh-performance processors usng an all-dgtal self-calbratng 5ps resoluton tme-to-dgtal converter, n Proc. IEEE ISSCC, Feb. 2010, pp [12] P. Gupta, Y. Agarwal, L. Dolece, N. Dutt, R. K. Gupta, R. Kumar, S. Mtra, A. Ncolau, T. S. Rosng, M. B. Srvastava, S. Swanson, and D. Sylvester, Underdesgned and opportunstc computng n presence of hardware varablty, IEEE Trans. Comput.-Aded Desgn Integr. Crcuts Syst., vol. 32, no. 1, pp. 8 23, Jan [13] K. Kang, S. P. Par, K. Km, and K. Roy, On-chp varablty sensor usng phase-loced loop for detectng and correctng parametrc tmng falures, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 2, pp , Feb [14] L. La, V. Chandra, R. Aten, and P. Gupta, SlacProbe: A low overhead n stu on-lne tmng slac montorng methodology, n Proc. IEEE DATE, Mar. 2013, pp [15] (2010). Lp_Solve Reference Gude [Onlne]. Avalable: sourceforge.net/5.5/ [16] Q. Lu and S. S. Sapatnear, Capturng post-slcon varatons usng a representatve crtcal path, IEEE Trans. Comput.-Aded Desgn Integr. Crcuts Syst., vol. 29, no. 2, pp , Feb [17] I. A. K. M. Mahfuzul, A. Tsuchya, K. Kobayash, and H. Onodera, Varaton-senstve montor crcuts for estmaton of global process parameter varaton, IEEE Trans. Semcond. Manuf., vol. 25, no. 4, pp , Nov [18] H. C. Ngo, G. D. Carpenter, A. J. Drae, and J. B. Kuang, Crcut tmng montor havng a selectable-path rng oscllator, U.S. Patent , Oct. 5, 2010.

14 Ths artcle has been accepted for ncluson n a future ssue of ths journal. Content s fnal as presented, wth the excepton of pagnaton. 14 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS [19] D. J. Phllng and C. Talledo, In-stu montor of process and devce parameters n ntegrated crcuts, U.S. Patent , Sep. 22, [20] K. Sha, Implementaton of a crtcal path based parametrc rng oscllator, M.S. thess, Dept. Electr. Comput. Eng., Texas Tech Unv., Lubboc, TX, USA, [21] A. Tetelbaum and S. Charavarty, Electronc desgn automaton tool and method for optmzng the placement of process montors n an ntegrated crcut, U.S. Patent , Nov. 12, [22] C. Vsweswarah, K. Ravndran, K. Kalafala, S. G. Waler, S. Narayan, D. K. Beece, J. Paget, N. Venateswaran, and J. G. Hemmett, Frst-order ncremental bloc-based statstcal tmng analyss, IEEE Trans. Comput.-Aded Desgn Integr. Crcuts Syst., vol. 25, no. 10, pp , Oct [23] X. X. Wang, M. Tehranpoor, S. George, D. Tran, R. Datta, and L. Wnemberg, Desgn and analyss of a delay sensor applcable to process/envronmental varatons and agng measurements, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 8, pp , Aug [24] L. Xe and A. Davood, Representatve path selecton for post-slcon predcton under varablty, n Proc. ACM/IEEE 47th Desgn Autom. Conf., Jun. 2010, pp [25] L. Xe and A. Davood, Bound-based statstcally-crtcal path extracton under process varatons, IEEE Trans. Comput.-Aded Desgn Integr. Crcuts Syst., vol. 30, no. 1, pp , Jan [26] V. Zolotov, J. Xong, H. Fatem, and C. Vsweswarah, Statstcal path selecton for at-speed test, n Proc. IEEE ICCAD, Sep. 2008, pp [27] T.-B. Chan, P. Gupta, A. Kahng, and L. La, DDRO: A novel performance montorng methodology based on desgn-dependent rng oscllators, n Proc. IEEE ISQED, Mar. 2012, pp [28] (2011). Synopsys PrmeTme User s Manual [Onlne]. Avalable: [29] (2011). Mathwors Matlab Documentaton [Onlne]. Avalable: [30] (2010). Synopsys HSPICE User s Manual [Onlne]. Avalable: [31] M. Grant and S. Boyd. (2012). CVX: Matlab Software for Dscplned Convex Programmng [Onlne]. Avalable: [32] (2013, Jun.). ARM Cortex-M0 Processor [Onlne]. Avalable: [33] (2013, Jun. 11). ARM Cortex-M3 Processor [Onlne]. Avalable: [34] OpenCores [Onlne]. Avalable: Puneet Gupta (M 07) receved the B.Tech. degree n electrcal engneerng from the Indan Insttute of Technology, Delh, Inda, n 2000 and the Ph.D. degree from the Unversty of Calforna, San Dego, CA, USA, n He s currently a Faculty Member wth the Electrcal Engneerng Department, Unversty of Calforna, Los Angeles, CA, USA. He co-founded Blaze DFM, Inc., (acqured by Tela Inc.), Sunnyvale, CA, USA, n 2004, and served as a Product Archtect n He has authored over 100 papers, 15 U.S. patents, a boo, and a boo chapter. Dr. Gupta s a recpent of the Natonal Scence Foundaton CAREER Award, the ACM/SIGDA Outstandng New Faculty Award, the European Desgn Automaton Assocaton Outstandng Dssertaton Award, and the IBM Faculty Award. He has gven several tutoral tals, served on several techncal program commttees, and was a Program Char of the IEEE DFM&Y Worshop n 2009, 2010, and He s the Drector of the Multunversty IMPACT+ Integrated Modelng Process and Computaton for Technology Center. Andrew B. Kahng (F 10) receved the Ph.D. degree n computer scence from the Unversty of Calforna at San Dego (UCSD), La Jolla, CA, USA, n He was wth the Computer Scence Department, Unversty of Calforna at Los Angeles, Los Angeles, CA, USA, from 1989 to Snce 2001, he has been wth the Department of Computer Scence and Engneerng and the Department of Electrcal and Computer Engneerng, UCSD, where he holds the endowed char n hgh-performance computng. He has authored or co-authored more than 400 journal and conference papers, and three boos. He holds 24 ssued U.S. patents. Hs current research nterests nclude IC physcal desgn, the desgn-manufacturng nterface, combnatoral algorthms and optmzaton, and the roadmappng of systems and technology. Tuc-Boon Chan (S 09) receved the M.S. degree from Natonal Tawan Unversty, Tape, Tawan, n He s currently pursung the Ph.D. degree wth the Electrcal and Computer Engneerng Department, Unversty of Calforna, San Dego, CA, USA. He s nvolved n research under the supervson of Prof. A. B. Kahng. Hs current research nterests nclude mtgatng VLSI crcut varablty and mprovng manufacturng yeld through desgn/manufacturng co-optmzaton. Langzhen La (S 12) receved the B.S. degree n electronc engneerng from the Hong Kong Unversty of Scence and Technology, Hong Kong, n 2010 and the M.S. degree n electrcal engneerng from the Unversty of Calforna, Los Angeles, CA, USA, n 2012, where he s currently pursung the Ph.D. degree wth the Department of Electrcal Engneerng. Hs current research nterests nclude hardware varablty montors and cross-dscplnary technques to leverage varablty.