FPGA Device and Architecture Evaluation Considering Process Variations

Transcription

1 FPGA Devce and Archtecture Evaluaton Consderng Process Varatons Ho-Yan Wong, Lerong Cheng, Yan Ln, Le He Electrcal Engneerng Department Unversty of Calforna, Los Angeles {phoebe, lerong, yln, ABSTRACT Process varatons n nanometer technologes are becomng an mportant ssue for cuttng-edge FPGAs wth a multmllon gate capacty. Consderng both de-to-de and wthnde varatons n effectve channel length, threshold voltage, and gate oxde thckness, we frst develop closed-form models of leakage and tmng varatons at the FPGA chp level. Experments show that our models are wthn 3% from Monte Carlo smulaton, and the leakage and delay varatons can be up to 3X and 1.9X, respectvely. We then derve analytcal yeld models consderng both leakage and tmng varatons, and use such models to evaluate FPGA devce and archtecture under process varatons. Compared to the archtecture smlar to a commercal FPGA and devce settng from ITRS roadmap, devce tunng alone mproves leakage yeld by 39% and archtecture and devce co-optmzaton ncreases leakage yeld by 73%. We also show that LUT sze 4 gves the hghest leakage yeld, LUT sze 7 gves the hghest tmng yeld, but LUT sze 5 acheves the maxmum combned leakage and tmng yeld. To the best of our knowledge, ths s the frst n-depth study on FPGA devce and archtecture co-evaluaton consderng process varatons. 1. INTRODUCTION Modern VLSI desgns see a large mpact from process varaton as devces scale down to nanometer technologes. Varablty n effectve channel length, threshold voltage, and gate oxde thckness ncurs uncertantes n both chp performance and power consumpton. For example, measured varaton n chp-level leakage can be as hgh as 0X compared to the nomnal value for hgh performance mcroprocessors [1]. In addton to meetng the performance constrant under tmng varaton, des wth excessvely large leakage due to such a hgh varaton have to be rejected to meet the gven power budget. There have been a few studes on parametrc yeld estmaton consderng both tmng [, 3] and leakage [4, 5] varatons n ASICs. However, the parametrc yeld study for FPGAs s largely unexplored n the lterature. Exstng FPGA archtecture evaluaton has consdered performance, area, and power [6, 7, 8, 9]. [10] evaluated new FPGA archtectures consderng feld programmable supply voltage ncludng dual-vdd and power-gatng. A very recent work [11] showed that devce and archtecture co-optmzaton s able to obtan the largest mprovement n FPGA performance and power effcency. Ths paper s partally supported by NSF CAREER award CCR , and NSF grant CCR We used computers donated by Intel. Address comments to lhe@ee.ucla.edu. However, all the evaluaton work so far dd not consder process varatons. In ths paper, we frst develop closed-form models of leakage and tmng varatons at the FPGA chp level wth consderaton of deto-de and wthn-de varatons. Experments show that our models are wthn 3% from Monte Carlo smulaton, and the leakage and delay varatons can be up to 3X and 1.9X, respectvely. In addton, t s also shown that leakage s more senstve to wthn-de varaton compared to nter-de varaton, whereas tmng s more senstve to nter-de varaton compared to wthn-de varaton. We then evaluate FPGA devce and archtecture under process varatons. Compared to the archtecture smlar to a commercal FPGA and devce settng from ITRS roadmap, devce tunng alone mproves leakage yeld by 39% and archtecture and devce co-optmzaton ncreases leakage yeld by 73%. We also show that LUT sze 4 gves the hghest leakage yeld, LUT sze 7 gves the hghest tmng yeld, but LUT sze 5 acheves the maxmum combned leakage and tmng yeld. The rest of the paper s organzed as follows. Secton presents background knowledge. Secton 3 derves closed-form models for leakage and delay varatons. Secton 4 develops the leakage and tmng yeld models. Secton 5 analyzes the leakage and tmng yeld rates, and Secton 6 concludes the paper.. BACKGROUND We assume the cluster-based sland style FPGA same as the exstng archtecture evaluaton work [8]-[11]. A logc block s a cluster of fully connected Basc Logc Elements that conssts of one LUT and one flp-flop. The cluster sze N and LUT sze K are the archtectural parameters to be evaluated. For smplcty, we assume a fxed routng archtecture same as [11],.e., fully buffered routng swtches and unform wre segment spannng four logc blocks. We also optmze devces n terms of V dd and V th. The above archtecture and devce co-optmzaton may easly have over hundreds devce and archtecture combnatons. A runtme effcent trace-based estmaton tool Ptrace s proposed to handle such co-optmzaton [11]. For a gven benchmark set and a gven FPGA archtecture, statstcal nformaton of swtchng actvty, crtcal path structure, and crcut element utlzaton are collected by proflng the placed and routed benchmark crcuts. These statstcal nformaton s called the trace of the gven benchmark set. Then, closed-form formulas are used to compute power and delay based on trace nformaton and devce parameters. Ptrace has a hgh accuracy compared to the detaled verfcaton, where a crcut s placed and routed by VPR [6] and smulated by cycleaccurate power smulaton Psm [10]. In ths paper, we consder the varaton n threshold voltage X/05/$ IEEE. 19

2 (V th ), effectve channel length (L ef f ), and gate oxde thckness (T ox). Smlar to [4] where ASIC s assumed, each varaton ( P ) s decomposed nto global (de-to-de) varaton ( P g) and local (wthn-de) varaton ( P l ). We wll extend Ptrace to consder the above varatons and then perform devce and archtecture cooptmzaton wth process varatons. 3. LEAKAGE AND TIMING VARIATIONS 3.1 Leakage under Varaton We extend the leakage model n FPGA power and delay estmaton framework Ptrace[11] to consder varatons. In Ptrace,the total leakage of an FPGA chp s calculated as follows, I chp = X N t I (1) where N t s the number of FPGA crcut elements n FPGA resource type,.e., an nterconnect swtch, buffer, LUT, confguraton SRAM cell, or flp-flop, and I s the leakage of an element. Dfferent szes of nterconnect swtches and buffers are consdered as dfferent crcut elements. The leakage current I of a crcut element s the sum of the subthreshold and gate leakages: I = I sub + I gate () Varaton n I sub manly sources from varaton n L ef f and V th. Varaton n I gate manly sources from varaton n T ox. Dfferent from [4] that models subthreshold leakage and gate leakage separately, we model the total leakage current I of crcut element n resource type as follows, I = I n() e f ( L eff ) e f ( V th) e f ( T ox) where I n() s the leakage of a crcut element n resource type n the absence of any varablty and f s the functon that represents the mpact of each type of process varaton on leakage. The nterdependency between these functons has been shown to be neglgble n [4]. From SPICE smulaton, we fnd that t s suffcent to express these functons as smple lnear functons. To make the presentaton smple, we denote L ef f, V th,and T ox as L, V,andT, respectvely. We can express these functons wth ths smple notaton as follows, (3) f(l) = c 1 L f(v )= c V f(t )= c 3 T (4) where c 1,c,c 3 are fttng parameters decded by SPICE smulatons. The negatve sgn n the exponent ndcates that the transstors wth shorter channel length, lower threshold voltage, and smaller oxde thckness lead to hgher leakage current. We rewrte (3) as follows by decomposng L, V and T n to local (L l,v l,t l )and global (L g,v g,t g) components. I = I n() e (c 1L g+c V g+c 3 T g ) e (c 1L l +c V l +c 3 T l ) To extend the leakage model (1) under varatons, we consder that each element has unque local varatons but all elements n one de share the same global varatons. Both global and local varatons are modeled as normal random varables. The leakage dstrbuton of a crcut element s a lognormal dstrbuton. The total leakage s the sum of all lognormals. The state-of-the-art FPGA chp usually has a large number of crcut elements and therefore the relatve random varance of the total leakage approaches zero. Same as [4], we apply the Central Lmt Theorem and use the mean of the dstrbuton to approxmate the dstrbuton of the sum of (5) lognormals. After ntegraton, we can wrte the expresson of the chp-level leakage as the follows, I chp X N t E[I ] = X N t S I Lg,Vg,T g () (6) S = e (c 1σ Ll +c σ Vl +c3 σ Tl )/ I Lg,Vg,T g () = I n()e (c 1L g+c V g+c 3 T g) where S s the scale factor ntroduced due to local varablty n L, V,andT. I Lg,Vg,T g () s the leakage as a functon of global varatons. σ Ll, σ Vl and σ Tl are the varances of L l, V l,andt l, respectvely. For an FPGA archtecture wth power-gatng capablty, an unused crcut element can be power-gated to reduce leakage power. In ths case, Ptracecalculates the total leakage current as follows, I chp = X X N u I + α gatng (N t N u )I (7) where N u s the number of used crcut elements n FPGA resource type and α gatng s the average leakage rato between a powergated crcut element and a crcut element n normal operaton. Same as [11], 1/300 s used for α gatng n ths paper. Smlar to (6), (7) can be easly extended to consder varatons as follows, I chp X where E[I ] s stll defned as n (6). X N u E[I ]+α gatng (N t N u )E[I ](8) 3. Tmng under Varaton The performance depends on L ef f, V th,andt ox, but ts varaton s prmarly affected by L ef f varaton[4]. Below we extend the delay model n Ptrace to consder global and local varatons of L ef f. The structure of the crtcal path for each benchmark s obtaned for tmng analyss. The path delay can be calculated as follows, D = X d (L g,l l ) (9) For crcut element n the path, d (L g,l l ) s the delay consderng global varaton L g and local varaton L l. L g s the same for all the crcut elements n the crtcal path. Gven L g,weevenly sample a few (eleven n ths paper) ponts wthn range of [L g 3σ Ll,L g +3σ Ll ]. We then perform SPICE smulaton to obtan the delay for each crcut element wth these varatons. As the delay monotoncally decreases when L ef f ncreases, we can drectly map the probablty of a channel length to the probablty of a delay and obtan the delay dstrbuton of a crcut element. We assume that the local channel length varaton of each element s ndependent from each other. Therefore, we can obtan the dstrbuton of the crtcal path delay for a gven L g as follows by convoluton operaton, PDF(D) =PDF(d 1) PDF(d ) PDF(d ) PDF(d n) (10) 4. YIELD MODELS 4.1 Leakage Yeld The leakage yeld s calculated on a bn-by-bn bass where each bn corresponds to a specfc value L g. For a partcular bn, the 0

3 value L g s constant. We can rewrte (6) for chp-level leakage current as follows, I chp A = X A e c Vg e c 3T g (11) = N I n()s e c 1L g where A s the leakage current for all crcut elements of resource type at a value of L g and ncludes the scale factor S due to the local varablty. Let X be the leakage consumed by the elements of resource type and t s a lognormal varable. The chp-level leakage current I chp s the sum of each lognormal varable X [4] and t can be expressed as follows, I chp = X X (1) X Lognormal(log(A ), ((c σ Vg ) +(c 3σ Tg ) )) Same as [4], we model I chp, the sum of the lognormal varables X, as another lognormal random varable. The lognormal varable X shares the same random varables σ Vg and σ Tg, and therefore these varables are dependent of each other. Consderng the dependency, we calculate the mean and varance of the new lognormal I chp as follows, µ Ichp = P {exp[log(a)+ (c σ Vg ) + (c 3σ Tg ) ]} (13) σ Ichp = P {exp[log(a)+(cσvg ) +(c 3σ Tg ) ] [exp(c σv g + c 3σT g ) 1]} + P,j COV (X,Xj) (14) where the mean of I chp, µ Ichp, s the sum of means of X and the varance of I chp, σ Ichp, s the sum of varance of X and the covarance of each par of X. The covarance s calculated as follows, COV (X,X j) = E[X X j] E[X ]E[X j] (15) E[X X j] = exp[log(a A j)+ (c + cj) σ Vg + (c3 + cj3) σ Tg ] E[X ] = exp[log(a )+ (cσvg ) + (c3σtg ) ] We then use the method from [4] to obtan the mean and varance (µ N,Ichp,σ N,Ichp ) of the normal random varable correspondng to the lognormal I chp. As the exponental functon that relates the lognormal varable I chp wth the normal varable I N,chp s a monotone ncreasng functon, the CDF of I chp can be expressed as follows usng the standard expresson for the CDF of a lognormal random varable, µ N,Ichp = log[µ I 4 /(µ chp Ichp +σ Ichp )] σ N,Ichp = log[1 + (σ Ichp /µ Ichp )] Y leak (I chp Lg )=CDF(I chp ) = 1 [1 + erf( log(i chp) µ N,Ichp σn,ichp )] (16) where erf() s the error functon. Gven a leakage lmt I cut for I chp, [CDF(I cut) 100%] gves the leakage yeld rate Y leak (I cut L g),.e., the percentage of FPGA chps that s smaller than I cut n a partcular L g bn. Smlarly, the yeld for the FPGA chp wth power-gatng capablty can be easly calculated usng (8). 4. Tmng Yeld The tmng yeld s agan calculated on a bn-by-bn bass where each bn corresponds to a specfc value L g. We further consder local varaton of channel length n tmng yeld analyss. Gven the global channel length varaton L g, (10) gves the PDF of the crtcal path delay D of the crcut. We can obtan the CDF of delay, CDF(D L g), byntegratngforagvenl g. Gven a cutoff delay (D cut)andl g, CDF(D cut L g) gves the probablty that the path delay s smaller than D cut consderng L ef f varatons. However, t s not suffcent to only analyze the orgnal crtcal path n the absence of process varatons. The close-to-be crtcal paths may become crtcal consderng varatons and an FPGA chp that meets the performance requrement should have the delay of all paths no greater than D cut. We assume that the delay of each path s ndependent and we can calculate the tmng yeld for a gven L g as follows, Y perf (D cut L g)= ny CDF (D cut L g) (17) =1 where CDF (D cut L g) gves the probablty that the delay of the th longest path s no greater than D cut. In ths paper, we only consder the ten longest paths,.e., n =10because the smulaton result shows that the ten longest paths have already covered all the paths wth a delay larger than 75% of the crtcal path delay under the nomnal condton. We then ntegrate Y perf (D cut L g) to calculate the performance yeld Y perf as follows, Y perf = Z + PDF(L g) Y perf (D cut L g) dl g (18) 4.3 Leakage and Tmng Combned Yeld To analyze the yeld of a lot, we need to consder both leakage and delay lmt. Gven a specfc global varaton of channel length L g, the leakage varablty only depends on the varablty of random varable V g and T g as shown n (6), and the tmng varablty only depends on the varablty of random varable L l. Therefore, we assume that the leakage yeld and tmng yeld are ndependent of each other. The yeld consderng the mposed leakage and tmng lmt can be calculated as follows, Y com = Z + PDF(L g)y leak (I cut L g)y perf (D cut L g) dl g (19) 5. LEAKAGE AND TIMING YIELD ANALYSIS For the total power and leakage power we report the arthmetc mean of 0 MCNC benchmarks wthn and among three FPGA archtecture classes: Homo-V t s the conventonal FPGA usng the same and optmzed V t for both logc blocks and nterconnect; Hetero-V t optmzes V t separately for logc blocks and nterconnect; and Homo-V t+g s the same as Homo-V t except that unused logc blocks and nterconnect are power-gated as studed n[10]. We assume 10% of the nomnal value as 3σ for all the process varatons. 5.1 Leakage Yeld Fgure 1 shows the full chp leakage power smulated by Monte Carlo smulaton and σ, n the presence of nter-de and ntra-de varatons. Leakage may change sgnfcantly due to process varatons. When there s a ±3σ nter-de varaton of L ef f, the leakage power has a 3X span. When no varaton s present, there s stll a X span n leakage power due to wthn-de varaton. Clearly, 1

4 Normalzed Leakage Power X Global Leff Varaton (σ) Fgure 1: Leakage power of baselne archtecture (N=8, K=4) wth ITRS devce settng under ntrade and nter-de varatons. leakage s more senstve to wthn-de varaton compared to nterde varaton. Therefore t s mportant to consder the mpact of process varatons on leakage when determnng the yeld. We further valdate our chp-level analytcal model for leakage by Monte Carlo smulaton to estmate the full chp leakage power n Table 1, where global varatons are all set to ±3σ, and local varatons are set to 0, ±1σ,and ±σ. The mean calculated from our analytcal method has a less than 3% dfference from the smulaton and the standard devatons dffered by 1% of the mean value. In the rest of the paper, we always report the standard devaton as a relatve value wth respect to the mean and use our analytcal model to calculate the yeld. Varatons(σ) Mean(W) SD(%) (L g, L l ) (V g, V l ) (T g, T l ) M-C Model M-C Model (±3,0) (±3,0) (±3,0) (±3,±1) (±3,±1) (±3,±1) (±3,±) (±3,±) (±3,±) Table 1: Comparson between analytcal varaton models and Monte Carlo (M-C )smulaton Impact of Archtecture and Devce Tunng In ths secton we consder combnatons of devce and archtecture parameters, called as hyper-archtecture (n short, hyperarch). Table shows the yeld, mean leakage, and standard devaton from two dfferent devce settngs, sorted by the yeld. Columns 1-4 use ITRS devce settng. Our baselne FPGA has N =8and K =4, whch s the archtecture used by Xlnx Vrtex-II Pro. Yeld s calculated usng the nomnal leakage of each archtecture plus an offset of 30% of the nomnal leakage of baselne archtecture, P L base, as the leakage lmt. As shown n column 1 of Table, the yeld ranges from 4% to 70%, whch shows that archtecture tunng has a sgnfcant mpact on the yeld. Among all archtectures, N =6and K =5gves the maxmum yeld, whch s 1% hgher than the baselne. The yeld s affected by both the mean and varance. When the mean leakage s close to the leakage lmt, the varance gans mportance n determnng the yeld. However, when the mean s not close to the lmt, the varance does not have that much mpact on the yeld. In ths case, the lower the mean leakage s, the hgher the yeld s (see columns 5 8). It s also notceable that larger LUT szes have larger mean leakage, thus yeld becomes smaller. X ITRS Vdd0.80V/V t0.0v Mn ED Vdd0.90V/V t0.30v Y Mean SD (N,K) Y Mean SD (N,K) (%) (W) (%) (%) (W) (%) (6, 5) (6, 4) (8, 3) (8, 4) (10, 3) (10, 4) (1, 3) (6, 5) (6, 4) (8, 3) (8, 4) (10, 3) (10, 4) (1, 3) (8, 5) (1, 4) (10, 5) (8, 5) (1, 5) (10, 5) (3, 6) (3, 6) (1, 4) (1, 5) (8, 6) (6, 6) (6, 6) (8, 6) (10, 6) (10, 6) (1, 6) (1, 6) (6, 7) (6, 7) (8, 7) (8, 7) (10, 7) (10, 7) (1, 7) (1, 7) Table : Comparson of Dfferent Devce Settng Devce tunng also affects the yeld. In Columns 5 8 of Table, we use a devce settng that provdes the mnmum energy-delay product (mnmum product of energy per clock cycle and crtcal path delay, n short, mn-ed) gven n [11]. Column 5 shows that optmzng Vdd and V t can ncrease the yeld rate of each archtecture by an average of 39%. Therefore, devce tunng has a great mpact on yeld rate and t s mportant to evaluate dfferent Vdd and V t levels whle consderng process varatons. Comparng the yeld of archtecture (1, 7) n ITRS devce settng and archtecture (6, 4) n Mn-ED devce settng shows that combnng devce tunng wth archtecture tunng can ncrease the yeld by up to 73%. From the Table, archtectures wth K=4 generally provdes the hghest yeld rate, and they have the mnmum area as reported n prevous work such as [11]. In the rest of the paper, we wll only consder domnant archtectures. Domnant archtectures are defned as the group of archtectures that ether has smaller delay or less energy consumpton than others [11]. Fg presents the energy and delay tradeoff between domnant archtectures assumng Homo-V t class. Total FPGA Energy/Cycle (nj) (6,7) (8,5) (10,5) (1,4) (8,4) Crtcal Path Delay (ns) (10,4) Fgure : Energy-delay tradeoff among archtectures n Homo-V t usng mn-ed devce settng Impact of Heterogeneous-V t and Power-gatng

5 Normalzed Delay X 1.9X Global Leff Varaton (σ) Fgure 3: Delay of baselne archtecture (N=8, K=4) wth ITRS devce settng under ntra-de and nter-de Leff varaton. It has been shown that heterogeneous-v t and power-gatng may have great mpact on energy delay tradeoff [11]. Here we further consder the mpact of heterogeneous-v t on the yeld by comparng Homo-V t and Hetero-V t n mn-ed devce settng. Table 3 shows the results of the domnant archtectures n all classes. The average yeld for each class s presented n the last row of the table. Comparng the yeld of Homo-V t and Hetero-V t, we can see that the average yeld s mproved by 5% va applyng dfferent V t for logc blocks and nterconnect. Therefore, ntroducng heterogeneous-v t could mprove yeld wth no or lttle area ncrease (due to an ncrease n dopng well area). Furthermore, power-gatng can be appled to unused FPGA logc blocks and nterconnect to reduce leakage power. As only one sleep transstor s used for one logc block, we use a 10X PMOS as the sleep transstor for each logc block. For nterconnect, the area overhead assocated wth sleep transstors s more sgnfcant. We therefore use a X PMOS as the sleep transstor for each nterconnect swtch. Comparng the yeld of Homo-V t and Homo-V t+g n Table 3, applyng power-gatng can mprove the yeld by 8%. Comparng the yeld of Hetero-V t and Homo-V t+g, power-gatng can obtan more yeld mprovement than heterogeneous-v t at the cost of chp-level area overhead between 10% to 0%. As leakage power can be greatly reduced by power-gatng, lttle beneft can be ntroduced by applyng smultaneous heterogeneous-v t and power-gatng, and we wll not present the results here. Agan, wth heterogeneous-v t or power-gatng, LUT sze K=4 s the best for leakage yeld rate. 5. Tmng Yeld For tmng yeld analyss, we only analyze the delay of the largest MCNC benchmark clma. Smlarly, the tmng yeld s often studed usng selected test crcut such as rng oscllator for ASIC n the lterature. Fgure 3 shows the delay wth ntra-de and nter-de channel length varaton at baselne archtecture (8, 4) wth ITRS devce settng. As shown n the fgure, there s a 1.9X span wth ±3σ L g varaton, and a 1.1X span wthout L g varaton. Clearly, delay s more senstve to nter-de varaton than wthn-de varaton. Ths s because of the ndependence of local L ef f varaton between each element. Therefore the effect of wthn-de L ef f varaton tends to average out when the crtcal path s long enough. For tmng yeld, we dscard des wth crtcal delay larger than the cutoff delay, whch s 1.1X of the nomnal crtcal path delay of each archtecture. Table 4 shows the delay yeld of Homo-V t+g. One can see from ths table that a larger LUT sze wll gve a hgher yeld rate. Ths s because a larger LUT sze generally gves a smaller mean delay wth a shorter crtcal path (see Fg ),.e., smaller number of elements n the path, whch leads to a smaller varance. Therefore, a larger LUT sze leads to a hgher tmng yeld. As the tmng specfcaton may be relaxed for certan applcatons that are not tmng-crtcal, the cutoff delay may be relaxed n ths case. In ths table, we also show the yeld wth the cutoff delay as 1.X of the nomnal delay. The yeld rate under a hgher cutoff stll has the same trend as that under a lower cutoff. Note that the other archtecture classes have smlar trends on tmng yeld. Y1.1X(%) Y1.X(%) Mean (ns) (6,4) (8,4) (10,4) (1,4) (6,5) (8,5) (10,5) (6,6) (8,6) (6,7) Avg Table 4: Tmng yeld for Homo-V t+g 5.3 Leakage and Tmng Combned Yeld Fgure 4 presents the leakage and delay varaton for the baselne case usng Monte Carlo smulaton wth Ptrace. It can be seen that a smaller delay leads to a larger leakage n general. Ths s because of the nverse correlaton between crcut delay and leakage. A devce wth short channel length has a small delay and consumes large leakage, whch may lead to a hgh leakage. To calculate the leakage and delay combned yeld, we set the cutoff leakage as the nomnal leakage plus 30% that of the baselne, whle the cutoff delay s 1.X of each archtecture s nomnal delay. Table 5 presents the combned yeld for Homo-V t wth ITRS devce settng and all classes wth mn-ed devce settng. The area overhead ntroduced by power-gatng s also presented n the table. Comparng Homo-V t wth ITRS devce settng and mn-ed devce settng, the combned yeld s mproved by 1%. Comparng the classes usng mn-ed devce settng, Hetero-V t has a 3% hgher yeld than Homo-V t due to heterogeneous-v t whle Homo-V t+g has a 8% hgher yeld than Homo-V t due to power-gatng. Homo- V t+g has the hghest combned yeld wth an average of 16% area overhead. Devce tunng and power-gatng mprove yeld by 9% comparng Homo-V t+g wth mn-ed settng to Homo-V t wth ITRS settng. Ths table also shows that archtectures wth LUT sze 5 gves the hghest yeld wthn each class. Ths s because t has both a relatvely hgh leakage yeld as well as tmng yeld. 6. CONCLUSIONS AND DISCUSSIONS In ths paper, we have developed effcent models for chp-level leakage varaton and system tmng varaton n FPGAs. Experments show that our models are wthn 3% from Monte Carlo smulaton, and the leakage and delay varatons can be up to 3X and 1.9X, respectvely. In addton, leakage s more senstve to wthn-de varatons compared to de-to-de varatons, but tmng s more senstve to de-to-de varatons. We have shown that archtecture and devce tunng has a sgnfcant mpact on FPGA parametrc yeld rate. LUT sze 4 has the hghest leakage yeld, 7 3

6 Homo-V t Hetero-V t Homo-V t+g (N,K) Vdd V t Y Mean SD Vdd CV t IV t Y Mean SD Vdd V t Y Mean SD (V) (V) (%) (W) (%) (V) (V) (V) (%) (W) (%) (V) (V) (%) (W) (%) (6,4) (8,4) (10,4) (1,4) (6,5) (8,5) (10,5) (6,6) (8,6) (6,7) Avg Table 3: Comparson of leakage yeld between classes. Normalzed Leakage Power % Leakage 10% Delay Normalzed Delay Fgure 4: Leakage and delay of baselne archtecture (N=8, K=4) wth ITRS settng under process varatons. ITRS Mn-ED (N,K) Homo-V t Homo-V t Hetero-V t Homo-V t+g Y(%) Y(%) Y(%) Y(%) Area Inc(%) (6,4) (8,4) (10,4) (1,4) (6,5) (8,5) (10,5) (6,6) (8,6) (6,7) Avg Table 5: Combned Leakage-delay yeld between FPGA Classes. [3] A. Gattker, S. Nassf, R. Dnakar, and C. Long, Tmng yeld estmaton from statc tmng analyss, n Internatonal Symposum on Qualty of Electronc Desgn, 001. [4] R. Rao, A. Devgan, D. Blaauw, and D. Sylvester, Parametrc yeld estmaton consderng leakage varablty, n Proc. Desgn Automaton Conf., June 004. [5] S. Zhang, V. Wason, and K. Banerjee, A probablstc framework to estmate full-chp subthreshold leakage power dstrbuton consderng wthn-de and de-to-de p-t-v varatons, n ISLPED, Aug 004. [6] V. Betz, J. Rose, and A. Marquardt, Archtecture and CAD for Deep-Submcron FPGAs. Kluwer Academc Publshers, Feb [7] V. Betz and J. Rose, FPGA routng archtecture: Segmentaton and bufferng to optmze speed and densty, n Proc. ACM Intl. Symp. Feld-Programmable Gate Arrays, Feb [8] E. Ahmed and J. Rose, The effect of LUT and cluster sze on deep-submcron FPGA performance and densty, n Proc. ACM Intl. Symp. Feld-Programmable Gate Arrays, pp. 3 1, Feb 000. [9] F. L, D. Chen, L. He, and J. Cong, Archtecture evaluaton for power-effcent FPGAs, n Proc. ACM Intl. Symp. Feld-Programmable Gate Arrays, Feb 003. [10] Y. Ln, F. L, and L. He, Power modelng and archtecture evaluaton for FPGA wth novel crcuts for vdd programmablty, n Proc. ACM Intl. Symp. Feld-Programmable Gate Arrays, February 005. [11] L. Cheng, P. Wong, F. L, Y. Ln, and L. He, Devce and archtecture co-optmzaton for FPGA power reducton, n Proc. Desgn Automaton Conf., June 005. has the hghest tmng yeld, but LUT sze 5 acheves the maxmum combned leakage and tmng yeld. We assume a fxed nterconnect structure n ths paper, and wll study the mpact of herarchcal nterconnect structure wth process varatons n the future. 7. REFERENCES [1] S. Borkar, T. Karnk, S. Narendra, J. Tschanz, A. Keshavarz, and V. De, Parameter varatons and mpact on crcuts and mcroarchtecture, n Proc. Desgn Automaton Conf., June 003. [] S. R. Nassf, Modelng and analyss of manufacturng varatons, n Proc. IEEE Custom Integrated Crcuts Conf.,