數位邏輯 ( 一 ) Text: : Charles H. Roth, Jr. Fundamentals of Logic Design 5th Edition THOMSON BROOKS/COLE. Review units 1-9 1

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1 數位邏輯 ( 一 ) Text: : Charles H. Roth, Jr. Fundamentals of Logic Design 5th Edition 2004 THOMSON BROOKS/COLE Review units 1-9 1

2 Digital Systems and Switching Circuits Digital system The physical quantities or signals can assume only discrete values Greater accuracy Analog system The physical quantities or signals may vary continuously over a specified range Review units 1-9 2

3 Review units 1-9 3

4 Digital Systems and Switching Circuits Design of digital systems System design Breaking the overall system into subsystems Specifying the characteristics of each subsystem E.g. digital computer : memory units, arithmetic unit, I/O devices, control unit Logic design Determining how to interconnect basic logic building blocks to perform a specific function E.g. arithmetic unit : binary addition: logic gates, Flip-Flops, Flops, interconnections Circuit design Specifying the interconnection of specific components such as resistors, diodes, and transistors to form a gate, flip-flop flop or other logic building block E.g. Flip-Flop: Flop: resistors, diodes, transistors Review units 1-9 4

5 Digital Systems and Switching Circuits Many of subsystems of a digital system take the form of a switching network Switching Networks Combinational Networks No memory Sequential Networks Combinational Circuits + Memory Review units 1-9 5

6 Basic Operations The basic operations of Boolean algebra are AND, OR, and NOT (complement, or inverse). NOT (Complement) 0 = 1 1 = 0 X = 1 if X = 0 and X = 0 if X = 1 Inverter Review units 1-9 6

7 Basic Operations AND Operation Omit the symbol.,, A. B=AB AND Gate Review units 1-9 7

8 Basic Operations OR operation OR Gate Review units 1-9 8

9 Exclusive-OR and Equivalence Operations Exclusive-OR: 0 1 = 1 Truth table and gate for 0 0 = = = X Y 0 X Y =1 if and only if X=1 or Y=1 and X and Y are not both 1. Review units 1-9 9

10 Exclusive-OR and Equivalence Operations The equivalence operation ( ) is defined by The truth table for X Y is ( X Y) = 1 X = Y if and only if. Review units

11 Exclusive-OR and Equivalence Operations ( X Y ) = XY + X Y Equivalence is the complement of exclusive-or OR: ( X Y ) = ( X Y + XY ) = ( X + Y )( X + Y ) = XY + X Y = ( X Y ) Alternate symbol for the equivalence gate The equivalence gate is also called an exclusive-nor gate. Review units

12 NAND and NOR Gates NAND gate: An AND gate followed by an NOT gate n-input NAND gates: F = ) n=2 ( AB = A + B n=3 F = ( ABC) = A + B + C F =... ( X1X 2... X n) = X1 + X X n Review units

13 NAND and NOR Gates NOR gate: An OR gate followed by an NOT gate n-input NOR gates: F = ( A + B) = A B n=2 n=3 F = ( A + B + C) = A B C F =... ( X1 + X X n) = X1X 2 X n Review units

14 Boolean Expressions and Truth Tables Order in which the operations are perform Parentheses Complentation Complentation AND OR Circuits for expressions A B + C [ A ( C + D) ] + BE Review units

15 Truth Table If an expression has n variables, the number of different combinations of values of the variables is 2 n. Therefore, a truth table for n-variable n expression will have 2 n rows. (2 ) There are functions of n variables. 2 n Review units

16 Sum-of of-products (SOP) An expression is said to be in sum-of of-products form when all products are the products of only single variables. AB + CD E + AC E, A + B + C + D E are ( A + B)CD + EF is not in SOP form. Product-of of-sums (POS) in SOP form, An expression is said to be in product-of of-sums form when all sums are the sums of only single variables. ( A + B )( C + D + E)( A + C + E ), AB C( D + (A + B)(C + D) + EF is not in POS form. E) are in POS form, Review units

17 Combinational Logic Design Using a Truth Table Example: : Design a switching circuit with three inputs A, B, and C and one output f. The input A,B, and C represent the first, second,, and third bits, respectively, for a binary number N. f=1 if N and f=0 if N < Sol-1: Review units

18 Combinational Logic Design Using a Truth Table Sol-1 1 (cont.): Derive an algebraic expression for f from the truth table by using the combinations of values of A,B, and C for which f=1. =1. f = A BC + AB C + AB C + ABC + ABC = A BC + AB + AB = A BC + A = A + BC The circuit is Review units

19 Combinational Logic Design Using a Truth Table f Sol-2: First write f as a sum of products, and then complement the result. f is 1 for input combinations ABC=000, 001, 010, so = = ( f = ( A + = ( A + A + BC f = A B C + A B C + A BC ) = ( A B C + A B C B + C)( A + B)( A + B + C) B + C )( A + + A BC ) B + C) ( Three 3-input OR gates and one 3-input AND gate) [Two OR gates and one AND gate] Review units

20 Minterm and Maxterm Expansions Minterm A minterm of n variables is a product of n literals in which each variable appears exactly once in either true or complement form, but not both. Maxterm A maxterm of n variables is a sum of n literals in which each variable appears exactly once in either true or complement form, but not both. Review units

21 Minterm and Maxterm Expansions Minterm and Maxterm for three variables Review units

22 Minterm and Maxterm Expansions Minterm expansion or Standard sum of products When a function is written as a sum of minterms,, this is referred to as a minterm expansion or standard sum of products. Examples: f ( A, B, C) = A BC + AB C + AB C + ABC + f ( A, B, C) = m + m + m + m + m ABC f ( A, B, C) m = (3,4,5,6,7 ) Review units

23 Minterm and Maxterm Expansions Maxterm expansion or Standard product of sums When a function is written as a product of maxterms, this is referred to as a maxterm expansion or standard product of sums. Example: f ( A, B, C) = ( A + B + C)( A + B + C )( A + B + C) f ( A, B, C) = M M M f ( A, B, C) M = (0,1,2 ) Review units

24 Minterm and Maxterm Expansions Complement of a function f. Example: f ( A, B, C) = m + m + m + m + m f = ( m m ) 7 = m 4 + m5 + m6 + m = 3m4m5m 6m7 M 3M 4M 5M 6M 7 f ( A, B, C) = M M1M 2 f = ( M = M + M + M = m + m + m 0 0 M1M 2) Review units

25 Incompletely Specified Functions Incompletely Specified Function A function contains don t t care terms. Example 1: The output of subcircuit N 1 drives the input of the subcircuit N 2. Assume that there are no combinations of values for w,x,y, and z which cause A,B, and C to assume values of 001 or The function F is incompletely specified. Review units

26 Incompletely Specified Functions Example 1(cont.): 1. Assign 0 to both X sx 2. Assign 1 to the first X and 0 to the second --- simplest solution 3. Assign 0 to the first X and 1 to the second F F F = A B C + A BC + ABC = A B C + = m( 0,3,7) + d(1,6 ) = M ( 2,4,5) D(1,6 ) BC F = A B C + A B C + A BC + ABC = A B + BC F = A B C + A BC + ABC + ABC = A B C + A BC + AB 4. Assign 1 to both X sx F = ABC + ABC + ABC + ABC + ABC= AB + BC+ AB Review units

27 Examples of Truth Table Construction Example 2: Design an adder which adds two 2-bit binary numbers to give a 3-bit 3 binary sum. The circuit has 4 inputs and 3 outputs : Review units

28 Examples of Truth Table Construction Example 2(cont.): The output functions are : X ( A, B, C, D) Y ( A, B, C, D) = = m(7,10,11,13,14,15) m(2,3,5,6,8,9,12,15) Z( A, b, C, D) = m(1,3,4,6,9,11,12,14) Review units

29 Design of Binary Adders and Subtracters Half Adder: Review units

30 Design of Binary Adders and Subtracters Full Adder: Review units

31 Design of Binary Adders and Subtracters The logic equation for the full adder: Review units

32 Design of Binary Adders and Subtracters The logic circuit of full adder: Review units

33 Design of Binary Adders and Subtracters 4-Bit Parallel Adder Adds two 4-bit 4 unsigned binary numbers Review units

34 Design of Binary Adders and Subtracters 4-Bit Parallel Adder Review units

35 Unit 5 Karnaugh Maps

36 Two- and Three- Variable Karnaugh Maps 2- variable Karnaugh Maps Example: Review units

37 Two- and Three- Variable Karnaugh Maps 2- variable Karnaugh Maps Example: Review units

38 Two- and Three- Variable Karnaugh Maps 3-variable Karnaugh Maps Review units

39 Two- and Three- Variable Karnaugh Maps Adjacent Cells Two cell which differ in just one variable are said to be adjacent. 2 k adjacent calls can be combined. Review units

40 Two- and Three- Variable Karnaugh Maps If F is given as a minterm (maxterm)) expansion, the map by placing 1 s(0 s) ) in the squares which correspond to the minterm ( maxterm) ) and then by filling in the remaining squares with 0 s(1 s). Example: F ( a, b, c) = m1 + m3 + m5 = M0M2M4M6M7 Review units

41 Two- and Three- Variable Karnaugh Maps If a function is given in algebraic form, plot it s Karnaugh Map. Example: f ( a, b, c) = abc + b c + a Review units

42 Two- and Three- Variable Karnaugh Maps Simplify a function using Karnaugh Map Example: F = m(1,3,5 ) Review units

43 Two- and Three- Variable Karnaugh Maps Simplify a function using Karnaugh Map Example: Simplify the complement of F = m(1,3,5 ) Review units

44 Two- and Three- Variable Karnaugh Maps Illustrate the Consensus Theorem Example: xy + x z + yz = xy + x z Review units

45 Two- and Three- Variable Karnaugh Maps Minimum sum-of of-products is not unique. Example: f = m(0,1,2,5,6,7 ) Review units

46 Four- Variable Karnaugh Maps 4-Variable Karnaugh Maps Review units

47 Four- Variable Karnaugh Maps Example: f ( a, b, c, d) = acd + a b + d Review units

48 Four- Variable Karnaugh Maps Example: Simplify f 1 = m(1,3,4,5,10,12,13) f 2 = m(0,2,3,5,6,7,8,10,11,14,15) Review units

49 Four- Variable Karnaugh Maps Simplify a function with don t t care Example: f m( 1,3,5,7,9) + d = (6,12,13) All the 1 s 1 s must be covered,, but the X s are only used if they will simplify the resulting expression. Review units

50 Four- Variable Karnaugh Maps Find a minimum product-of of-sums 1. Find a minimum sum-of of-products for F F 2. Complement F F using DeMorgan s Theorem Example: Find a minimum product-of of-sums for f = x z + wyz + w y z + x y f = y z + wxz + w xy f = ( f ) = ( y+ z )( w + x + z)( w+ x + y ) Review units

51 Determination of Minimum Expansions Using Essential Prime Implicants Cover: A switching function f(x 1,x 2,,x n ) is said to cover another function g(x 1,x 2,,x n ), if f assumes the value 1 whenever g does. Cover: Implicant : Given a function F of n variables, a product term P is an implicant of F iff for every combination of values of the n variables for which P=1, F is also equal 1.That is, P=1 implies F=1. Prime Implicant: A prime prime implicant of a function F is a product term implicart which is no longer an implicant if any literal is deleted from it. Essential Prime Implicant: If If a minterm is covered by only one prime implicant,, then that prime implicant is called an essential prime implicant. Review units

52 Implicant : 函數 f 在卡諾圖中任何單一個 1 或任何一組 1 可以被合併在一起而形成一個積項, 則被稱為 F 的含項 Prime Implicant: 若一個積項不能再和其他項合併消去變數則稱為質含項 Essential Prime Implicant: 某些最小項 (minterm 全及項 ) 只被單一個質含項包含, 如果一個最小項只被一個質含項包含, 則包含此最小項的質含項稱為基本質含項 Review units

53 Determination of Minimum Expansions Using Essential Prime Implicants On a Karnaugh Map Any single 1 or any group of 1 s 1 s (2 k 1 s, k=0,1,2, ) which can be combined together on a map of the function F represents a product term which is called an implicant of F. A product term implicant is called a prime implicant if it cannot be combined with another term to eliminate a variable. If a minterm is covered by only one prime implicant, then that prime implicant is called an essential prime implicant. Review units

54 Determination of Minimum Expansions Using Essential Prime Implicants Examples f=wx+yz wx+yz,, g=wxy wxy g=1 (w=1,x=1,y=0) implies f= z=1, f covers g. g is a product term, g is an implicant of f. f g is not a prime implicant.. The literal y y is deleted from wxy,, the resulting term wx is also an implicant of f. h=wx is a prime implicant.. The deletion of any literal (w or x) results a new product (x or w) which is not covered by f. [w=1 does not imply f=1 (w=1,x=0,y=0,z=0 imply f=0)] Review units

55 5-Variable Karnaugh Maps 5-variable Karnaugh Map Review units

56 5-Variable Karnaugh Maps Example : Simplify the function F( A, B, C, D, E) m(0,1,4,5,13,15,20,21,22,23,24,26,28,30,31) = Review units

57 Unit 7 Multi-Level Gate Circuits NAND and NOR Gates

58 Multi-Level Gate Circuits Increasing/reducing the number of levels Increasing the number of levels Reduce the required number of gates Reduce the number of gate inputs Increase gate delays Reducing the number of levels Reduce gate delays, speed up the operation of the digital system Review units

59 Multi-Level Gate Circuits Example: 4 levels 6 gates 13 gate inputs Review units

60 Functionally Complete A set of logic operations is said to be functionally complete if any Boolean function can be expressed in terms of this set of operations. {AND,OR,NOT} is functionally complete. Any set of logic gates which can realize AND,OR, and NOT is also functionally complete. {NAND} is functionally complete. {NOR} is functionally complete. {AND,OR} is not functionally complete. Review units

61 Functionally Complete {AND,NOT} is functionally complete. {OR,NOT} is functionally complete. Review units

62 Functionally Complete {NAND} is functionally complete. Any switching function can be realized using only NAND gates. Review units

63 Functionally Complete {NOR} is functionally complete. Any switching function can be realized using only NOR gates. Review units

64 Design of Two-level Circuits Using NAND and NOR Gates Example (cont.): Review units

65 Design of Two-level Circuits Using NAND and NOR Gates Example (cont.): Review units

66 Design of Two-Level, Multiple- Output Circuits Example: Design a circuit with four inputs and three outputs which realizes the functions F ( A, B, C, D) = m(11,12,13,14,15) Example: F F ( A, B, C, D) ( A, B, C, D) = = m(3,7,11,12,13,15) m(3,7,12,13,14,15) Sol: Each function is realized individually. The cost of the resulting circuit is 9 gates and 21 gate inputs. Review units

67 Design of Two-Level, Multiple- Output Circuits Sol (cont.): F ( A, B, C, D) = 1 F (A,B,C,D) = 2 F (A,B,C,D) = 3 m(11,12,13,14,15) = AB + ACD m( 3, ,,,, ) = ABC + CD m( 3, ,,,, ) = A CD + AB Review units

68 Design of Two-Level, Multiple- Output Circuits Sol (cont.): Review units

69 Design of Two-Level, Multiple- Output Circuits Sol (cont.): Use the Use the common terms to save gates. F 1 =AB+ACDACD F 2 =ABC +CD=ABC +A CD+ACD F 3 =A CD+AB Review units

70 Design of Two-Level, Multiple- Output Circuits Sol (cont.): 4 AND gates 3 OR gates In realizing multiple-output circuits, the use of a minimum sum-of of-product implicants for each function does not necessarily lead to a minimum cost solution for the circuit as a whole. Review units

71 Unit 08 Combinational Circuit Design and Simulation Using Gates

72 Gate Delays and Timing Diagrams Propagation delay : If the change in output is delayed by time, ε, with respect to the input, we say that this gate has a propagation delay of ε. Propagation delay in an inverter Review units

73 Gate Delays and Timing Diagrams Timing Diagram Example: Assume that each gate has a propagation delay of 20 ns (nanoseconds). Review units

74 Gate Delays and Timing Diagrams Example: Circuit with and delay element Review units

75 Hazards in Combinational Logic The unwanted switching transients may appear in the output when different paths from input to output have different propagation delays. Static 1-1 hazard: If, in response to any single input change and for some combination of propagation delays,, a circuit output may momentarily go to 0 when it should remain a constant 1, we say that the circuit has a static 1-hazard. Static 0- hazard: If, in response to any single input change and for some combination of propagation delays,, a circuit output may momentarily go to 1 when it should remain a constant 0,, we say that the circuit has a static 0-hazard. Static 0 Review units

76 Hazards in Combinational Logic Dynamic hazard: If, when If, when output is supposed to change from 0 to 1 (or 1 to 0), the output may change three or more times,, we say that the circuit has a dynamic hazard. Review units

77 Hazards in Combinational Logic Example: Circuit with a static 1-hazard Assume that each gate has a propagation delay of 10 ns. If A=C=1, then F=B+B =1. =1. F should remain a constant 1 when B changes from 1 to 0. Review units

78 Hazards in Combinational Logic Procedure for detecting hazards in a two-level AND-OR circuit 1.Write down the SOP expression for the circuit. 2.Plot each term on the map and loop it. 3.If any two adjacent 1 s 1 s are not covered by the same loop, a 1-hazard 1 exists for the transition between the two 1 s. 1. For an n- variable map, this transition occurs when one variable changes and the other n-1 variables are held constant. Review units

79 Hazards in Combinational Logic Eliminating hazards Add a loop to cover two adjacent 1 s. 1 Review units

80 Hazards in Combinational Logic Example: A circuit with several 0-hazards0 F=(A+C)(A +D +D )(B +C +D) +D) Example: A=0, B=1, D=0, C changes from 0 to 1 Gate delay : 3 ns for NOT, 5 ns for AND/OR Review units

81 Hazards in Combinational Logic Example (cont.): Review units

82 Hazards in Combinational Logic Example (cont.): Review units

83 Hazards in Combinational Logic Example (cont.): Eliminating the 0 Eliminating the 0-hazards by looping additional prime implicants that cover the adjacent 0 s 0 s that are not covered by a common loop. F = ( A+ C)( A + D )( B + C + D)( C + D )( A+ B + D)( A + B + C ) Review units

84 Unit 9 Multiplexers, Decoders, and Programmable Logic Devices

85 Multiplexers Multiplexers (MUX( MUX,, or data selector) A MUX has a group of data inputs and a group of control inputs. The control inputs are used to select one of the data inputs and connect it to the output terminal. 2-to 1 MUX A=0, Z=I 0 A=1, Z=I 1 Z=A I 0 +AI 1 Review units

86 Multiplexers 4-to-1, 8-to8 to-1, 2 n -to-11 MUX Logic equation for 8-to8 to-1 1 MUX Z = + A B C I 0 AB C I A B CI 1 AB CI A BC I ABC I A BCI ABCI Review units

87 Multiplexers Logic Diagram for 8-to8 to-1 1 MUX Review units

88 Multiplexers Logic equation for 2 n -to-11 MUX Z = n 2 1 k= 0 m k I k m k where is a minterm of the n control variables and I k is the corresponding data input Review units

89 Multiplexers Quad Multiplexer Used to Select Data A=0, (z 0 z 1 z 2 z 3 )=(x 0 x 1 x 2 x 3 ) A=1, (z 0 z 1 z 2 z 3 )=(y 0 y 1 y 2 y 3 ) Review units

90 Multiplexers Quad Multiplexer with Bus Input and Output A=0, Z=X A=1, Z=Y Review units

91 Three-State Buffers A gate output can only be connected to a limited number of other device inputs without degrading the performance of a digital system. A buffer may be used to increase the driving capability of a gate output. F = C Review units

92 Three-State Buffers A logic circuit will not operate correctly if the outputs of two or more gates or other logic devices are directly connected to each other. Use of three-state logic permits the outputs of two or more gates or other logic devices to be connected together. Review units

93 Three-State Buffers Three-state buffer (Tri-state buffer) Enable input B=1, output C=A, when B=0, C acts like an open circuit,, C is effectively disconnected from the buffer output so that no current can flow. This is referred to a Hi-Z Z (high-impedance) impedance) state of the output because the circuit offers a very high resistance or impedance to the flow of current. Review units

94 Three-State Buffers Data Selection Using Three-State Buffers D=B A+BC Review units

95 Three-State Buffers Circuit with Two Three-State Buffers Review units

96 Three-State Buffers Three-state Bus A bus is driven by three-state buffers 4-Bit Adder with four sources for one operand Use a 4-to4 to-1 1 MUX to select one of several sources Set up a three-state bus Review units

97 Three-State Buffers Bi-directional I/O Pin Buffer is enabled, Output Buffer is disabled, Input Review units

98 Decoders and Encoders Decoder Generates all of minterms Exactly one of the outputs lines will be 1 for each combination of the values of the input variables. 3-to-88 Decoder Review units

99 Decoders and Encoders 4-to-10 Line Decoder with Inverted Output Review units

100 Decoders and Encoders 4-to-10 Line Decoder Review units

101 Decoders and Encoders n-to-2 n line decoder Generate all 2 n minterms (or maxterms) ) of the n input variables Outputs Noninverted y i =m i, i=0,1,2,,2,2 n -1 Inverted y i =m i =M i, i=0,1,2,,2,2 n -1 Review units

102 Decoders and Encoders Use decoder and gates to realize a function Example: Realize the following functions using a decoder. Example: f f 1 2 ( a, b, c, d) ( a, b, c, d) = = m 1 m m 2 m 7 + m4 + m 9 Sol: f f 1 2 = = ( m m m 1 ) ( m m m ) Review units

103 Decoders and Encoders Sol: f f 1 2 = ( m m m ) = ( m m m ) 9 Review units

104 Decoders and Encoders Encoder The inverse function of a decoder 8-to-33 Priority Encoder Review units

105 Read-Only Memories Read-Only Memory (ROM) Consists of semiconductor devices that interconnected to store binary data Review units

106 Read-Only Memories A n m ROM can realize m functions (F 1,F 2, F n ) of n variables. A ROM consists of a decoder and a memory array. 2 m Review units

107 Read-Only Memories Multiple-output combinational circuits can be realized using ROMs. Example: Realize the following functions using ROM. Review units

108 Read-Only Memories Sol: Review units

109 Read-Only Memories Example: Design a Design a code converter that converts a 4-bit 4 binary number to a hexadecimal digit and outputs the 7-bit 7 ASCII code. Review units

110 Read-Only Memories Sol: Because A 5 = A4, A6 = A 4, the ROM needs only five outputs. The ROM size is 16 words by 5 bits. The decoder is a 4-to4 to-16 decoder. Review units

111 Read-Only Memories Types of ROMs Mask-programmable ROMs Programmable ROMs (PROMs( PROMs) Electrically Erasable Programmable ROMs (EEPROMs,, E 2 PROMs) Flash memories Flash memory has built-in in programming and erase capability so that data can be written to it while it is in place in a circuit without the need for a separate programmer. Review units