First Commercial Demonstration of an Emerging Memory Technology for Embedded flash using CBRAM

Transcription

1 adesto TECHNOLOGIES First Commercial Demonstration of an Emerging Memory Technology for Embedded flash using CBRAM P. Blanchard, C. Gopalan, J. Shields, W. Lee, Y. Ma, S. Park, B. Guichet, S. Hsu, T. Gallo, F. Koushan, J. Saenz, D. Wang, V. McCaffrey, C. Chen, V. Gopinath, E. Runnion, V. Gopalakrishnan, J. Wang, and S. Hollmer Adesto Technologies Corbeil Essonne, France Tel: Innovative Memory Technologies Workshop 2011 MINATEC, Grenoble - France

2 Outline CBRAM Principle Adesto CBRAM Development Update Development of a learning vehicle and product validation Manufacturability demonstration Adesto CBRAM Performance Reliability results Conclusions 2

3 Operation Physical Principles for CBRAM The operational principle of Conductive Bridging RAM technology Based on a reversible creation of an electrochemically induced nanoscale conductive link Occurs in a special dielectric acting as a ion conducting solid-electrolyte In its simplest implementation, the basic storage element consists of an access transistor and a programmable resistor (1T1R) BL WL SL or Anode + V read + V read Ag Resistance High enough is determined reverse bias by will the high restore resistance the original of 3 Chalcogenide OFF state. Data 0 dielectric. is now re-written This state represents into the cell. Data 0 R > 1 GΩ 1 R > 1 GΩ W 0 V Ag W 0 V After write operation, a low resistance path is formed between the top and the bottom electrode. Data 1 has been written to the cell. R < 10KΩ Ag W Ag + 0 V + V erase Reversing the polarity to the cell erases the data and removes the metallic electrodeposit. The original state can be recovered Ag W Ag + + V prog 0 V During write operation, ions from top electrode get injected into the dielectric and are reduced to metallic form Ag W + V prog Ag + 0 V 3

4 Adesto s Commercializing March Yielding 1Mb Devices > 20% Die Yields Production Ramp Yield Improvement > 80% Bit Yields Partnership with Early Adopters Design of First Product. CMOS Integration Completed Manufacturing Bring Up More Than 90% Die Yields Consumer Reliability Specs Customer Samples 2007 Research 2008 Engagement with ALTIS 1 st Functional Silicon Devices Adesto Founded Achieving a Critical Milestone in 3 Years Build on Innovation and Move To Market 4

5 Development of a learning vehicle and product validation Adesto has developed a design based on 130 nm technology with a Cu BEOL The main features are : 1Mb EEPROM/Flash Macro on Standard Foundry 130nm (Cu BEOL) Programmable elements requires 2 non critical masks in BEOL steps Cell size determined by access device / Core cell will scale with CMOS. 5

6 Cu integration and manufacturability demonstration Integration of the CBRAM cell in a copper BEOL: No impact on the core process Confirmation of no Ag cross contamination from our manufacturing partner (validation of our previous study on the cross contamination) Product introduction in the fabrication line with defect density control and electrical tests (95% of the operations are under manufacturing controls) 6

7 CBRAM Cell Architecture and Operation Read Program Erase BL=1.3V BL=0.2V BL=1.5V VAN=1.5V VAN=1.5V VAN=0V WL=2.5V WL=2.5V WL=2.5V Read time: 20ns Program time: 100ns Erase time: 250 ns 7

8 Performance Adesto EEPROM Example of Image Captured and Stored on Adesto s CBRAM Device Key Advantages of Embedded CBRAM: Ultra Fast Program/Erase Speeds (10x faster than today s flash) Ultra Low Power Program/Erase (10x lower power than today s flash at 100x lower energy) Low cost memory solution for embedded and discrete applications (less than 1/3 the cost of today s flash) High Endurance of >10 5 Memory Write cycles 8

9 Time to Program With appropriate selection of operating algorithms and conditions, uniform and fast Time to Program across cycling can be achieved (Note: 1E-7 sec is the tester limitation) 9

10 Cycling from 1Mb Array ON State Cycle 100 OFF State > 400 Resistance Bin (kilo-ohms) ON State Cycle 50,000 OFF State > 400 Resistance Bin (kilo-ohms) No Degradation Observed After Endurance Using Standard 10

11 1Mb Array 100K Cycling and Process Dependence 100% 90% 80% CBRAM Stack Optimization is critical in achieving good cycling yield Functional Yield (%) 70% 60% 50% 40% 30% Process A Process B Process C Process D Process E Process F Process G 20% Process H 10% 0% 100 1,000 10, ,000 Cycle Number 11

12 10 6 W/E Cycling Demonstration Dependence on Algorithms and Process Splits CBRAM Stack Split 1 CBRAM Stack Split 2 Individual Cycle Yield % Erase Yield Program Yield Erase Yield Program Yield Demonstration of 1 million W/E cycles. Illustrating the importance of algorithms and stack module process 12

13 Consumer Spec Reliability Demonstrated Reliability models have been developed to predict end of life behavior of CBRAM Technology. Our work has guided us on process, device and design improvements to achieve consumer spec reliability. Special algorithms improve yield and reliability of our 1Mb Device: ALGO 1: 1 part per 1000 parts failure for 10 70C ALGO 2: Less than 1 part per 1,000,000 parts failure for 10 70C Sufficient reliability for consumer spec reliability (market entry target) 13

14 Future Cell Structure Options for Adesto s CBRAM NOTE: Adesto s focus has been to minimize risk by focusing cell concept with the lowest barrier cell for implementation. BL WL SL or Anode BL ANODE Cathode WL NMOS Access Device Diode Access Device Logic Rules DRAM Rules Logic Rules Effective Cell Size (Single Level Cell) Effective Cell Size (2 Levels Per Cell) Effective Cell Size (4 Levels Per Cell) Application Best Suited 15F 2 to 20F 2 8F 2 to 6F 2 8F 2 to 10F 2 4F 2 to 3F 2 4F 2 to 5F 2 2F 2 to 1.5F 2 NOR Flash, ULP DRAM Embedded Flash or DRAM 4F 2 2F 2 1F 2 NAND and Mass Storage Can do stackable cell to reduce cell size even more 14

15 Conclusions Significant progress towards CBRAM production CBRAM is ideal memory for embedded solutions High speed, low power sense design Optimized design for CBRAM writing CBRAM reliability passed threshold for product introduction Adesto continues R&D to make CBRAM fit EEPROM, high reliability and DRAM applications 15

16 Acknowledgements Adesto Design and Product/Test Engineering Teams Altis Design Team and Altis CBRAM Team 16