Charge-trap memories with high-k control dielectrics
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1 Charge-trap memories with high-k control dielectrics Gabriel Molas CEA-LETI MINATEC Advanced Memory Technology G. Molas Workshop on Innovative Memory Technologies June 24 th
2 Outline Context Charge trap memories with high-k control dielectrics Modelling and simulation Conclusions G. Molas Workshop on Innovative Memory Technologies June 24 th
![Year of production NAND Flash Technology [nm] Cell type Floating gate NAND Interpoly Interpoly](/docs-images/80/80884468/images/3-0.jpg "thickness [nm] Context TANOS NAND 2007 51 FG ONO 10-13 2008 45 FG ONO 10-13 2009 40 FG ONO")
3 Year of production NAND Flash Technology [nm] Cell type Floating gate NAND Interpoly Interpoly thickness [nm] Context TANOS NAND FG ONO FG ONO FG ONO FG/CT ONO CT ONO CT High-k CT-3D High-k CT-3D High-k 9-10 ITRS 2007 envisages High-k interpoly combined with charge trapping (CT) layers for sub-30nm nodes to maintain high coupling ratio and good reliability Samsung TANOS (TaN / Al 2 O 3 / Si 3 N 4 / SiO 2 / Si) memory envisaged for sub-30 nm (resistance to SILC, low cell to cell X coupling ) CT-3D High-k 9-10 TANOS 63nm SAMSUNG IEDM 05 TANOS 40nm SAMSUNG IEDM 06, VLSI 06 G. Molas Workshop on Innovative Memory Technologies June 24 th
4 Context - Embedded charge traps 1T SONOS + high-k dielectrics Nitride charge trap memory Reduction of the programming voltages (high-k tunox and topox) Split gate SONOS Reduction of the programming consumption (SSI instead of CHE) MG AG R. v. Schaijk, NVSMW 2006, NXP LETI program in progress Patent US 2008/ , K. YASUI et al., Nov. 2008, RENESAS LETI program in progress G. Molas Workshop on Innovative Memory Technologies June 24 th
5 Outline Context Charge trap memories with high-k control dielectrics High-k Control dielectric optimization Nitride thickness Metal gate Modelling and simulation Conclusions G. Molas Workshop on Innovative Memory Technologies June 24 th
6 Optimization of charge trap memories SANOS-like memories High-k Control dielectric - Study of various high-k materials - Introduction of a SiO 2 interlayer Nitride thickness Impact of the nitride thickness on the memory retention 16nm Al 2 O 3 50nm 5.5nm 3.5nm Si 3 N 4 SiO 2 Control gate Comparison of various gate types on the erasing characteristics G. Molas Workshop on Innovative Memory Technologies June 24 th
7 High-k control dielectrics - HfAlO HfO 2, Al 2 O 3, and HfAlO deposited by ALCVD (H 2 O, TMA and HfCl 4 precursors) in ASM PULSAR 2000 tool used as control dielectrics Optical Bandgap [ev] Eg = [Hf] Al 2 O 3 HfO 2 Hf fraction Bandgap: HfO 2 < HfAlO < Al 2 O Stress Time [s] G. Molas Workshop on Innovative Memory Technologies June 24 th V T [V] V G : 10V 14V Programming speed: HfO 2 > HfAlO > Al 2 O 3 Tuning the memory characteristics with the Hf:Al ratio HfO 2 HfAlO Al 2 O 3
![High-k control dielectrics - HTO / Al 2 O 3 bilayer SANOS 100% HTO/Al2O3 EOT 4/8 nm => 7.3nm Al 2 O 3 V T / V T,t=0s [-] 90% Al2O3 EOT 16 nm => 6.6nm 20nm => 8.](/docs-images/80/80884468/images/8-1.jpg "2nm Poly-Si Al 2 O 3 HTO SAONOS Al 2 O 3 HTO 80% Si 3 N 4 SiO 2 10 2 10 4 10 6 10 8 Retention time [s] Same EOT HTO/Al 2 O 3 bilayers enable improved retention for the same EOT (so with no")
8 High-k control dielectrics - HTO / Al 2 O 3 bilayer SANOS 100% HTO/Al2O3 EOT 4/8 nm => 7.3nm Al 2 O 3 V T / V T,t=0s [-] 90% Al2O3 EOT 16 nm => 6.6nm 20nm => 8.2nm Poly-Si Al 2 O 3 HTO SAONOS Al 2 O 3 HTO 80% Si 3 N 4 SiO Retention time [s] Same EOT HTO/Al 2 O 3 bilayers enable improved retention for the same EOT (so with no degradation of the programming voltages) M. Bocquet et al., SSE 2009 G. Molas Workshop on Innovative Memory Technologies June 24 th
9 Impact of the nitride thickness V T / V Tinit [% ] Si 3 N 4 : 3nm 6nm 10nm Nitride layer Retention Time [s] T=25 C 10 5 Si 3 N 4 3nm 6nm nm HT : no difference G. Molas Workshop on Innovative Memory Technologies June 24 th Life Time (@ V T / V Tprog =95%) Thick Si 3 N 4 Better retention 1/kT [1/eV] Nitride thickness mostly impacts the retention at RT: Same retention behavior at high temperature RT : difference data retention Si 3 N 4 3nm 6nm 10nm M. Bocquet et al., IMW 2009
10 Impact of the control gate on erasing V T - V To [V] Poly N+ Poly P+ V G =-18V Blocking Oxide: HTO / Al2O3 V G =-12V Stress time [s] M. Bocquet et al., ESSDERC 2008 Same speed between P+/N+ poly-si gate Poly - Si N+ / P+ Al 2 O 3 HTO Si 3 N 4 V T saturation appears for N+ type gate at high voltages P+ poly-si gate: limited erase saturation G. Molas Workshop on Innovative Memory Technologies June 24 th h+ e- Control Gate SiO 2 8nm 5nm 6nm 2.5nm
11 Collaboration with Aixtron Metal gate Deposition of TaN and TaAlN gates (AVD ) on ANOS stacks Midgap metal gates reduce erase saturation with respect to N+ gates G. Molas Workshop on Innovative Memory Technologies June 24 th
12 Outline Context Charge traps memories with high-k control dielectrics Modelling and simulation Nitride ab-initio Device physical modelling Device TCAD simulation Conclusions G. Molas Workshop on Innovative Memory Technologies June 24 th
13 Ab-initio: SiN Band-gap calculations Objectives: Study of the origin of charge trapping in SiN layers Consideration of defects: N and Si vacancies, saturated with H species (measured by MIR) Are the defects electrically active (e- energy states in the gap)? β phase E. Vianello, P. Blaise et al. G. Molas Workshop on Innovative Memory Technologies June 24 th
14 x V G Poly-Si Device physical modelling [E. Vianello, ESSDERC 2008] Al2O3 Si3N4 SiO2 (1) Tunnel-In (FN, DT, mfn, B-T) J in (1) program V G >>0 x (2) J out (3) (2) Electron transport + capture/emission Motion of electrons in SiN:Drift-Diffusion Interaction between the electrons in the CB and in the energy gap Emission rate (Poole-Frenkel) J out retention V G =0 J out (3) (2) (3) (3) Tunnel-Out G. Molas Workshop on Innovative Memory Technologies June 24 th
15 4x10 19 Retention at high temperature: Nitride charge distribution Trapped charge Trapped density charge [1/cm density 3 ] [1/cm 3 ] Immediately After programming 2x T=250 C x10 19 Nitride thickness [nm] Si Jout e- SiO 2 Si 3 N 4 Jout Al 2 O 3 Gate During retention 2x10 19 Jout e- Jout T=250 C T=250 C Si Nitride thickness [nm] SiO 2 Si 3 N 4 G. Molas Workshop on Innovative Memory Technologies June 24 th Al 2 O 3 Thermal emission in Si 3 N 4 Trapped charge redistribution Quick migration to SiO 2 and Al 2 O 3 interfaces Small retention difference between thin and thick SiN Gate M. Bocquet et al., IMW 2009
16 Drain Current Id [ua/um] TCAD: SONOS Split gate architectures Simulated structure defined using Synopsis tool E-3 Memory gate bias AG MG Vd=5V Vg2= 0V 2V 4V 6V 8V 10V Access Gate Voltage Vg1 [V] LETI program in collaboration with STM E. Nowak et al. In programming mode: Vg1=1V: Id limited by the conduction in the access transistor (weak inversion). Low consumption. Vmg=9V: generates the vertical electric field for SSI G. Molas Workshop on Innovative Memory Technologies June 24 th
17 Outline Context Charge traps memories with high-k control dielectrics Modelling and simulation Conclusions G. Molas Workshop on Innovative Memory Technologies June 24 th
18 Conclusions 1/2 Charge trap memories with high-k control dielectrics High-k control dielectrics engineering of SANOS HfAlO: by tuning the Hf/Al concentration of HfAlO alloys, a good compromise can be achieved in terms of: Coupling ratio (ε): good PE speed with Hf-rich samples Insulating capabilities: high bandgap, low E A with Al-rich samples Thermal stability (crystallization T ): increases w ith %Hf Improvement of SANOS memory retention by using a HTO/Al 2 O 3 control dielectrics double layer Impact of nitride thickness on retention Retention at room temperature increases with SiN thickness Thickness dependance disappears at high temperatures Impact of control gate on erasing Metal (TiN, TaN, TaAlN) an P+ control gates reduce erase saturation at high voltages G. Molas Workshop on Innovative Memory Technologies June 24 th
19 Modelling and simulations Conclusions 2/2 Ab-initio simulations of nitride layers (DFT, GW) Evaluation of the intrinsic properties of nitride (bandgap, impacts of defects on electrical traps ) Simulation hypotheses based on physical and morphological characterisation of nitride layers Physical modelling of nitride memories based on drift diffusion in nitride Quantitative description of the charge redistribution in nitride at high temperature during retention TCAD simulations allow to evaluate the potentiality of new architectures Reduced consumption in SONOS split gate memories in comparison with 1T architectures G. Molas Workshop on Innovative Memory Technologies June 24 th
20 Acknowledgments B. De Salvo (leader of the advanced memory activity), M. Bocquet, E. Vianello, J. P. Colonna, M. Gély, E. Nowak, L. Perniola, H. Grampeix, P. Blaise, P. Brianceau, F. Martin, C. Licitra, N. Rochat, E. Martinez, A. M. Papon, H. Dansas, P. Besson, P. Scheiblin, V. Vidal, A. Toffoli, R. Kies, G. Ghibaudo, G. Pananakakis, O. Boissière LETI cleanroom facilities CEA-LETI MINATEC Grenoble, France IU.NET, Udine, Italy CNRS IMEP Grenoble, France Aixtron, USA G. Molas Workshop on Innovative Memory Technologies June 24 th
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