Interface Degradation of Al Heavy Wire Bonds on Power Semiconductors during Active Power Cycling measured by the Shear Test

Transcription

1 Interface Degradation of Heavy Wire Bonds on Power Semiconductors during Active Power Cycling measured by the Shear Test Jens Goehre, Fraunhofer IZM, Berlin, Germany Martin Schneider-Ramelow, Fraunhofer IZM, Berlin, Germany Ute Geißler, Berlin University of Technology, Berlin, Germany Klaus-Dieter Lang, Fraunhofer IZM, Berlin, Germany Abstract Wire bonding is still the dominant interconnection technology for power semiconductors in power modules, e.g. for automotive or photovoltaic applications. In the past, many research activities have occurred in the field of reliability of power modules, where the life time of the complete module is affected by bond wire lift offs, heel cracks and other failures. Less effort was spent for investigating the degradation process at the wire bond itself. This paper addresses a new approach and focuses on the investigation of the cracks in the interface region between the die and the wire by using the shear test. These cracks form after several thousand temperature swings due to CTE mismatch and ultimately lead to wire bond lift off. New results of active power cycling with different temperature amplitudes and medium temperatures will be discussed. Shear tests have been carried out in regular intervals to monitor the degradation of the 4 µm wire bonds on power MOS-FETs. It was found out that the rate of the shear force reduction was mostly dependent on the amplitude of the temperature cycling. A significant effect of different medium temperatures could not be identified. These results will contribute to the development of an enhanced life time model for heavy wire bonds on power semiconductors. 1 Introduction One of the key challenges engineers have to face before releasing a power module design for production is the reliability of the electrical components and their electrical connections to the next integration level. Typical usage of power electronics, e.g. in an electrical car, results in a high number of different temperature cycles induced by electrical losses of the power semiconductors [1]. During the expected product life time of commonly more than 17 years in automotive applications these cycles easily sum up to several hundred thousand or even millions of cycles. For the electrical components not to fail too early the degradation rate for all possible failure mechanisms must stay below a critical value. Typical failures in power modules can be accounted to the formation of cracks in the following areas - Interface chip/substrate - Interface substrate/base plate - Heel of the wire bond - Interface wire bond/chip metallization The introduction of solder free packages by using the low temperature joining technique for the die attach and substituting the base plate and its solder technology by a pressure contact design has led to a situation in which the reliability of the wire bond is now the main lifetime determining factor [2, 3, 4]. Most of the past research in this field has concentrated on the module life time. Modules are comprised of multiple dies which are bonded with a high number of wires. Failures were mostly defined by a change of electrical parameters by a certain amount. A typical failure criterion for power cycling experiments on IGBT modules is a 5% increase of V CE,sat [5, 6]. This failure criterion was met when a certain number of wires had failed. So only the final result of the degradation but not the degradation process itself had been studied in most of the cases. 2 Failure Mechanism It is goal of this work to investigate the degradation in the interface region between the wire bond and the chip. The interface is formed during ultrasonic wire bonding of the wire onto the metallization of the chip. The main parameters of this process are the ultrasonic power, bond force and bond time. During the bonding process hardening and softening effects take place in the wire material near the interface. The applied bonding force leads to a large degree of deformation which increases the dislocation density and therefore contributes to a hardening. The ultrasonic energy on the other hand leads to dynamic recrystallization so that a softening effect can be observed. Depending on the bond parameter setting and the properties of the wire and metallization material the hardening or the softening effect is prevailing. [7] and [8] are describing this process in more detail for thin wire 1 bonds on Ni/Au metallizations. Wire and chip material ( and ) show a significant difference in their thermal expansion behavior (see Coefficient of Thermal Expansion (CTE) in Table 1). Considering both materials in unbonded state, the expansion and

2 contraction of the is roughly 8 times higher than that of the. nce both materials are interconnected at the bond interface their free expansion is limited. This leads to a situation in which thermo-mechanical stresses and strains occur. Under this condition shows a very ductile behavior with low yield stress (Table 1) while behaves brittle. Table 1 Selected material properties Material Property Unit CTE /K Youngs Modulus E GPa Yield Stress y 2 MPa To gain a basic understanding of the strains in the interface region a simple 2-layer model and an analogy to the uniaxial tension test is used, Figure 1. th el pl Figure 1 Model of an / interface heating up Directly at the interface and are joined together. In a free state they would expand differently when heated up due to their different CTEs ( th, dottet symbols). Because of the fact that they are joined together strains occur in the of the chip and the of the wire. nce behaves brittle this strain is only elastic. The strain in the is the sum of elastic and plastic parts. Assuming elastic material behavior for the, elastic/ideal plastic material behavior for the and setting the total strain in the equal to the one in the plastic strains per cycle in the can be estimated y y 2 (1) pl th el T E E The formula states, that the plastic strain is the difference in thermal strain minus the elastic deformation of and. With the assumption of the elastic/ideal plastic material law, the maximum stress that can arise in either the or the is the yield stress of the. Of course, the real stresses and strains can only be calculated by considering the real geometries and the correct material properties. nce it is actually a multi-axial state of stress and realistic material laws for ductile metals are non-linear an analytical model of the real stresses and strains is not available. These values can be calculated by numerical methods such as FEM. It is known that periodic plastic strains in metals damage the material [9, 1] so that after a certain number of cycles the interface is destroyed and the wire lifts off. A lift off of a single wire will increase the current load for the remaining wires leading to more self heating and a further increase in the temperature excursions and an acceleration of the degradation process. If all wires have lifted or the current capability of the remaining wires is exceeded the device will fail. The degradation takes place in the form of crack growth from either end of the interconnected area towards the center of the bond, Figure 2. Figure 2 Cross section of a bond showing cracks growing from either end of the wire towards the center of the bond Even with optimized bond parameters the interconnected area in the interface is commonly below 1% of the complete area. In addition, oxides from the wire and the chip metallization surfaces are accumulated locally during the bond process and built into the interface. So the weakest spot and therefore the preferred crack path is expected to be the bond interface itself. As can be seen in Figure 3 the crack does not advance directly in the bond interface but in the wire material approximately 1-2 µm above the interface. interface crack Figure 3 Crack grows 1-2 µm above the bond interface An explanation for this can be given by recalling the hardening and softening processes that take place during bonding and by analyzing the microstructure in the interface region in Figure 4. The picture was taken by FIB (Focused Ion Beam) imaging and shows that there are 3 different zones. The first zone is the metallization of the chip. Bonding force and ultrasonic energy have resulted in high degree of deformation and dynamic recrystallization. In unbounded state the chip metallization layer (5 µm) is one grain thick. After the bond process this layer consists of multiple grains with grain size less than 1 µm. The second zone is the one between the bond interface and the crack. Here the grains of the wire material were exposed to the bond parameters and recrystallized to a size of chip metallization

3 approximately 1 µm. Both zones are characterized by a high degree of deformation. In the third zone, above the crack, the grains are much bigger. These are the original grains of the wire material which were deformed but did not recrystallize. The correct size cannot be estimated from the image. wire interface Figure 4 Microstructure in the interface region The crack travels along grain boundaries in an area between zone 2 and zone 3. though this area is 1-2 µm away from the interface, which means that the area of CTE mismatch is approximately one layer of grains away, it is still the path with the least effort for crack propagation. The reason for that is not completely understood but most likely due to a prevailing hardening effect in the region below the crack path. This however needs to be verified in future measurements. More details on this can be found in [11]. Assuming that in most cases the crack path will be above the first layer of grains in the wire material and that the damaging plastic strains become smaller with a greater distance from the interface it should be possible by increasing the grain size of the first layer of grains to decrease the crack propagation rate and therefore enhance the reliability. This has been investigated and confirmed in [12, 13]. 3 Experiment crack chip metallization The specimen consisted of power MOS-FETs (Infineon CoolMOS, 5 µm 1Cu.5 metallization) glued with electrically conductive adhesive to a DCB substrate. The chips were bonded with 4 µm heavy wire (Heraeus -H11, 25 bonds per chip), Figure 5. Initial quality was optimized by shear tests. During the shear test a shear tool is shearing through the bond at a defined height (1% of wire diameter) above the interface. The measured shear force and the coverage of the shear site with wire material were recorded. The optimized bonds had an average shear force of 27 cn and a standard deviation of 13 cn. The complete shear site was covered with wire material (shear through, Figure 6a). The specimen were mounted on a water cooler (1 C) and heated by the electrical losses of the semiconductor (active power cycling). The test bench was designed in the way that the minimum and maximum temperature of each cycle was constant. Heating times were fixed to 1.8 seconds. The exact cycling period was dependent on the time for cooling. Typical cycling periods were in the range of 3 seconds. More details about the self developed test bench can be found in [14]. Table 2 shows an overview about the different experiments and their settings. Table 2 Overview over experiments Experiment T min T max T med T Gamma pha Delta Epsilon Zeta Eta There were two groups of experiments. The first group (Gamma, pha, Delta, Epsilon) had different temperature swings while the medium temperature T med = ½(T min +T max ) stayed the same. This group was used to study the effects of the temperature swing amplitude. The second group (Epsilon, Eta, Zeta) had the same amplitude but different medium temperatures. This group was used to study whether it makes a difference to cycle at a lower or a higher medium temperature. After a defined number of cycles the specimen were removed from the test bench and all 25 wires of one chip were tested destructively by the shear test. Decreasing shear forces and decreasing coverage of the shear site with wire material were an indicator for the advance of the cracks, Figure 6. Figure 5 Specimen consisting of MOS-FET, DCB and 4 µm wire bonds a) b) Figure 6 Shear site a) in initial state and b) after 1, cycles T= 6 K

4 4 Results 4.1 Effect of Temperature Amplitude At first, the effects of the temperature amplitude have been studied, Figure 7. The initial bond quality was the same for all experiments. In all experiments the measured shear force decreases with increasing numbers of cycles. The decrease rate is dependent on the temperature amplitude. Higher temperature amplitudes lead to a faster decrease. Average Shear Force [cn] Figure 7 Shear Force vs. Number of Cycles for different temperature amplitudes After the shear test, some specimens were used to measure the sheared area. Figure 8 shows the results. The sheared area is decreasing with increasing number of cycles. This leads to the conclusion that the decrease of the shear force is due to the fact, that the growing cracks decrease the intact interface area and therefore the area that can withstand the shear test (see also Figure 6b). Average Sheared Area [µm²] Epsilon (6/12) Delta (5/13) pha (4/14) Gamma (3/15),,2,4,6,8 1, Number of Cycles [1 6 ] Epsilon (6/12) Delta (5/13) pha (4/14) Gamma (3/15),,1,2,3,4 Number of Cycles [1 6 ] Figure 8 Sheared Area vs. Number of Cycles for different temperature amplitudes At this point, it is important to note that the fact that the shear test leaves no shear remains in an area does not necessarily mean that this area was already completely unconnected. It just means that the cracks have weakened it enough to cause a lift off during the shear test. For conducting electrical current and for mechanical stability there may still be a sufficient amount of connected spots. In this case the device would function without any noticeable changes in electrical parameters. The previous approaches for life time modeling, which in most cases used electrical parameters for the definition of a failure criterion, would not be sensitive to this part of the degradation process. In Figure 9 the sheared area is plotted versus the measured shear force. In the graph it can be seen that there were numerous points where no shear remains were left but significant shear forces were measured. This supports the statement that between intact interface area and completely unconnected area there is a state where the interface is weakened but is not yet unconnected. In this state the interface can withstand significant shear forces but at the same time it is the place where the wire breaks during the shear test so that no shear remains are generated. A similar effect is known from wire bonds that were insufficiently welded due to not optimized bond parameters or contaminations on the surfaces of the wire or chip metallization. These bonds very often show high shear forces but no shear remains. Further investigations are required to describe the forces acting during the shear test in more detail. Apart from that, the shear force and the sheared area show a linear correlation. The slope and y-intercept of this curve did not show a dependence on the numbers of cycles or the temperature settings of the cycling test. Shear Force [cn] Figure 9 Shear Force vs. Sheared Area R² =, Sheared Area [1³ µm²] The linear correlation between sheared area and measured shear force gives the opportunity to use the shear force (Figure 7) for the definition of a failure criterion as long as shear remains are greater zero. Selecting a minimum shear force of 5% of the initial value leads to the lifetimes listed in Table 3. Table 3 Life time of wire bonds using the 5% criterion Experiment T [K] pl [%] Cycles to failure N f Gamma ,24 pha ,751 Delta ,95 Epsilon ,671

5 Plastic strains per cycle calculated on the base of Formula 1 are also inserted in Table 3. For this calculation the material properties of Table 1 were used. With a linear fit of the logarithms of N f and pl (Figure 1) the parameters for a plain Coffin-Manson relationship [9, 1] can be derived which leads to the following expression for the lifetime of the wirebond: N f N f pl y =,389x 1,764 R² =,998 1.,1%,1% 1,% pl Figure 1 Cycles to failure vs. calculated plastic strains per cycle With this equation the lifetime for the wire bonds can be calculated. Currently, the parameters of the equation are only valid for the wire bonds that were investigated for this publication. Switching to a different wire size, a different wire material, a different bonding machine or changing any other parameter, e.g. bond parameters, will most likely result in different lifetimes. It is a goal for future investigations to be able to distinguish between the effects on the life time of these important parameters and to incorporate them into an enhanced lifetime model. As a first step, the effect of the medium temperature on the lifetime of the wire bonds should be studied (see next section). By fitting the sheared area values of Figure 8 to a linear function the area decrease rate in µm²/cycle or % of original area/cycle can be calculated, Figure 11. Area Decrease Rate [µm²/cycle], 1, 2, 3, 4, 5,,%,4%,7%,11%,15%,18% 6,,22% Temperature Swing [K] Figure 11 Area decrease rate for different temperature swings Area Decrease Rate [%/cycle] This is the rate in which the area that withstands a shear test is decreased. This rate in combination with a failure criterion based on the minimum acceptable area of shear remains can also be used as a convenient way to calculate the expected lifetime of a wire bond. 4.2 Effect of Medium Temperature It has been shown in the LESIT project that the number of cycles to failure for complete modules is also dependent on the medium temperature of the temperature cycles [6]. However, in these investigations the degradation process of the wire bond is not treated separately. nce failure is commonly defined as a 5% increase in V CE,sat the degradations on the metallization and the solder interface also have an effect. In addition, both of these effects may accelerate the degradation at the wire bond by increasing the peak temperature of the die. As a conclusion it can be stated that if the medium temperature has an effect on metallization and solder interface degradation mechanisms it will automatically affect the measured wire bond lifetime. In this work the wire bond failure is isolated from other effects. This is achieved by assuring that the temperatures T min and T max remain constant for all cycles even if the chip metallization or the die attach start to degrade. In this case, the current flowing through the devices is automatically slightly adjusted so that the temperature cycles stay at the same level. The result of the power cycling experiments is depicted in Figure 12, which shows the measured shear force versus the number of cycles for 3 different medium temperatures. The amplitude of the temperature cycles was the same. The curves show no distinct difference. A dependence on the medium temperature under the described conditions can therefore not be confirmed. Average Shear Force [cn] Zeta (3/9) Epsilon (6/12) Eta (9/15),,2,4,6,8 1, Number of Cycles [1 6 ] Figure 12 Shear Force vs. Number of Cycles for different medium temperatures

6 5 Summary Power cycling experiments have been carried out with 4 µm wire bonds on power semiconductors. The degradation of the wire bonds was monitored by using the shear test to destructively measure the shear force that the cycled bonds can withstand in regular intervals. This is a different approach compared to most previous investigations, where only the final result of the degradation, a lift off, was evaluated. It could be shown that the shear forces decrease with increasing number of cycles and that there is a strong dependence on the magnitude of the temperature swing but no dependence on the medium temperature of the cycles. Using a simple analytical thermo-mechanical model the plastic strain ranges for the experiments were analytically calculated and fitted to the number of cycles to failure. The failure criterion was a 5% decrease of the shear force. This resulted in the extraction of the parameters for a Coffin-Manson based lifetime model for wire bonds. The separation of the wire bond degradation from other degradation processes in a power module allows a deeper understanding of the life time limiting factors of power electronics. In order to reach the goal of an enhanced lifetime model for wire bonds technology parameters such as wire size, bonding parameter and exact material properties will be included in future investigations. Acknowledgments The authors would like to thank Mr. Christian Wald from Infineon Technologies AG for providing the semiconductors. 6 References [1] Ciappa, M: Lifetime prediction on the base of mission profiles, Microelectronics and Reliability, Volume 45, Issues 9-11, Proceedings of the 16th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Sept/Nov. 25, pp [2] Amro, R.; Lutz, J.; Rudzki, J.; Thoben, M.; Lindemann, A.: Double-sided low-temperature joining technique for power cycling capability at high temperature, European Conference on Power Electronics and Applications, 25 [3] Rudzki, J.; Eisele, R.: Reliability of Ag ntering vs. Soldering, ECPE Workshop Mechatronic System Integration, Oct. 29 [4] Scheuermann, U.: Reliability challenges of automotive power electronics, Microelectronics Reliability, Volume 49, Issues 9-11, 2th European Symposium on the Reliability of Electron Devices, Failure Physics and Analysis, Sept/Nov 29, pp [5] Lutz, J.; Herrmann, T.; Feller, M.; Bayerer, R.; Licht, T.: Power cycling induced failure mechanisms in the viewpoint of rough temperature environment, European conference on power electronics and applications, 27 [6] Held, M.; Jacob, P.; Nicoletti, G.; Scacco, P.; Poech, M.H.: Fast Power Cycling Test for IGBT Modules in Traction Application, Proc. Power Electronics and Drive Systems, 1997 [7] Geißler, U.; Schneider-Ramelow, M.; Lang, K.-D.; Reichl, H.: Investigation of Microstructural Processes during Ultrasonic Wedge/Wedge Bonding of 1 Wires, Journal of Electronic Materials, 26, pp [8] Geissler, U.; Schneider-Ramelow, M.; Reichl, H.: Hardening and Softening in 1 Bond Contacts During Ultrasonic Wire Bonding, IEEE Transactions on Components and Packaging Technologies, Vol.32, No.4, pp , Dec. 29 [9] Coffin Jr, L.F.: A study of the effects of cyclic thermal stresses on a ductile metal, Trans ASME 76, 1954, pp [1] Manson, SS.: Behavior of materials under conditions of thermal stress, NACA TN, 2933, 1953 [11] Göhre, J.; Geißler, U.; Schmitz, S.; Schneider- Ramelow, M.: Analyse des Rissverlaufs in Dickdrahtbondverbindungen auf Leistungshalbleitern beim Active Power Cycling, PLUS 8/29, pp [12] Onuki, J.; Koizumi, M.; Suwa, M.: Reliability of thick wire bonds in IGBT modules for traction motor drives, IEEE Trans Adv Packag 23 (1), 2, pp [13] Wei-Sun Loh; Corfield, M.; Hua Lu; Hogg, S.; Tilford, T.; Johnson, C.M.: Wire Bond Reliability for Power Electronic Modules - Effect of Bonding Temperature, International Conference on Thermal, Mechanical and Multi-Physics mulation Experiments in Microelectronics and Micro-Systems, 27 [14] Lang, K.-D.; Goehre, J.; Schneider-Ramelow, M.: Interface Investigations and Modeling of Heavy Wire Bonds on Power Semiconductors for End of Life Determination, Electronics Packaging Technology Conference, 28